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Paul Mackerrasbbd0abd2005-10-26 21:45:56 +10001/*
2 * CHRP pci routines.
3 */
4
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +10005#include <linux/kernel.h>
6#include <linux/pci.h>
7#include <linux/delay.h>
8#include <linux/string.h>
9#include <linux/init.h>
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +100010
11#include <asm/io.h>
12#include <asm/pgtable.h>
13#include <asm/irq.h>
14#include <asm/hydra.h>
15#include <asm/prom.h>
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +100016#include <asm/machdep.h>
17#include <asm/sections.h>
18#include <asm/pci-bridge.h>
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +100019#include <asm/grackle.h>
20#include <asm/rtas.h>
21
Paul Mackerrasb86756a2006-04-03 16:37:23 +100022#include "chrp.h"
Kumar Gala33d71d22007-08-20 08:50:28 -050023#include "gg2.h"
Paul Mackerrasb86756a2006-04-03 16:37:23 +100024
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +100025/* LongTrail */
26void __iomem *gg2_pci_config_base;
27
28/*
29 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
30 * limit the bus number to 3 bits
31 */
32
33int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
34 int len, u32 *val)
35{
36 volatile void __iomem *cfg_data;
Kumar Gala84569932009-04-30 03:10:11 +000037 struct pci_controller *hose = pci_bus_to_host(bus);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +100038
39 if (bus->number > 7)
40 return PCIBIOS_DEVICE_NOT_FOUND;
41 /*
42 * Note: the caller has already checked that off is
43 * suitably aligned and that len is 1, 2 or 4.
44 */
45 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
46 switch (len) {
47 case 1:
48 *val = in_8(cfg_data);
49 break;
50 case 2:
51 *val = in_le16(cfg_data);
52 break;
53 default:
54 *val = in_le32(cfg_data);
55 break;
56 }
57 return PCIBIOS_SUCCESSFUL;
58}
59
60int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
61 int len, u32 val)
62{
63 volatile void __iomem *cfg_data;
Kumar Gala84569932009-04-30 03:10:11 +000064 struct pci_controller *hose = pci_bus_to_host(bus);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +100065
66 if (bus->number > 7)
67 return PCIBIOS_DEVICE_NOT_FOUND;
68 /*
69 * Note: the caller has already checked that off is
70 * suitably aligned and that len is 1, 2 or 4.
71 */
72 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
73 switch (len) {
74 case 1:
75 out_8(cfg_data, val);
76 break;
77 case 2:
78 out_le16(cfg_data, val);
79 break;
80 default:
81 out_le32(cfg_data, val);
82 break;
83 }
84 return PCIBIOS_SUCCESSFUL;
85}
86
87static struct pci_ops gg2_pci_ops =
88{
Nathan Lynchf1d645f2007-08-10 05:18:44 +100089 .read = gg2_read_config,
90 .write = gg2_write_config,
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +100091};
92
93/*
94 * Access functions for PCI config space using RTAS calls.
95 */
96int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
97 int len, u32 *val)
98{
Kumar Gala84569932009-04-30 03:10:11 +000099 struct pci_controller *hose = pci_bus_to_host(bus);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000100 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
101 | (((bus->number - hose->first_busno) & 0xff) << 16)
Kumar Gala5516b542007-06-27 01:17:57 -0500102 | (hose->global_number << 24);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000103 int ret = -1;
104 int rval;
105
106 rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
107 *val = ret;
108 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
109}
110
111int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
112 int len, u32 val)
113{
Kumar Gala84569932009-04-30 03:10:11 +0000114 struct pci_controller *hose = pci_bus_to_host(bus);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000115 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
116 | (((bus->number - hose->first_busno) & 0xff) << 16)
Kumar Gala5516b542007-06-27 01:17:57 -0500117 | (hose->global_number << 24);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000118 int rval;
119
120 rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
121 addr, len, val);
122 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
123}
124
125static struct pci_ops rtas_pci_ops =
126{
Nathan Lynchf1d645f2007-08-10 05:18:44 +1000127 .read = rtas_read_config,
128 .write = rtas_write_config,
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000129};
130
131volatile struct Hydra __iomem *Hydra = NULL;
132
133int __init
134hydra_init(void)
135{
136 struct device_node *np;
David Woodhouse575e3212006-01-14 00:13:49 +0000137 struct resource r;
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000138
Stephen Rothwell30686ba2007-04-24 13:53:04 +1000139 np = of_find_node_by_name(NULL, "mac-io");
140 if (np == NULL || of_address_to_resource(np, 0, &r)) {
141 of_node_put(np);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000142 return 0;
Stephen Rothwell30686ba2007-04-24 13:53:04 +1000143 }
Nicolas Palix29e931c2008-12-02 03:34:46 +0000144 of_node_put(np);
Joe Perches28f65c12011-06-09 09:13:32 -0700145 Hydra = ioremap(r.start, resource_size(&r));
Greg Kroah-Hartman685143a2006-06-12 15:18:31 -0700146 printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000147 printk("Hydra Feature_Control was %x",
148 in_le32(&Hydra->Feature_Control));
149 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
150 HYDRA_FC_SCSI_CELL_EN |
151 HYDRA_FC_SCCA_ENABLE |
152 HYDRA_FC_SCCB_ENABLE |
153 HYDRA_FC_ARB_BYPASS |
154 HYDRA_FC_MPIC_ENABLE |
155 HYDRA_FC_SLOW_SCC_PCLK |
156 HYDRA_FC_MPIC_IS_MASTER));
157 printk(", now %x\n", in_le32(&Hydra->Feature_Control));
158 return 1;
159}
160
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000161#define PRG_CL_RESET_VALID 0x00010000
162
163static void __init
164setup_python(struct pci_controller *hose, struct device_node *dev)
165{
166 u32 __iomem *reg;
167 u32 val;
David Woodhouse575e3212006-01-14 00:13:49 +0000168 struct resource r;
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000169
David Woodhouse575e3212006-01-14 00:13:49 +0000170 if (of_address_to_resource(dev, 0, &r)) {
171 printk(KERN_ERR "No address for Python PCI controller\n");
172 return;
173 }
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000174
175 /* Clear the magic go-slow bit */
David Woodhouse575e3212006-01-14 00:13:49 +0000176 reg = ioremap(r.start + 0xf6000, 0x40);
177 BUG_ON(!reg);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000178 val = in_be32(&reg[12]);
179 if (val & PRG_CL_RESET_VALID) {
180 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
181 in_be32(&reg[12]);
182 }
183 iounmap(reg);
David Woodhouse575e3212006-01-14 00:13:49 +0000184
Kumar Gala2e56ff22007-07-19 16:07:35 -0500185 setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000186}
187
188/* Marvell Discovery II based Pegasos 2 */
189static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
190{
Stephen Rothwell8c8dc322007-04-24 13:50:55 +1000191 struct device_node *root = of_find_node_by_path("/");
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000192 struct device_node *rtas;
193
194 rtas = of_find_node_by_name (root, "rtas");
195 if (rtas) {
196 hose->ops = &rtas_pci_ops;
Olaf Heringd60dcd92006-02-04 12:55:41 +0100197 of_node_put(rtas);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000198 } else {
199 printk ("RTAS supporting Pegasos OF not found, please upgrade"
200 " your firmware\n");
201 }
Josh Boyer7fe519c2008-12-11 09:46:44 +0000202 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
Stephen Rothwell8c8dc322007-04-24 13:50:55 +1000203 /* keep the reference to the root node */
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000204}
205
206void __init
207chrp_find_bridges(void)
208{
209 struct device_node *dev;
Jeremy Kerrae6b4102006-07-12 15:40:05 +1000210 const int *bus_range;
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000211 int len, index = -1;
212 struct pci_controller *hose;
Jeremy Kerrae6b4102006-07-12 15:40:05 +1000213 const unsigned int *dma;
214 const char *model, *machine;
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000215 int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
Stephen Rothwell8c8dc322007-04-24 13:50:55 +1000216 struct device_node *root = of_find_node_by_path("/");
David Woodhouse575e3212006-01-14 00:13:49 +0000217 struct resource r;
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000218 /*
219 * The PCI host bridge nodes on some machines don't have
220 * properties to adequately identify them, so we have to
221 * look at what sort of machine this is as well.
222 */
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000223 machine = of_get_property(root, "model", NULL);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000224 if (machine != NULL) {
225 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
226 is_mot = strncmp(machine, "MOT", 3) == 0;
227 if (strncmp(machine, "Pegasos2", 8) == 0)
228 is_pegasos = 2;
229 else if (strncmp(machine, "Pegasos", 7) == 0)
230 is_pegasos = 1;
231 }
232 for (dev = root->child; dev != NULL; dev = dev->sibling) {
233 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
234 continue;
235 ++index;
236 /* The GG2 bridge on the LongTrail doesn't have an address */
David Woodhouse575e3212006-01-14 00:13:49 +0000237 if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000238 printk(KERN_WARNING "Can't use %s: no address\n",
239 dev->full_name);
240 continue;
241 }
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000242 bus_range = of_get_property(dev, "bus-range", &len);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000243 if (bus_range == NULL || len < 2 * sizeof(int)) {
244 printk(KERN_WARNING "Can't get bus-range for %s\n",
245 dev->full_name);
246 continue;
247 }
248 if (bus_range[1] == bus_range[0])
249 printk(KERN_INFO "PCI bus %d", bus_range[0]);
250 else
251 printk(KERN_INFO "PCI buses %d..%d",
252 bus_range[0], bus_range[1]);
Benjamin Herrenschmidt26c50322006-07-04 14:16:28 +1000253 printk(" controlled by %s", dev->full_name);
David Woodhouse575e3212006-01-14 00:13:49 +0000254 if (!is_longtrail)
Greg Kroah-Hartman685143a2006-06-12 15:18:31 -0700255 printk(" at %llx", (unsigned long long)r.start);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000256 printk("\n");
257
Kumar Galadbf84712007-06-27 01:56:50 -0500258 hose = pcibios_alloc_controller(dev);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000259 if (!hose) {
260 printk("Can't allocate PCI controller structure for %s\n",
261 dev->full_name);
262 continue;
263 }
Benjamin Herrenschmidtee673ea2008-10-13 20:49:47 +0000264 hose->first_busno = hose->self_busno = bus_range[0];
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000265 hose->last_busno = bus_range[1];
266
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000267 model = of_get_property(dev, "model", NULL);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000268 if (model == NULL)
269 model = "<none>";
Benjamin Herrenschmidt22007a12008-10-13 20:14:09 +0000270 if (strncmp(model, "IBM, Python", 11) == 0) {
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000271 setup_python(hose, dev);
272 } else if (is_mot
273 || strncmp(model, "Motorola, Grackle", 17) == 0) {
274 setup_grackle(hose);
275 } else if (is_longtrail) {
276 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
277 hose->ops = &gg2_pci_ops;
278 hose->cfg_data = p;
279 gg2_pci_config_base = p;
280 } else if (is_pegasos == 1) {
Kumar Gala2e56ff22007-07-19 16:07:35 -0500281 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000282 } else if (is_pegasos == 2) {
283 setup_peg2(hose, dev);
Benjamin Herrenschmidt26c50322006-07-04 14:16:28 +1000284 } else if (!strncmp(model, "IBM,CPC710", 10)) {
285 setup_indirect_pci(hose,
286 r.start + 0x000f8000,
Kumar Gala2e56ff22007-07-19 16:07:35 -0500287 r.start + 0x000f8010,
288 0);
Benjamin Herrenschmidt26c50322006-07-04 14:16:28 +1000289 if (index == 0) {
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000290 dma = of_get_property(dev, "system-dma-base",
291 &len);
Benjamin Herrenschmidt26c50322006-07-04 14:16:28 +1000292 if (dma && len >= sizeof(*dma)) {
293 dma = (unsigned int *)
294 (((unsigned long)dma) +
295 len - sizeof(*dma));
296 pci_dram_offset = *dma;
297 }
298 }
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000299 } else {
300 printk("No methods for %s (model %s), using RTAS\n",
301 dev->full_name, model);
302 hose->ops = &rtas_pci_ops;
303 }
304
305 pci_process_bridge_OF_ranges(hose, dev, index == 0);
306
307 /* check the first bridge for a property that we can
308 use to set pci_dram_offset */
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000309 dma = of_get_property(dev, "ibm,dma-ranges", &len);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000310 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
311 pci_dram_offset = dma[2] - dma[3];
312 printk("pci_dram_offset = %lx\n", pci_dram_offset);
313 }
314 }
Stephen Rothwell8c8dc322007-04-24 13:50:55 +1000315 of_node_put(root);
Paul Mackerrasbbd0abd2005-10-26 21:45:56 +1000316}
Benjamin Herrenschmidt26c50322006-07-04 14:16:28 +1000317
318/* SL82C105 IDE Control/Status Register */
319#define SL82C105_IDECSR 0x40
320
Benjamin Herrenschmidt6d98bda2007-12-10 15:29:22 +1100321/* Fixup for Winbond ATA quirk, required for briq mostly because the
322 * 8259 is configured for level sensitive IRQ 14 and so wants the
323 * ATA controller to be set to fully native mode or bad things
324 * will happen.
325 */
326static void __devinit chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
Benjamin Herrenschmidt26c50322006-07-04 14:16:28 +1000327{
328 u8 progif;
329
330 /* If non-briq machines need that fixup too, please speak up */
331 if (!machine_is(chrp) || _chrp_type != _CHRP_briq)
332 return;
333
334 if ((sl82c105->class & 5) != 5) {
335 printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
336 /* Enable SL82C105 PCI native IDE mode */
337 pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
338 pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
339 sl82c105->class |= 0x05;
340 /* Disable SL82C105 second port */
341 pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
Benjamin Herrenschmidt6d98bda2007-12-10 15:29:22 +1100342 /* Clear IO BARs, they will be reassigned */
343 pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_0, 0);
344 pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_1, 0);
345 pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_2, 0);
346 pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_3, 0);
Benjamin Herrenschmidt26c50322006-07-04 14:16:28 +1000347 }
348}
Benjamin Herrenschmidt6d98bda2007-12-10 15:29:22 +1100349DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
350 chrp_pci_fixup_winbond_ata);
Olaf Hering556ecf92007-08-18 04:27:17 +1000351
352/* Pegasos2 firmware version 20040810 configures the built-in IDE controller
353 * in legacy mode, but sets the PCI registers to PCI native mode.
354 * The chip can only operate in legacy mode, so force the PCI class into legacy
355 * mode as well. The same fixup must be done to the class-code property in
356 * the IDE node /pci@80000000/ide@C,1
357 */
Olaf Hering092ca5b2008-01-21 20:39:30 +1100358static void chrp_pci_fixup_vt8231_ata(struct pci_dev *viaide)
Olaf Hering556ecf92007-08-18 04:27:17 +1000359{
360 u8 progif;
361 struct pci_dev *viaisa;
362
363 if (!machine_is(chrp) || _chrp_type != _CHRP_Pegasos)
364 return;
365 if (viaide->irq != 14)
366 return;
367
368 viaisa = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
369 if (!viaisa)
370 return;
Greg Kroah-Hartmanfc3a8822008-05-02 06:02:41 +0200371 dev_info(&viaide->dev, "Fixing VIA IDE, force legacy mode on\n");
Olaf Hering556ecf92007-08-18 04:27:17 +1000372
373 pci_read_config_byte(viaide, PCI_CLASS_PROG, &progif);
374 pci_write_config_byte(viaide, PCI_CLASS_PROG, progif & ~0x5);
375 viaide->class &= ~0x5;
376
377 pci_dev_put(viaisa);
378}
Olaf Hering092ca5b2008-01-21 20:39:30 +1100379DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, chrp_pci_fixup_vt8231_ata);