| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-l7200/include/mach/serial_l7200.h |
| 3 | * |
| 4 | * Copyright (c) 2000 Steven Hill (sjhill@cotw.com) |
| 5 | * |
| 6 | * Changelog: |
| 7 | * 05-09-2000 SJH Created |
| 8 | */ |
| 9 | #ifndef __ASM_ARCH_SERIAL_L7200_H |
| 10 | #define __ASM_ARCH_SERIAL_L7200_H |
| 11 | |
| 12 | #include <mach/memory.h> |
| 13 | |
| 14 | /* |
| 15 | * This assumes you have a 3.6864 MHz clock for your UART. |
| 16 | */ |
| 17 | #define BASE_BAUD 3686400 |
| 18 | |
| 19 | /* |
| 20 | * UART base register addresses |
| 21 | */ |
| 22 | #define UART1_BASE (IO_BASE + 0x00044000) |
| 23 | #define UART2_BASE (IO_BASE + 0x00045000) |
| 24 | |
| 25 | /* |
| 26 | * UART register offsets |
| 27 | */ |
| 28 | #define UARTDR 0x00 /* Tx/Rx data */ |
| 29 | #define RXSTAT 0x04 /* Rx status */ |
| 30 | #define H_UBRLCR 0x08 /* mode register high */ |
| 31 | #define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/ |
| 32 | #define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/ |
| 33 | #define UARTCON 0x14 /* control register */ |
| 34 | #define UARTFLG 0x18 /* flag register */ |
| 35 | #define UARTINTSTAT 0x1C /* FIFO IRQ status register */ |
| 36 | #define UARTINTMASK 0x20 /* FIFO IRQ mask register */ |
| 37 | |
| 38 | /* |
| 39 | * UART baud rate register values |
| 40 | */ |
| 41 | #define BR_110 0x827 |
| 42 | #define BR_1200 0x06e |
| 43 | #define BR_2400 0x05f |
| 44 | #define BR_4800 0x02f |
| 45 | #define BR_9600 0x017 |
| 46 | #define BR_14400 0x00f |
| 47 | #define BR_19200 0x00b |
| 48 | #define BR_38400 0x005 |
| 49 | #define BR_57600 0x003 |
| 50 | #define BR_76800 0x002 |
| 51 | #define BR_115200 0x001 |
| 52 | |
| 53 | /* |
| 54 | * Receiver status register (RXSTAT) mask values |
| 55 | */ |
| 56 | #define RXSTAT_NO_ERR 0x00 /* No error */ |
| 57 | #define RXSTAT_FRM_ERR 0x01 /* Framing error */ |
| 58 | #define RXSTAT_PAR_ERR 0x02 /* Parity error */ |
| 59 | #define RXSTAT_OVR_ERR 0x04 /* Overrun error */ |
| 60 | |
| 61 | /* |
| 62 | * High byte of UART bit rate and line control register (H_UBRLCR) values |
| 63 | */ |
| 64 | #define UBRLCR_BRK 0x01 /* generate break on tx */ |
| 65 | #define UBRLCR_PEN 0x02 /* enable parity */ |
| 66 | #define UBRLCR_PDIS 0x00 /* disable parity */ |
| 67 | #define UBRLCR_EVEN 0x04 /* 1= even parity,0 = odd parity */ |
| 68 | #define UBRLCR_STP2 0x08 /* transmit 2 stop bits */ |
| 69 | #define UBRLCR_FIFO 0x10 /* enable FIFO */ |
| 70 | #define UBRLCR_LEN5 0x60 /* word length5 */ |
| 71 | #define UBRLCR_LEN6 0x40 /* word length6 */ |
| 72 | #define UBRLCR_LEN7 0x20 /* word length7 */ |
| 73 | #define UBRLCR_LEN8 0x00 /* word length8 */ |
| 74 | |
| 75 | /* |
| 76 | * UART control register (UARTCON) values |
| 77 | */ |
| 78 | #define UARTCON_UARTEN 0x01 /* Enable UART */ |
| 79 | #define UARTCON_DMAONERR 0x08 /* Mask RxDmaRq when errors occur */ |
| 80 | |
| 81 | /* |
| 82 | * UART flag register (UARTFLG) mask values |
| 83 | */ |
| 84 | #define UARTFLG_UTXFF 0x20 /* Transmit FIFO full */ |
| 85 | #define UARTFLG_URXFE 0x10 /* Receiver FIFO empty */ |
| 86 | #define UARTFLG_UBUSY 0x08 /* Transmitter busy */ |
| 87 | #define UARTFLG_DCD 0x04 /* Data carrier detect */ |
| 88 | #define UARTFLG_DSR 0x02 /* Data set ready */ |
| 89 | #define UARTFLG_CTS 0x01 /* Clear to send */ |
| 90 | |
| 91 | /* |
| 92 | * UART interrupt status/clear registers (UARTINTSTAT/CLR) values |
| 93 | */ |
| 94 | #define UART_TXINT 0x01 /* TX interrupt */ |
| 95 | #define UART_RXINT 0x02 /* RX interrupt */ |
| 96 | #define UART_RXERRINT 0x04 /* RX error interrupt */ |
| 97 | #define UART_MSINT 0x08 /* Modem Status interrupt */ |
| 98 | #define UART_UDINT 0x10 /* UART Disabled interrupt */ |
| 99 | #define UART_ALLIRQS 0x1f /* All interrupts */ |
| 100 | |
| 101 | #endif |