Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 SMP source file. It contains platform specific fucntions |
| 3 | * needed for the linux smp kernel. |
| 4 | * |
| 5 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 6 | * |
| 7 | * Author: |
| 8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 9 | * |
| 10 | * Platform file needed for the OMAP4 SMP. This file is based on arm |
| 11 | * realview smp platform. |
| 12 | * * Copyright (c) 2002 ARM Limited. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | */ |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/device.h> |
| 20 | #include <linux/jiffies.h> |
| 21 | #include <linux/smp.h> |
| 22 | #include <linux/io.h> |
| 23 | |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame^] | 24 | #include <asm/cacheflush.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 25 | #include <asm/localtimer.h> |
| 26 | #include <asm/smp_scu.h> |
| 27 | #include <mach/hardware.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 28 | #include <plat/common.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 29 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 30 | /* SCU base address */ |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 31 | static void __iomem *scu_base; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * Use SCU config register to count number of cores |
| 35 | */ |
| 36 | static inline unsigned int get_core_count(void) |
| 37 | { |
| 38 | if (scu_base) |
| 39 | return scu_get_core_count(scu_base); |
| 40 | return 1; |
| 41 | } |
| 42 | |
| 43 | static DEFINE_SPINLOCK(boot_lock); |
| 44 | |
| 45 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 46 | { |
| 47 | trace_hardirqs_off(); |
| 48 | |
| 49 | /* |
| 50 | * If any interrupts are already enabled for the primary |
| 51 | * core (e.g. timer irq), then they will not have been enabled |
| 52 | * for us: do so |
| 53 | */ |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 54 | gic_cpu_init(0, gic_cpu_base_addr); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 55 | |
| 56 | /* |
| 57 | * Synchronise with the boot thread. |
| 58 | */ |
| 59 | spin_lock(&boot_lock); |
| 60 | spin_unlock(&boot_lock); |
| 61 | } |
| 62 | |
| 63 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 64 | { |
| 65 | unsigned long timeout; |
| 66 | |
| 67 | /* |
| 68 | * Set synchronisation state between this boot processor |
| 69 | * and the secondary one |
| 70 | */ |
| 71 | spin_lock(&boot_lock); |
| 72 | |
| 73 | /* |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame^] | 74 | * Update the AuxCoreBoot0 with boot state for secondary core. |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 75 | * omap_secondary_startup() routine will hold the secondary core till |
| 76 | * the AuxCoreBoot1 register is updated with cpu state |
| 77 | * A barrier is added to ensure that write buffer is drained |
| 78 | */ |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame^] | 79 | omap_modify_auxcoreboot0(0x200, 0x0); |
| 80 | flush_cache_all(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 81 | smp_wmb(); |
| 82 | |
| 83 | timeout = jiffies + (1 * HZ); |
| 84 | while (time_before(jiffies, timeout)) |
| 85 | ; |
| 86 | |
| 87 | /* |
| 88 | * Now the secondary core is starting up let it run its |
| 89 | * calibrations, then wait for it to finish |
| 90 | */ |
| 91 | spin_unlock(&boot_lock); |
| 92 | |
| 93 | return 0; |
| 94 | } |
| 95 | |
| 96 | static void __init wakeup_secondary(void) |
| 97 | { |
| 98 | /* |
| 99 | * Write the address of secondary startup routine into the |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame^] | 100 | * AuxCoreBoot1 where ROM code will jump and start executing |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 101 | * on secondary core once out of WFE |
| 102 | * A barrier is added to ensure that write buffer is drained |
| 103 | */ |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame^] | 104 | omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 105 | smp_wmb(); |
| 106 | |
| 107 | /* |
| 108 | * Send a 'sev' to wake the secondary core from WFE. |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame^] | 109 | * Drain the outstanding writes to memory |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 110 | */ |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame^] | 111 | dsb(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 112 | set_event(); |
| 113 | mb(); |
| 114 | } |
| 115 | |
| 116 | /* |
| 117 | * Initialise the CPU possible map early - this describes the CPUs |
| 118 | * which may be present or become present in the system. |
| 119 | */ |
| 120 | void __init smp_init_cpus(void) |
| 121 | { |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 122 | unsigned int i, ncores; |
| 123 | |
| 124 | /* Never released */ |
| 125 | scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256); |
| 126 | BUG_ON(!scu_base); |
| 127 | |
| 128 | ncores = get_core_count(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 129 | |
| 130 | for (i = 0; i < ncores; i++) |
| 131 | set_cpu_possible(i, true); |
| 132 | } |
| 133 | |
| 134 | void __init smp_prepare_cpus(unsigned int max_cpus) |
| 135 | { |
| 136 | unsigned int ncores = get_core_count(); |
| 137 | unsigned int cpu = smp_processor_id(); |
| 138 | int i; |
| 139 | |
| 140 | /* sanity check */ |
| 141 | if (ncores == 0) { |
| 142 | printk(KERN_ERR |
| 143 | "OMAP4: strange core count of 0? Default to 1\n"); |
| 144 | ncores = 1; |
| 145 | } |
| 146 | |
| 147 | if (ncores > NR_CPUS) { |
| 148 | printk(KERN_WARNING |
| 149 | "OMAP4: no. of cores (%d) greater than configured " |
| 150 | "maximum of %d - clipping\n", |
| 151 | ncores, NR_CPUS); |
| 152 | ncores = NR_CPUS; |
| 153 | } |
| 154 | smp_store_cpu_info(cpu); |
| 155 | |
| 156 | /* |
| 157 | * are we trying to boot more cores than exist? |
| 158 | */ |
| 159 | if (max_cpus > ncores) |
| 160 | max_cpus = ncores; |
| 161 | |
| 162 | /* |
| 163 | * Initialise the present map, which describes the set of CPUs |
| 164 | * actually populated at the present time. |
| 165 | */ |
| 166 | for (i = 0; i < max_cpus; i++) |
| 167 | set_cpu_present(i, true); |
| 168 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 169 | if (max_cpus > 1) { |
| 170 | /* |
| 171 | * Enable the local timer or broadcast device for the |
| 172 | * boot CPU, but only if we have more than one CPU. |
| 173 | */ |
| 174 | percpu_timer_setup(); |
| 175 | |
| 176 | /* |
| 177 | * Initialise the SCU and wake up the secondary core using |
| 178 | * wakeup_secondary(). |
| 179 | */ |
| 180 | scu_enable(scu_base); |
| 181 | wakeup_secondary(); |
| 182 | } |
| 183 | } |