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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Russell King4baa9922008-08-02 10:55:55 +01002 * arch/arm/include/asm/ptrace.h
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 1996-2003 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARM_PTRACE_H
11#define __ASM_ARM_PTRACE_H
12
Catalin Marinasd1cbbd62007-07-11 11:29:39 +010013#include <asm/hwcap.h>
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#define PTRACE_GETREGS 12
16#define PTRACE_SETREGS 13
17#define PTRACE_GETFPREGS 14
18#define PTRACE_SETFPREGS 15
Russell King1b116522007-05-06 14:49:56 +010019/* PTRACE_ATTACH is 16 */
20/* PTRACE_DETACH is 17 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#define PTRACE_GETWMMXREGS 18
22#define PTRACE_SETWMMXREGS 19
Russell King1b116522007-05-06 14:49:56 +010023/* 20 is unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#define PTRACE_OLDSETOPTIONS 21
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#define PTRACE_GET_THREAD_AREA 22
Nicolas Pitre3f471122006-01-14 19:30:04 +000026#define PTRACE_SET_SYSCALL 23
Lennert Buytenhek5429b062006-06-27 22:56:19 +010027/* PTRACE_SYSCALL is 24 */
Lennert Buytenhek5429b062006-06-27 22:56:19 +010028#define PTRACE_GETCRUNCHREGS 25
29#define PTRACE_SETCRUNCHREGS 26
Catalin Marinas3d1228e2009-02-11 13:12:56 +010030#define PTRACE_GETVFPREGS 27
31#define PTRACE_SETVFPREGS 28
Will Deacon864232f2010-09-03 10:42:55 +010032#define PTRACE_GETHBPREGS 29
33#define PTRACE_SETHBPREGS 30
Lennert Buytenhek5429b062006-06-27 22:56:19 +010034
Linus Torvalds1da177e2005-04-16 15:20:36 -070035/*
36 * PSR bits
37 */
38#define USR26_MODE 0x00000000
39#define FIQ26_MODE 0x00000001
40#define IRQ26_MODE 0x00000002
41#define SVC26_MODE 0x00000003
42#define USR_MODE 0x00000010
43#define FIQ_MODE 0x00000011
44#define IRQ_MODE 0x00000012
45#define SVC_MODE 0x00000013
46#define ABT_MODE 0x00000017
47#define UND_MODE 0x0000001b
48#define SYSTEM_MODE 0x0000001f
49#define MODE32_BIT 0x00000010
50#define MODE_MASK 0x0000001f
51#define PSR_T_BIT 0x00000020
52#define PSR_F_BIT 0x00000040
53#define PSR_I_BIT 0x00000080
Catalin Marinasd1cbbd62007-07-11 11:29:39 +010054#define PSR_A_BIT 0x00000100
Catalin Marinas26584852009-05-30 14:00:18 +010055#define PSR_E_BIT 0x00000200
Linus Torvalds1da177e2005-04-16 15:20:36 -070056#define PSR_J_BIT 0x01000000
57#define PSR_Q_BIT 0x08000000
58#define PSR_V_BIT 0x10000000
59#define PSR_C_BIT 0x20000000
60#define PSR_Z_BIT 0x40000000
61#define PSR_N_BIT 0x80000000
Linus Torvalds1da177e2005-04-16 15:20:36 -070062
63/*
64 * Groups of PSR bits
65 */
66#define PSR_f 0xff000000 /* Flags */
67#define PSR_s 0x00ff0000 /* Status */
68#define PSR_x 0x0000ff00 /* Extension */
69#define PSR_c 0x000000ff /* Control */
70
Catalin Marinasd71e1352009-05-30 14:00:15 +010071/*
Jon Medhurst7460bce2011-06-03 12:12:33 +010072 * ARMv7 groups of PSR bits
Catalin Marinasd71e1352009-05-30 14:00:15 +010073 */
Jon Medhurst7460bce2011-06-03 12:12:33 +010074#define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */
Catalin Marinasd71e1352009-05-30 14:00:15 +010075#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
76#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
77#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
78
Catalin Marinas26584852009-05-30 14:00:18 +010079/*
80 * Default endianness state
81 */
82#ifdef CONFIG_CPU_ENDIAN_BE8
83#define PSR_ENDSTATE PSR_E_BIT
84#else
85#define PSR_ENDSTATE 0
86#endif
87
Paul Brook68b7f7152009-07-24 12:34:58 +010088/*
89 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
90 * process is located in memory.
91 */
92#define PT_TEXT_ADDR 0x10000
93#define PT_DATA_ADDR 0x10004
94#define PT_TEXT_END_ADDR 0x10008
95
Linus Torvalds1da177e2005-04-16 15:20:36 -070096#ifndef __ASSEMBLY__
97
Nicolas Pitre2dede2d2006-01-14 16:18:08 +000098/*
99 * This struct defines the way the registers are stored on the
100 * stack during a system call. Note that sizeof(struct pt_regs)
101 * has to be a multiple of 8.
102 */
Jamie Iles092a4e92010-01-06 10:50:08 +0100103#ifndef __KERNEL__
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104struct pt_regs {
105 long uregs[18];
106};
Jamie Iles092a4e92010-01-06 10:50:08 +0100107#else /* __KERNEL__ */
108struct pt_regs {
109 unsigned long uregs[18];
110};
111#endif /* __KERNEL__ */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112
113#define ARM_cpsr uregs[16]
114#define ARM_pc uregs[15]
115#define ARM_lr uregs[14]
116#define ARM_sp uregs[13]
117#define ARM_ip uregs[12]
118#define ARM_fp uregs[11]
119#define ARM_r10 uregs[10]
120#define ARM_r9 uregs[9]
121#define ARM_r8 uregs[8]
122#define ARM_r7 uregs[7]
123#define ARM_r6 uregs[6]
124#define ARM_r5 uregs[5]
125#define ARM_r4 uregs[4]
126#define ARM_r3 uregs[3]
127#define ARM_r2 uregs[2]
128#define ARM_r1 uregs[1]
129#define ARM_r0 uregs[0]
130#define ARM_ORIG_r0 uregs[17]
131
Dave Martin5be6f622011-04-18 14:48:23 +0100132/*
133 * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
134 * and core dumps.
135 */
136#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ )
137
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138#ifdef __KERNEL__
139
140#define user_mode(regs) \
141 (((regs)->ARM_cpsr & 0xf) == 0)
142
143#ifdef CONFIG_ARM_THUMB
144#define thumb_mode(regs) \
145 (((regs)->ARM_cpsr & PSR_T_BIT))
146#else
147#define thumb_mode(regs) (0)
148#endif
149
George G. Davis909d6c62007-06-26 01:38:27 +0100150#define isa_mode(regs) \
151 ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
152 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
153
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154#define processor_mode(regs) \
155 ((regs)->ARM_cpsr & MODE_MASK)
156
157#define interrupts_enabled(regs) \
158 (!((regs)->ARM_cpsr & PSR_I_BIT))
159
160#define fast_interrupts_enabled(regs) \
161 (!((regs)->ARM_cpsr & PSR_F_BIT))
162
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163/* Are the current registers suitable for user mode?
164 * (used to maintain security in signal handlers)
165 */
166static inline int valid_user_regs(struct pt_regs *regs)
167{
Russell King41e2e8f2010-08-13 23:33:46 +0100168 unsigned long mode = regs->ARM_cpsr & MODE_MASK;
169
170 /*
171 * Always clear the F (FIQ) and A (delayed abort) bits
172 */
173 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
174
175 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
176 if (mode == USR_MODE)
177 return 1;
178 if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
179 return 1;
Catalin Marinasd1cbbd62007-07-11 11:29:39 +0100180 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181
182 /*
183 * Force CPSR to something logical...
184 */
Russell King41e2e8f2010-08-13 23:33:46 +0100185 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
Catalin Marinasd1cbbd62007-07-11 11:29:39 +0100186 if (!(elf_hwcap & HWCAP_26BIT))
187 regs->ARM_cpsr |= USR_MODE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188
189 return 0;
190}
191
Russell King1de765c2008-09-06 10:14:24 +0100192#define instruction_pointer(regs) (regs)->ARM_pc
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193
194#ifdef CONFIG_SMP
195extern unsigned long profile_pc(struct pt_regs *regs);
196#else
197#define profile_pc(regs) instruction_pointer(regs)
198#endif
199
Russell King652a12e2005-04-17 15:50:36 +0100200#define predicate(x) ((x) & 0xf0000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201#define PREDICATE_ALWAYS 0xe0000000
Adrian Bunkf22ab812008-07-25 01:47:34 -0700202
Will Deacone513f8b2010-06-25 12:24:53 +0100203/*
Jon Medhurst592201a2011-03-26 19:19:07 +0000204 * True if instr is a 32-bit thumb instruction. This works if instr
205 * is the first or only half-word of a thumb instruction. It also works
206 * when instr holds all 32-bits of a wide thumb instruction if stored
207 * in the form (first_half<<16)|(second_half)
208 */
209#define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800)
210
211/*
Will Deacone513f8b2010-06-25 12:24:53 +0100212 * kprobe-based event tracer support
213 */
214#include <linux/stddef.h>
215#include <linux/types.h>
216#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
217
218extern int regs_query_register_offset(const char *name);
219extern const char *regs_query_register_name(unsigned int offset);
220extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
221extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
222 unsigned int n);
223
224/**
225 * regs_get_register() - get register value from its offset
226 * @regs: pt_regs from which register value is gotten
227 * @offset: offset number of the register.
228 *
229 * regs_get_register returns the value of a register whose offset from @regs.
230 * The @offset is the offset of the register in struct pt_regs.
231 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
232 */
233static inline unsigned long regs_get_register(struct pt_regs *regs,
234 unsigned int offset)
235{
236 if (unlikely(offset > MAX_REG_OFFSET))
237 return 0;
238 return *(unsigned long *)((unsigned long)regs + offset);
239}
240
241/* Valid only for Kernel mode traps. */
242static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
243{
244 return regs->ARM_sp;
245}
246
Adrian Bunkf22ab812008-07-25 01:47:34 -0700247#endif /* __KERNEL__ */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248
249#endif /* __ASSEMBLY__ */
250
251#endif
252