Zang Roy-r61911 | 2b9d746 | 2006-06-13 15:07:23 +0800 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-ppc/tsi108.h |
| 3 | * |
| 4 | * common routine and memory layout for Tundra TSI108(Grendel) host bridge |
| 5 | * memory controller. |
| 6 | * |
| 7 | * Author: Jacob Pan (jacob.pan@freescale.com) |
| 8 | * Alex Bounine (alexandreb@tundra.com) |
| 9 | * 2004 (c) Freescale Semiconductor Inc. This file is licensed under |
| 10 | * the terms of the GNU General Public License version 2. This program |
| 11 | * is licensed "as is" without any warranty of any kind, whether express |
| 12 | * or implied. |
| 13 | */ |
| 14 | #ifndef __PPC_KERNEL_TSI108_H |
| 15 | #define __PPC_KERNEL_TSI108_H |
| 16 | |
| 17 | #include <asm/pci-bridge.h> |
| 18 | |
| 19 | /* Size of entire register space */ |
| 20 | #define TSI108_REG_SIZE (0x10000) |
| 21 | |
| 22 | /* Sizes of register spaces for individual blocks */ |
| 23 | #define TSI108_HLP_SIZE 0x1000 |
| 24 | #define TSI108_PCI_SIZE 0x1000 |
| 25 | #define TSI108_CLK_SIZE 0x1000 |
| 26 | #define TSI108_PB_SIZE 0x1000 |
| 27 | #define TSI108_SD_SIZE 0x1000 |
| 28 | #define TSI108_DMA_SIZE 0x1000 |
| 29 | #define TSI108_ETH_SIZE 0x1000 |
| 30 | #define TSI108_I2C_SIZE 0x400 |
| 31 | #define TSI108_MPIC_SIZE 0x400 |
| 32 | #define TSI108_UART0_SIZE 0x200 |
| 33 | #define TSI108_GPIO_SIZE 0x200 |
| 34 | #define TSI108_UART1_SIZE 0x200 |
| 35 | |
| 36 | /* Offsets within Tsi108(A) CSR space for individual blocks */ |
| 37 | #define TSI108_HLP_OFFSET 0x0000 |
| 38 | #define TSI108_PCI_OFFSET 0x1000 |
| 39 | #define TSI108_CLK_OFFSET 0x2000 |
| 40 | #define TSI108_PB_OFFSET 0x3000 |
| 41 | #define TSI108_SD_OFFSET 0x4000 |
| 42 | #define TSI108_DMA_OFFSET 0x5000 |
| 43 | #define TSI108_ETH_OFFSET 0x6000 |
| 44 | #define TSI108_I2C_OFFSET 0x7000 |
| 45 | #define TSI108_MPIC_OFFSET 0x7400 |
| 46 | #define TSI108_UART0_OFFSET 0x7800 |
| 47 | #define TSI108_GPIO_OFFSET 0x7A00 |
| 48 | #define TSI108_UART1_OFFSET 0x7C00 |
| 49 | |
| 50 | /* Tsi108 registers used by common code components */ |
| 51 | #define TSI108_PCI_CSR (0x004) |
| 52 | #define TSI108_PCI_IRP_CFG_CTL (0x180) |
| 53 | #define TSI108_PCI_IRP_STAT (0x184) |
| 54 | #define TSI108_PCI_IRP_ENABLE (0x188) |
| 55 | #define TSI108_PCI_IRP_INTAD (0x18C) |
| 56 | |
| 57 | #define TSI108_PCI_IRP_STAT_P_INT (0x00400000) |
| 58 | #define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000) |
| 59 | |
| 60 | #define TSI108_CG_PWRUP_STATUS (0x234) |
| 61 | |
| 62 | #define TSI108_PB_ISR (0x00C) |
| 63 | #define TSI108_PB_ERRCS (0x404) |
| 64 | #define TSI108_PB_AERR (0x408) |
| 65 | |
| 66 | #define TSI108_PB_ERRCS_ES (1 << 1) |
| 67 | #define TSI108_PB_ISR_PBS_RD_ERR (1 << 8) |
| 68 | |
| 69 | #define TSI108_PCI_CFG_BASE_PHYS (0xfb000000) |
| 70 | #define TSI108_PCI_CFG_SIZE (0x01000000) |
| 71 | /* Global variables */ |
| 72 | |
| 73 | extern u32 tsi108_pci_cfg_base; |
| 74 | /* Exported functions */ |
| 75 | |
| 76 | extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base); |
| 77 | extern unsigned long tsi108_get_mem_size(void); |
| 78 | extern unsigned long tsi108_get_cpu_clk(void); |
| 79 | extern unsigned long tsi108_get_sdc_clk(void); |
| 80 | extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn, |
| 81 | int offset, int len, u32 val); |
| 82 | extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, |
| 83 | int offset, int len, u32 * val); |
| 84 | extern void tsi108_clear_pci_error(u32 pci_cfg_base); |
| 85 | |
| 86 | extern phys_addr_t get_csrbase(void); |
| 87 | |
| 88 | typedef struct { |
| 89 | u32 regs; /* hw registers base address */ |
| 90 | u32 phyregs; /* phy registers base address */ |
| 91 | u16 phy; /* phy address */ |
| 92 | u16 irq_num; /* irq number */ |
| 93 | u8 mac_addr[6]; /* phy mac address */ |
| 94 | } hw_info; |
| 95 | |
| 96 | extern u32 get_vir_csrbase(void); |
| 97 | extern u32 tsi108_csr_vir_base; |
| 98 | |
| 99 | extern inline u32 tsi108_read_reg(u32 reg_offset) |
| 100 | { |
| 101 | return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset)); |
| 102 | } |
| 103 | |
| 104 | extern inline void tsi108_write_reg(u32 reg_offset, u32 val) |
| 105 | { |
| 106 | out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val); |
| 107 | } |
| 108 | |
| 109 | #endif /* __PPC_KERNEL_TSI108_H */ |