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gerrit-public.fairphone.software / kernel / msm / 972c3fb69cd1cd8d549b8a06ce42611eab405c20 / . / arch / arm / plat-samsung / include / plat / s3c64xx-spi.h
blob: 4c16fa3621bb813f1dbd80f25e9a987dbd5e04ca [file] [log] [blame]
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]1/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S3C64XX_PLAT_SPI_H
12#define __S3C64XX_PLAT_SPI_H
13
14/**
15 * struct s3c64xx_spi_csinfo - ChipSelect description
16 * @fb_delay: Slave specific feedback delay.
17 * Refer to FB_CLK_SEL register definition in SPI chapter.
18 * @line: Custom 'identity' of the CS line.
19 * @set_level: CS line control.
20 *
21 * This is per SPI-Slave Chipselect information.
22 * Allocate and initialize one in machine init code and make the
23 * spi_board_info.controller_data point to it.
24 */
25struct s3c64xx_spi_csinfo {
26 u8 fb_delay;
27 unsigned line;
28 void (*set_level)(unsigned line_id, int lvl);
29};
30
31/**
32 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
34 * @src_clk_name: Platform name of the corresponding clock.
Jassi Brarb42a81c2010-09-29 17:31:33 +0900[diff] [blame]35 * @clk_from_cmu: If the SPI clock/prescalar control block is present
36 * by the platform's clock-management-unit and not in SPI controller.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]37 * @num_cs: Number of CS this controller emulates.
38 * @cfg_gpio: Configure pins for this SPI controller.
39 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
40 * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
41 * @high_speed: If the controller supports HIGH_SPEED_EN bit
Padmavathi Venna89180342011-07-05 17:13:56 +0900[diff] [blame]42 * @tx_st_done: Depends on tx fifo_lvl field
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]43 */
44struct s3c64xx_spi_info {
45 int src_clk_nr;
46 char *src_clk_name;
Jassi Brarb42a81c2010-09-29 17:31:33 +0900[diff] [blame]47 bool clk_from_cmu;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]48
49 int num_cs;
50
51 int (*cfg_gpio)(struct platform_device *pdev);
52
53 /* Following two fields are for future compatibility */
54 int fifo_lvl_mask;
55 int rx_lvl_offset;
56 int high_speed;
Padmavathi Venna89180342011-07-05 17:13:56 +0900[diff] [blame]57 int tx_st_done;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]58};
59
60/**
61 * s3c64xx_spi_set_info - SPI Controller configure callback by the board
62 * initialization code.
63 * @cntrlr: SPI controller number the configuration is for.
64 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
65 * @num_cs: Number of elements in the 'cs' array.
66 *
67 * Call this from machine init code for each SPI Controller that
68 * has some chips attached to it.
69 */
70extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
Jassi Brar7c3943f2010-05-18 16:43:34 +0900[diff] [blame]71extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
Jassi Brarf0c303a2010-05-18 16:43:37 +0900[diff] [blame]72extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
Kukjin Kime661faa2010-09-08 19:21:23 +0900[diff] [blame]73extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]74
75#endif /* __S3C64XX_PLAT_SPI_H */