| Ben Dooks | b6d6454 | 2007-02-20 13:58:01 -0800 | [diff] [blame] | 1 | /* sm501-regs.h |
| 2 | * |
| 3 | * Copyright 2006 Simtec Electronics |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * Silicon Motion SM501 register definitions |
| 10 | */ |
| 11 | |
| 12 | /* System Configuration area */ |
| 13 | /* System config base */ |
| 14 | #define SM501_SYS_CONFIG (0x000000) |
| 15 | |
| 16 | /* config 1 */ |
| 17 | #define SM501_SYSTEM_CONTROL (0x000000) |
| Ben Dooks | eb78f9b | 2007-10-16 01:28:39 -0700 | [diff] [blame] | 18 | |
| 19 | #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0) |
| 20 | #define SM501_SYSCTRL_MEM_TRISTATE (1<<1) |
| 21 | #define SM501_SYSCTRL_CRT_TRISTATE (1<<2) |
| 22 | |
| 23 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4) |
| 24 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4) |
| 25 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4) |
| 26 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4) |
| 27 | #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4) |
| 28 | |
| 29 | #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6) |
| 30 | #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7) |
| 31 | #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11) |
| 32 | #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15) |
| 33 | |
| 34 | /* miscellaneous control */ |
| 35 | |
| Ben Dooks | b6d6454 | 2007-02-20 13:58:01 -0800 | [diff] [blame] | 36 | #define SM501_MISC_CONTROL (0x000004) |
| 37 | |
| 38 | #define SM501_MISC_BUS_SH (0x0) |
| 39 | #define SM501_MISC_BUS_PCI (0x1) |
| 40 | #define SM501_MISC_BUS_XSCALE (0x2) |
| 41 | #define SM501_MISC_BUS_NEC (0x6) |
| 42 | #define SM501_MISC_BUS_MASK (0x7) |
| 43 | |
| 44 | #define SM501_MISC_VR_62MB (1<<3) |
| 45 | #define SM501_MISC_CDR_RESET (1<<7) |
| 46 | #define SM501_MISC_USB_LB (1<<8) |
| 47 | #define SM501_MISC_USB_SLAVE (1<<9) |
| 48 | #define SM501_MISC_BL_1 (1<<10) |
| 49 | #define SM501_MISC_MC (1<<11) |
| 50 | #define SM501_MISC_DAC_POWER (1<<12) |
| 51 | #define SM501_MISC_IRQ_INVERT (1<<16) |
| 52 | #define SM501_MISC_SH (1<<17) |
| 53 | |
| 54 | #define SM501_MISC_HOLD_EMPTY (0<<18) |
| 55 | #define SM501_MISC_HOLD_8 (1<<18) |
| 56 | #define SM501_MISC_HOLD_16 (2<<18) |
| 57 | #define SM501_MISC_HOLD_24 (3<<18) |
| 58 | #define SM501_MISC_HOLD_32 (4<<18) |
| 59 | #define SM501_MISC_HOLD_MASK (7<<18) |
| 60 | |
| 61 | #define SM501_MISC_FREQ_12 (1<<24) |
| 62 | #define SM501_MISC_PNL_24BIT (1<<25) |
| 63 | #define SM501_MISC_8051_LE (1<<26) |
| 64 | |
| 65 | |
| 66 | |
| 67 | #define SM501_GPIO31_0_CONTROL (0x000008) |
| 68 | #define SM501_GPIO63_32_CONTROL (0x00000C) |
| 69 | #define SM501_DRAM_CONTROL (0x000010) |
| 70 | |
| 71 | /* command list */ |
| 72 | #define SM501_ARBTRTN_CONTROL (0x000014) |
| 73 | |
| 74 | /* command list */ |
| 75 | #define SM501_COMMAND_LIST_STATUS (0x000024) |
| 76 | |
| 77 | /* interrupt debug */ |
| 78 | #define SM501_RAW_IRQ_STATUS (0x000028) |
| 79 | #define SM501_RAW_IRQ_CLEAR (0x000028) |
| 80 | #define SM501_IRQ_STATUS (0x00002C) |
| 81 | #define SM501_IRQ_MASK (0x000030) |
| 82 | #define SM501_DEBUG_CONTROL (0x000034) |
| 83 | |
| 84 | /* power management */ |
| Ben Dooks | 8190622 | 2007-06-23 17:16:30 -0700 | [diff] [blame] | 85 | #define SM501_POWERMODE_P2X_SRC (1<<29) |
| 86 | #define SM501_POWERMODE_V2X_SRC (1<<20) |
| 87 | #define SM501_POWERMODE_M_SRC (1<<12) |
| 88 | #define SM501_POWERMODE_M1_SRC (1<<4) |
| 89 | |
| Ben Dooks | b6d6454 | 2007-02-20 13:58:01 -0800 | [diff] [blame] | 90 | #define SM501_CURRENT_GATE (0x000038) |
| 91 | #define SM501_CURRENT_CLOCK (0x00003C) |
| 92 | #define SM501_POWER_MODE_0_GATE (0x000040) |
| 93 | #define SM501_POWER_MODE_0_CLOCK (0x000044) |
| 94 | #define SM501_POWER_MODE_1_GATE (0x000048) |
| 95 | #define SM501_POWER_MODE_1_CLOCK (0x00004C) |
| 96 | #define SM501_SLEEP_MODE_GATE (0x000050) |
| 97 | #define SM501_POWER_MODE_CONTROL (0x000054) |
| 98 | |
| 99 | /* power gates for units within the 501 */ |
| 100 | #define SM501_GATE_HOST (0) |
| 101 | #define SM501_GATE_MEMORY (1) |
| 102 | #define SM501_GATE_DISPLAY (2) |
| 103 | #define SM501_GATE_2D_ENGINE (3) |
| 104 | #define SM501_GATE_CSC (4) |
| 105 | #define SM501_GATE_ZVPORT (5) |
| 106 | #define SM501_GATE_GPIO (6) |
| 107 | #define SM501_GATE_UART0 (7) |
| 108 | #define SM501_GATE_UART1 (8) |
| 109 | #define SM501_GATE_SSP (10) |
| 110 | #define SM501_GATE_USB_HOST (11) |
| 111 | #define SM501_GATE_USB_GADGET (12) |
| 112 | #define SM501_GATE_UCONTROLLER (17) |
| 113 | #define SM501_GATE_AC97 (18) |
| 114 | |
| 115 | /* panel clock */ |
| 116 | #define SM501_CLOCK_P2XCLK (24) |
| 117 | /* crt clock */ |
| 118 | #define SM501_CLOCK_V2XCLK (16) |
| 119 | /* main clock */ |
| 120 | #define SM501_CLOCK_MCLK (8) |
| 121 | /* SDRAM controller clock */ |
| 122 | #define SM501_CLOCK_M1XCLK (0) |
| 123 | |
| 124 | /* config 2 */ |
| 125 | #define SM501_PCI_MASTER_BASE (0x000058) |
| 126 | #define SM501_ENDIAN_CONTROL (0x00005C) |
| 127 | #define SM501_DEVICEID (0x000060) |
| 128 | /* 0x050100A0 */ |
| 129 | |
| Ben Dooks | 1e27dbe | 2007-06-23 17:16:31 -0700 | [diff] [blame] | 130 | #define SM501_DEVICEID_SM501 (0x05010000) |
| 131 | #define SM501_DEVICEID_IDMASK (0xffff0000) |
| 132 | |
| Ben Dooks | b6d6454 | 2007-02-20 13:58:01 -0800 | [diff] [blame] | 133 | #define SM501_PLLCLOCK_COUNT (0x000064) |
| 134 | #define SM501_MISC_TIMING (0x000068) |
| 135 | #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) |
| 136 | |
| 137 | /* GPIO base */ |
| 138 | #define SM501_GPIO (0x010000) |
| 139 | #define SM501_GPIO_DATA_LOW (0x00) |
| 140 | #define SM501_GPIO_DATA_HIGH (0x04) |
| 141 | #define SM501_GPIO_DDR_LOW (0x08) |
| 142 | #define SM501_GPIO_DDR_HIGH (0x0C) |
| 143 | #define SM501_GPIO_IRQ_SETUP (0x10) |
| 144 | #define SM501_GPIO_IRQ_STATUS (0x14) |
| 145 | #define SM501_GPIO_IRQ_RESET (0x14) |
| 146 | |
| 147 | /* I2C controller base */ |
| 148 | #define SM501_I2C (0x010040) |
| 149 | #define SM501_I2C_BYTE_COUNT (0x00) |
| 150 | #define SM501_I2C_CONTROL (0x01) |
| 151 | #define SM501_I2C_STATUS (0x02) |
| 152 | #define SM501_I2C_RESET (0x02) |
| 153 | #define SM501_I2C_SLAVE_ADDRESS (0x03) |
| 154 | #define SM501_I2C_DATA (0x04) |
| 155 | |
| 156 | /* SSP base */ |
| 157 | #define SM501_SSP (0x020000) |
| 158 | |
| 159 | /* Uart 0 base */ |
| 160 | #define SM501_UART0 (0x030000) |
| 161 | |
| 162 | /* Uart 1 base */ |
| 163 | #define SM501_UART1 (0x030020) |
| 164 | |
| 165 | /* USB host port base */ |
| 166 | #define SM501_USB_HOST (0x040000) |
| 167 | |
| 168 | /* USB slave/gadget base */ |
| 169 | #define SM501_USB_GADGET (0x060000) |
| 170 | |
| 171 | /* USB slave/gadget data port base */ |
| 172 | #define SM501_USB_GADGET_DATA (0x070000) |
| 173 | |
| 174 | /* Display contoller/video engine base */ |
| 175 | #define SM501_DC (0x080000) |
| 176 | |
| 177 | /* common defines for the SM501 address registers */ |
| 178 | #define SM501_ADDR_FLIP (1<<31) |
| 179 | #define SM501_ADDR_EXT (1<<27) |
| 180 | #define SM501_ADDR_CS1 (1<<26) |
| 181 | #define SM501_ADDR_MASK (0x3f << 26) |
| 182 | |
| 183 | #define SM501_FIFO_MASK (0x3 << 16) |
| 184 | #define SM501_FIFO_1 (0x0 << 16) |
| 185 | #define SM501_FIFO_3 (0x1 << 16) |
| 186 | #define SM501_FIFO_7 (0x2 << 16) |
| 187 | #define SM501_FIFO_11 (0x3 << 16) |
| 188 | |
| 189 | /* common registers for panel and the crt */ |
| 190 | #define SM501_OFF_DC_H_TOT (0x000) |
| 191 | #define SM501_OFF_DC_V_TOT (0x008) |
| 192 | #define SM501_OFF_DC_H_SYNC (0x004) |
| 193 | #define SM501_OFF_DC_V_SYNC (0x00C) |
| 194 | |
| 195 | #define SM501_DC_PANEL_CONTROL (0x000) |
| 196 | |
| 197 | #define SM501_DC_PANEL_CONTROL_FPEN (1<<27) |
| 198 | #define SM501_DC_PANEL_CONTROL_BIAS (1<<26) |
| 199 | #define SM501_DC_PANEL_CONTROL_DATA (1<<25) |
| 200 | #define SM501_DC_PANEL_CONTROL_VDD (1<<24) |
| 201 | #define SM501_DC_PANEL_CONTROL_DP (1<<23) |
| 202 | |
| 203 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21) |
| 204 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21) |
| 205 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21) |
| 206 | |
| 207 | #define SM501_DC_PANEL_CONTROL_DE (1<<20) |
| 208 | |
| 209 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18) |
| 210 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18) |
| 211 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18) |
| 212 | |
| 213 | #define SM501_DC_PANEL_CONTROL_CP (1<<14) |
| 214 | #define SM501_DC_PANEL_CONTROL_VSP (1<<13) |
| 215 | #define SM501_DC_PANEL_CONTROL_HSP (1<<12) |
| 216 | #define SM501_DC_PANEL_CONTROL_CK (1<<9) |
| 217 | #define SM501_DC_PANEL_CONTROL_TE (1<<8) |
| 218 | #define SM501_DC_PANEL_CONTROL_VPD (1<<7) |
| 219 | #define SM501_DC_PANEL_CONTROL_VP (1<<6) |
| 220 | #define SM501_DC_PANEL_CONTROL_HPD (1<<5) |
| 221 | #define SM501_DC_PANEL_CONTROL_HP (1<<4) |
| 222 | #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3) |
| 223 | #define SM501_DC_PANEL_CONTROL_EN (1<<2) |
| 224 | |
| 225 | #define SM501_DC_PANEL_CONTROL_8BPP (0<<0) |
| 226 | #define SM501_DC_PANEL_CONTROL_16BPP (1<<0) |
| 227 | #define SM501_DC_PANEL_CONTROL_32BPP (2<<0) |
| 228 | |
| 229 | |
| 230 | #define SM501_DC_PANEL_PANNING_CONTROL (0x004) |
| 231 | #define SM501_DC_PANEL_COLOR_KEY (0x008) |
| 232 | #define SM501_DC_PANEL_FB_ADDR (0x00C) |
| 233 | #define SM501_DC_PANEL_FB_OFFSET (0x010) |
| 234 | #define SM501_DC_PANEL_FB_WIDTH (0x014) |
| 235 | #define SM501_DC_PANEL_FB_HEIGHT (0x018) |
| 236 | #define SM501_DC_PANEL_TL_LOC (0x01C) |
| 237 | #define SM501_DC_PANEL_BR_LOC (0x020) |
| 238 | #define SM501_DC_PANEL_H_TOT (0x024) |
| 239 | #define SM501_DC_PANEL_H_SYNC (0x028) |
| 240 | #define SM501_DC_PANEL_V_TOT (0x02C) |
| 241 | #define SM501_DC_PANEL_V_SYNC (0x030) |
| 242 | #define SM501_DC_PANEL_CUR_LINE (0x034) |
| 243 | |
| 244 | #define SM501_DC_VIDEO_CONTROL (0x040) |
| 245 | #define SM501_DC_VIDEO_FB0_ADDR (0x044) |
| 246 | #define SM501_DC_VIDEO_FB_WIDTH (0x048) |
| 247 | #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) |
| 248 | #define SM501_DC_VIDEO_TL_LOC (0x050) |
| 249 | #define SM501_DC_VIDEO_BR_LOC (0x054) |
| 250 | #define SM501_DC_VIDEO_SCALE (0x058) |
| 251 | #define SM501_DC_VIDEO_INIT_SCALE (0x05C) |
| 252 | #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) |
| 253 | #define SM501_DC_VIDEO_FB1_ADDR (0x064) |
| 254 | #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) |
| 255 | |
| 256 | #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) |
| 257 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) |
| 258 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) |
| 259 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) |
| 260 | #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) |
| 261 | #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) |
| 262 | #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) |
| 263 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) |
| 264 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) |
| 265 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) |
| 266 | |
| 267 | #define SM501_DC_PANEL_HWC_BASE (0x0F0) |
| 268 | #define SM501_DC_PANEL_HWC_ADDR (0x0F0) |
| 269 | #define SM501_DC_PANEL_HWC_LOC (0x0F4) |
| 270 | #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) |
| 271 | #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) |
| 272 | |
| 273 | #define SM501_HWC_EN (1<<31) |
| 274 | |
| 275 | #define SM501_OFF_HWC_ADDR (0x00) |
| 276 | #define SM501_OFF_HWC_LOC (0x04) |
| 277 | #define SM501_OFF_HWC_COLOR_1_2 (0x08) |
| 278 | #define SM501_OFF_HWC_COLOR_3 (0x0C) |
| 279 | |
| 280 | #define SM501_DC_ALPHA_CONTROL (0x100) |
| 281 | #define SM501_DC_ALPHA_FB_ADDR (0x104) |
| 282 | #define SM501_DC_ALPHA_FB_OFFSET (0x108) |
| 283 | #define SM501_DC_ALPHA_TL_LOC (0x10C) |
| 284 | #define SM501_DC_ALPHA_BR_LOC (0x110) |
| 285 | #define SM501_DC_ALPHA_CHROMA_KEY (0x114) |
| 286 | #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) |
| 287 | |
| 288 | #define SM501_DC_CRT_CONTROL (0x200) |
| 289 | |
| 290 | #define SM501_DC_CRT_CONTROL_TVP (1<<15) |
| 291 | #define SM501_DC_CRT_CONTROL_CP (1<<14) |
| 292 | #define SM501_DC_CRT_CONTROL_VSP (1<<13) |
| 293 | #define SM501_DC_CRT_CONTROL_HSP (1<<12) |
| 294 | #define SM501_DC_CRT_CONTROL_VS (1<<11) |
| 295 | #define SM501_DC_CRT_CONTROL_BLANK (1<<10) |
| 296 | #define SM501_DC_CRT_CONTROL_SEL (1<<9) |
| 297 | #define SM501_DC_CRT_CONTROL_TE (1<<8) |
| 298 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
| 299 | #define SM501_DC_CRT_CONTROL_GAMMA (1<<3) |
| 300 | #define SM501_DC_CRT_CONTROL_ENABLE (1<<2) |
| 301 | |
| 302 | #define SM501_DC_CRT_CONTROL_8BPP (0<<0) |
| 303 | #define SM501_DC_CRT_CONTROL_16BPP (1<<0) |
| 304 | #define SM501_DC_CRT_CONTROL_32BPP (2<<0) |
| 305 | |
| 306 | #define SM501_DC_CRT_FB_ADDR (0x204) |
| 307 | #define SM501_DC_CRT_FB_OFFSET (0x208) |
| 308 | #define SM501_DC_CRT_H_TOT (0x20C) |
| 309 | #define SM501_DC_CRT_H_SYNC (0x210) |
| 310 | #define SM501_DC_CRT_V_TOT (0x214) |
| 311 | #define SM501_DC_CRT_V_SYNC (0x218) |
| 312 | #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) |
| 313 | #define SM501_DC_CRT_CUR_LINE (0x220) |
| 314 | #define SM501_DC_CRT_MONITOR_DETECT (0x224) |
| 315 | |
| 316 | #define SM501_DC_CRT_HWC_BASE (0x230) |
| 317 | #define SM501_DC_CRT_HWC_ADDR (0x230) |
| 318 | #define SM501_DC_CRT_HWC_LOC (0x234) |
| 319 | #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) |
| 320 | #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) |
| 321 | |
| 322 | #define SM501_DC_PANEL_PALETTE (0x400) |
| 323 | |
| 324 | #define SM501_DC_VIDEO_PALETTE (0x800) |
| 325 | |
| 326 | #define SM501_DC_CRT_PALETTE (0xC00) |
| 327 | |
| 328 | /* Zoom Video port base */ |
| 329 | #define SM501_ZVPORT (0x090000) |
| 330 | |
| 331 | /* AC97/I2S base */ |
| 332 | #define SM501_AC97 (0x0A0000) |
| 333 | |
| 334 | /* 8051 micro controller base */ |
| 335 | #define SM501_UCONTROLLER (0x0B0000) |
| 336 | |
| 337 | /* 8051 micro controller SRAM base */ |
| 338 | #define SM501_UCONTROLLER_SRAM (0x0C0000) |
| 339 | |
| 340 | /* DMA base */ |
| 341 | #define SM501_DMA (0x0D0000) |
| 342 | |
| 343 | /* 2d engine base */ |
| 344 | #define SM501_2D_ENGINE (0x100000) |
| 345 | #define SM501_2D_SOURCE (0x00) |
| 346 | #define SM501_2D_DESTINATION (0x04) |
| 347 | #define SM501_2D_DIMENSION (0x08) |
| 348 | #define SM501_2D_CONTROL (0x0C) |
| 349 | #define SM501_2D_PITCH (0x10) |
| 350 | #define SM501_2D_FOREGROUND (0x14) |
| 351 | #define SM501_2D_BACKGROUND (0x18) |
| 352 | #define SM501_2D_STRETCH (0x1C) |
| 353 | #define SM501_2D_COLOR_COMPARE (0x20) |
| 354 | #define SM501_2D_COLOR_COMPARE_MASK (0x24) |
| 355 | #define SM501_2D_MASK (0x28) |
| 356 | #define SM501_2D_CLIP_TL (0x2C) |
| 357 | #define SM501_2D_CLIP_BR (0x30) |
| 358 | #define SM501_2D_MONO_PATTERN_LOW (0x34) |
| 359 | #define SM501_2D_MONO_PATTERN_HIGH (0x38) |
| 360 | #define SM501_2D_WINDOW_WIDTH (0x3C) |
| 361 | #define SM501_2D_SOURCE_BASE (0x40) |
| 362 | #define SM501_2D_DESTINATION_BASE (0x44) |
| 363 | #define SM501_2D_ALPHA (0x48) |
| 364 | #define SM501_2D_WRAP (0x4C) |
| 365 | #define SM501_2D_STATUS (0x50) |
| 366 | |
| 367 | #define SM501_CSC_Y_SOURCE_BASE (0xC8) |
| 368 | #define SM501_CSC_CONSTANTS (0xCC) |
| 369 | #define SM501_CSC_Y_SOURCE_X (0xD0) |
| 370 | #define SM501_CSC_Y_SOURCE_Y (0xD4) |
| 371 | #define SM501_CSC_U_SOURCE_BASE (0xD8) |
| 372 | #define SM501_CSC_V_SOURCE_BASE (0xDC) |
| 373 | #define SM501_CSC_SOURCE_DIMENSION (0xE0) |
| 374 | #define SM501_CSC_SOURCE_PITCH (0xE4) |
| 375 | #define SM501_CSC_DESTINATION (0xE8) |
| 376 | #define SM501_CSC_DESTINATION_DIMENSION (0xEC) |
| 377 | #define SM501_CSC_DESTINATION_PITCH (0xF0) |
| 378 | #define SM501_CSC_SCALE_FACTOR (0xF4) |
| 379 | #define SM501_CSC_DESTINATION_BASE (0xF8) |
| 380 | #define SM501_CSC_CONTROL (0xFC) |
| 381 | |
| 382 | /* 2d engine data port base */ |
| 383 | #define SM501_2D_ENGINE_DATA (0x110000) |