Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ahci.c - AHCI SATA support |
| 3 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2004-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
domen@coderock.org | 87507cf | 2005-04-08 09:53:06 +0200 | [diff] [blame] | 42 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 43 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 45 | #include <scsi/scsi_cmnd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #include <linux/libata.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
| 48 | #define DRV_NAME "ahci" |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 49 | #define DRV_VERSION "2.3" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
| 51 | |
| 52 | enum { |
| 53 | AHCI_PCI_BAR = 5, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 54 | AHCI_MAX_PORTS = 32, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 56 | AHCI_DMA_BOUNDARY = 0xffffffff, |
Jens Axboe | be5d821 | 2007-05-22 09:45:39 +0200 | [diff] [blame] | 57 | AHCI_USE_CLUSTERING = 1, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 58 | AHCI_MAX_CMDS = 32, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 59 | AHCI_CMD_SZ = 32, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 60 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | AHCI_RX_FIS_SZ = 256, |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 62 | AHCI_CMD_TBL_CDB = 0x40, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 63 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
| 64 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
| 65 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
| 66 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | AHCI_RX_FIS_SZ, |
| 68 | AHCI_IRQ_ON_SG = (1 << 31), |
| 69 | AHCI_CMD_ATAPI = (1 << 5), |
| 70 | AHCI_CMD_WRITE = (1 << 6), |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 71 | AHCI_CMD_PREFETCH = (1 << 7), |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 72 | AHCI_CMD_RESET = (1 << 8), |
| 73 | AHCI_CMD_CLR_BUSY = (1 << 10), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 76 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | |
| 79 | board_ahci = 0, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 80 | board_ahci_pi = 1, |
| 81 | board_ahci_vt8251 = 2, |
| 82 | board_ahci_ign_iferr = 3, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 83 | board_ahci_sb600 = 4, |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 84 | board_ahci_mv = 5, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | |
| 86 | /* global controller registers */ |
| 87 | HOST_CAP = 0x00, /* host capabilities */ |
| 88 | HOST_CTL = 0x04, /* global host control */ |
| 89 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 90 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 91 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
| 92 | |
| 93 | /* HOST_CTL bits */ |
| 94 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 95 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
| 96 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 97 | |
| 98 | /* HOST_CAP bits */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 99 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 100 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 101 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
Tejun Heo | 979db80 | 2006-05-15 21:03:52 +0900 | [diff] [blame] | 102 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 103 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | |
| 105 | /* registers for each SATA port */ |
| 106 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 107 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 108 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 109 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 110 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 111 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 112 | PORT_CMD = 0x18, /* port command */ |
| 113 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 114 | PORT_SIG = 0x24, /* device TF signature */ |
| 115 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
| 116 | PORT_SCR = 0x28, /* SATA phy register block */ |
| 117 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 118 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 119 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 120 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
| 121 | |
| 122 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 123 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 124 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 125 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 126 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 127 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 128 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 129 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 130 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 131 | |
| 132 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 133 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 134 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 135 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 136 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 137 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 138 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 139 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 140 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 141 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 142 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
| 143 | PORT_IRQ_IF_ERR | |
| 144 | PORT_IRQ_CONNECT | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 145 | PORT_IRQ_PHYRDY | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 146 | PORT_IRQ_UNK_FIS, |
| 147 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
| 148 | PORT_IRQ_TF_ERR | |
| 149 | PORT_IRQ_HBUS_DATA_ERR, |
| 150 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
| 151 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
| 152 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | |
| 154 | /* PORT_CMD bits */ |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 155 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 157 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 158 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 159 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 161 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 162 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 163 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 164 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 165 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 166 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 167 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 168 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 169 | /* ap->flags bits */ |
Tejun Heo | 4aeb0e3 | 2006-11-01 17:58:33 +0900 | [diff] [blame] | 170 | AHCI_FLAG_NO_NCQ = (1 << 24), |
| 171 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 172 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 173 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 174 | AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */ |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 175 | AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */ |
| 176 | AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */ |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 177 | |
| 178 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 179 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
Tejun Heo | 3cadbcc | 2007-05-15 03:28:15 +0900 | [diff] [blame] | 180 | ATA_FLAG_SKIP_D2H_BSY | |
| 181 | ATA_FLAG_ACPI_SATA, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | }; |
| 183 | |
| 184 | struct ahci_cmd_hdr { |
| 185 | u32 opts; |
| 186 | u32 status; |
| 187 | u32 tbl_addr; |
| 188 | u32 tbl_addr_hi; |
| 189 | u32 reserved[4]; |
| 190 | }; |
| 191 | |
| 192 | struct ahci_sg { |
| 193 | u32 addr; |
| 194 | u32 addr_hi; |
| 195 | u32 reserved; |
| 196 | u32 flags_size; |
| 197 | }; |
| 198 | |
| 199 | struct ahci_host_priv { |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 200 | u32 cap; /* cap to use */ |
| 201 | u32 port_map; /* port map to use */ |
| 202 | u32 saved_cap; /* saved initial cap */ |
| 203 | u32 saved_port_map; /* saved initial port_map */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | struct ahci_port_priv { |
| 207 | struct ahci_cmd_hdr *cmd_slot; |
| 208 | dma_addr_t cmd_slot_dma; |
| 209 | void *cmd_tbl; |
| 210 | dma_addr_t cmd_tbl_dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | void *rx_fis; |
| 212 | dma_addr_t rx_fis_dma; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 213 | /* for NCQ spurious interrupt analysis */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 214 | unsigned int ncq_saw_d2h:1; |
| 215 | unsigned int ncq_saw_dmas:1; |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 216 | unsigned int ncq_saw_sdb:1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | }; |
| 218 | |
| 219 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); |
| 220 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); |
| 221 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 222 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | static void ahci_irq_clear(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | static int ahci_port_start(struct ata_port *ap); |
| 225 | static void ahci_port_stop(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
| 227 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
| 228 | static u8 ahci_check_status(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 229 | static void ahci_freeze(struct ata_port *ap); |
| 230 | static void ahci_thaw(struct ata_port *ap); |
| 231 | static void ahci_error_handler(struct ata_port *ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 232 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 233 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 234 | static int ahci_port_resume(struct ata_port *ap); |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 235 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
| 236 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 237 | u32 opts); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 238 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 239 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 240 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
| 241 | static int ahci_pci_device_resume(struct pci_dev *pdev); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 242 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 244 | static struct scsi_host_template ahci_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | .module = THIS_MODULE, |
| 246 | .name = DRV_NAME, |
| 247 | .ioctl = ata_scsi_ioctl, |
| 248 | .queuecommand = ata_scsi_queuecmd, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 249 | .change_queue_depth = ata_scsi_change_queue_depth, |
| 250 | .can_queue = AHCI_MAX_CMDS - 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | .this_id = ATA_SHT_THIS_ID, |
| 252 | .sg_tablesize = AHCI_MAX_SG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 254 | .emulated = ATA_SHT_EMULATED, |
| 255 | .use_clustering = AHCI_USE_CLUSTERING, |
| 256 | .proc_name = DRV_NAME, |
| 257 | .dma_boundary = AHCI_DMA_BOUNDARY, |
| 258 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 259 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | }; |
| 262 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 263 | static const struct ata_port_operations ahci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | .port_disable = ata_port_disable, |
| 265 | |
| 266 | .check_status = ahci_check_status, |
| 267 | .check_altstatus = ahci_check_status, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | .dev_select = ata_noop_dev_select, |
| 269 | |
| 270 | .tf_read = ahci_tf_read, |
| 271 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | .qc_prep = ahci_qc_prep, |
| 273 | .qc_issue = ahci_qc_issue, |
| 274 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 275 | .irq_clear = ahci_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 276 | .irq_on = ata_dummy_irq_on, |
| 277 | .irq_ack = ata_dummy_irq_ack, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | |
| 279 | .scr_read = ahci_scr_read, |
| 280 | .scr_write = ahci_scr_write, |
| 281 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 282 | .freeze = ahci_freeze, |
| 283 | .thaw = ahci_thaw, |
| 284 | |
| 285 | .error_handler = ahci_error_handler, |
| 286 | .post_internal_cmd = ahci_post_internal_cmd, |
| 287 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 288 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 289 | .port_suspend = ahci_port_suspend, |
| 290 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 291 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 292 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | .port_start = ahci_port_start, |
| 294 | .port_stop = ahci_port_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | }; |
| 296 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 297 | static const struct ata_port_operations ahci_vt8251_ops = { |
| 298 | .port_disable = ata_port_disable, |
| 299 | |
| 300 | .check_status = ahci_check_status, |
| 301 | .check_altstatus = ahci_check_status, |
| 302 | .dev_select = ata_noop_dev_select, |
| 303 | |
| 304 | .tf_read = ahci_tf_read, |
| 305 | |
| 306 | .qc_prep = ahci_qc_prep, |
| 307 | .qc_issue = ahci_qc_issue, |
| 308 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 309 | .irq_clear = ahci_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 310 | .irq_on = ata_dummy_irq_on, |
| 311 | .irq_ack = ata_dummy_irq_ack, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 312 | |
| 313 | .scr_read = ahci_scr_read, |
| 314 | .scr_write = ahci_scr_write, |
| 315 | |
| 316 | .freeze = ahci_freeze, |
| 317 | .thaw = ahci_thaw, |
| 318 | |
| 319 | .error_handler = ahci_vt8251_error_handler, |
| 320 | .post_internal_cmd = ahci_post_internal_cmd, |
| 321 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 322 | #ifdef CONFIG_PM |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 323 | .port_suspend = ahci_port_suspend, |
| 324 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 325 | #endif |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 326 | |
| 327 | .port_start = ahci_port_start, |
| 328 | .port_stop = ahci_port_stop, |
| 329 | }; |
| 330 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 331 | static const struct ata_port_info ahci_port_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | /* board_ahci */ |
| 333 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 334 | .flags = AHCI_FLAG_COMMON, |
Brett Russ | 7da7931 | 2005-09-01 21:53:34 -0400 | [diff] [blame] | 335 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 336 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | .port_ops = &ahci_ops, |
| 338 | }, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 339 | /* board_ahci_pi */ |
| 340 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 341 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 342 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 343 | .udma_mask = ATA_UDMA6, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 344 | .port_ops = &ahci_ops, |
| 345 | }, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 346 | /* board_ahci_vt8251 */ |
| 347 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 348 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME | |
| 349 | AHCI_FLAG_NO_NCQ, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 350 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 351 | .udma_mask = ATA_UDMA6, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 352 | .port_ops = &ahci_vt8251_ops, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 353 | }, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 354 | /* board_ahci_ign_iferr */ |
| 355 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 356 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 357 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 358 | .udma_mask = ATA_UDMA6, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 359 | .port_ops = &ahci_ops, |
| 360 | }, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 361 | /* board_ahci_sb600 */ |
| 362 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 363 | .flags = AHCI_FLAG_COMMON | |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 364 | AHCI_FLAG_IGN_SERR_INTERNAL | |
| 365 | AHCI_FLAG_32BIT_ONLY, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 366 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 367 | .udma_mask = ATA_UDMA6, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 368 | .port_ops = &ahci_ops, |
| 369 | }, |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 370 | /* board_ahci_mv */ |
| 371 | { |
| 372 | .sht = &ahci_sht, |
| 373 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 374 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
| 375 | ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI | |
| 376 | AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI | |
| 377 | AHCI_FLAG_MV_PATA, |
| 378 | .pio_mask = 0x1f, /* pio0-4 */ |
| 379 | .udma_mask = ATA_UDMA6, |
| 380 | .port_ops = &ahci_ops, |
| 381 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | }; |
| 383 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 384 | static const struct pci_device_id ahci_pci_tbl[] = { |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 385 | /* Intel */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 386 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
| 387 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ |
| 388 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ |
| 389 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ |
| 390 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ |
Tejun Heo | 82490c0 | 2007-01-23 15:13:39 +0900 | [diff] [blame] | 391 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 392 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
| 393 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ |
| 394 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ |
| 395 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 396 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ |
| 397 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ |
| 398 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ |
| 399 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ |
| 400 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ |
| 401 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ |
| 402 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ |
| 403 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ |
| 404 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ |
| 405 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ |
| 406 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ |
| 407 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ |
| 408 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ |
Jason Gaston | 8af12cd | 2007-03-02 17:39:46 -0800 | [diff] [blame] | 409 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 410 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ |
| 411 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ |
| 412 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 413 | |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 414 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
| 415 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 416 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 417 | |
| 418 | /* ATI */ |
Conke Hu | c65ec1c | 2007-04-11 18:23:14 +0800 | [diff] [blame] | 419 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
Henry Su | 2bcfdde | 2007-05-10 22:48:51 -0700 | [diff] [blame] | 420 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 421 | |
| 422 | /* VIA */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 423 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
Tejun Heo | bf33554 | 2007-04-11 17:27:14 +0900 | [diff] [blame] | 424 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 425 | |
| 426 | /* NVIDIA */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 427 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
| 428 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ |
| 429 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ |
| 430 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ |
Peer Chen | 6fbf5ba | 2006-12-20 14:18:00 -0500 | [diff] [blame] | 431 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
| 432 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ |
| 433 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ |
| 434 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ |
| 435 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ |
| 436 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ |
| 437 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ |
| 438 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ |
Peer Chen | 895663c | 2006-11-02 17:59:46 -0500 | [diff] [blame] | 439 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
| 440 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ |
| 441 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ |
| 442 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ |
| 443 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ |
| 444 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ |
| 445 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ |
| 446 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ |
Peer Chen | 0522b28 | 2007-06-07 18:05:12 +0800 | [diff] [blame] | 447 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
| 448 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ |
| 449 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ |
| 450 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ |
| 451 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ |
| 452 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ |
| 453 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ |
| 454 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ |
| 455 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ |
| 456 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ |
| 457 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ |
| 458 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ |
| 459 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ |
| 460 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ |
| 461 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ |
| 462 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ |
| 463 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ |
| 464 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ |
| 465 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ |
| 466 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ |
| 467 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ |
| 468 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ |
| 469 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ |
| 470 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 471 | |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 472 | /* SiS */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 473 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
| 474 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ |
| 475 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 476 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 477 | /* Marvell */ |
| 478 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ |
| 479 | |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 480 | /* Generic, PCI class code for AHCI */ |
| 481 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 482 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 483 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | { } /* terminate list */ |
| 485 | }; |
| 486 | |
| 487 | |
| 488 | static struct pci_driver ahci_pci_driver = { |
| 489 | .name = DRV_NAME, |
| 490 | .id_table = ahci_pci_tbl, |
| 491 | .probe = ahci_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 492 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 493 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 494 | .suspend = ahci_pci_device_suspend, |
| 495 | .resume = ahci_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 496 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 497 | }; |
| 498 | |
| 499 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 500 | static inline int ahci_nr_ports(u32 cap) |
| 501 | { |
| 502 | return (cap & 0x1f) + 1; |
| 503 | } |
| 504 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 505 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
| 506 | unsigned int port_no) |
| 507 | { |
| 508 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 509 | |
| 510 | return mmio + 0x100 + (port_no * 0x80); |
| 511 | } |
| 512 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 513 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 515 | return __ahci_port_base(ap->host, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | } |
| 517 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 518 | /** |
| 519 | * ahci_save_initial_config - Save and fixup initial config values |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 520 | * @pdev: target PCI device |
| 521 | * @pi: associated ATA port info |
| 522 | * @hpriv: host private area to store config values |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 523 | * |
| 524 | * Some registers containing configuration info might be setup by |
| 525 | * BIOS and might be cleared on reset. This function saves the |
| 526 | * initial values of those registers into @hpriv such that they |
| 527 | * can be restored after controller reset. |
| 528 | * |
| 529 | * If inconsistent, config values are fixed up by this function. |
| 530 | * |
| 531 | * LOCKING: |
| 532 | * None. |
| 533 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 534 | static void ahci_save_initial_config(struct pci_dev *pdev, |
| 535 | const struct ata_port_info *pi, |
| 536 | struct ahci_host_priv *hpriv) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 537 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 538 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 539 | u32 cap, port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 540 | int i; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 541 | |
| 542 | /* Values prefixed with saved_ are written back to host after |
| 543 | * reset. Values without are used for driver operation. |
| 544 | */ |
| 545 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); |
| 546 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); |
| 547 | |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 548 | /* some chips lie about 64bit support */ |
| 549 | if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) { |
| 550 | dev_printk(KERN_INFO, &pdev->dev, |
| 551 | "controller can't do 64bit DMA, forcing 32bit\n"); |
| 552 | cap &= ~HOST_CAP_64; |
| 553 | } |
| 554 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 555 | /* fixup zero port_map */ |
| 556 | if (!port_map) { |
Tejun Heo | a3d2cc5 | 2007-06-19 18:52:56 +0900 | [diff] [blame] | 557 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 558 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 559 | "PORTS_IMPL is zero, forcing 0x%x\n", port_map); |
| 560 | |
| 561 | /* write the fixed up value to the PI register */ |
| 562 | hpriv->saved_port_map = port_map; |
| 563 | } |
| 564 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 565 | /* |
| 566 | * Temporary Marvell 6145 hack: PATA port presence |
| 567 | * is asserted through the standard AHCI port |
| 568 | * presence register, as bit 4 (counting from 0) |
| 569 | */ |
| 570 | if (pi->flags & AHCI_FLAG_MV_PATA) { |
| 571 | dev_printk(KERN_ERR, &pdev->dev, |
| 572 | "MV_AHCI HACK: port_map %x -> %x\n", |
| 573 | hpriv->port_map, |
| 574 | hpriv->port_map & 0xf); |
| 575 | |
| 576 | port_map &= 0xf; |
| 577 | } |
| 578 | |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 579 | /* cross check port_map and cap.n_ports */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 580 | if (pi->flags & AHCI_FLAG_HONOR_PI) { |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 581 | u32 tmp_port_map = port_map; |
| 582 | int n_ports = ahci_nr_ports(cap); |
| 583 | |
| 584 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { |
| 585 | if (tmp_port_map & (1 << i)) { |
| 586 | n_ports--; |
| 587 | tmp_port_map &= ~(1 << i); |
| 588 | } |
| 589 | } |
| 590 | |
| 591 | /* Whine if inconsistent. No need to update cap. |
| 592 | * port_map is used to determine number of ports. |
| 593 | */ |
| 594 | if (n_ports || tmp_port_map) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 595 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 596 | "nr_ports (%u) and implemented port map " |
| 597 | "(0x%x) don't match\n", |
| 598 | ahci_nr_ports(cap), port_map); |
| 599 | } else { |
| 600 | /* fabricate port_map from cap.nr_ports */ |
| 601 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
| 602 | } |
| 603 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 604 | /* record values to use during operation */ |
| 605 | hpriv->cap = cap; |
| 606 | hpriv->port_map = port_map; |
| 607 | } |
| 608 | |
| 609 | /** |
| 610 | * ahci_restore_initial_config - Restore initial config |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 611 | * @host: target ATA host |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 612 | * |
| 613 | * Restore initial config stored by ahci_save_initial_config(). |
| 614 | * |
| 615 | * LOCKING: |
| 616 | * None. |
| 617 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 618 | static void ahci_restore_initial_config(struct ata_host *host) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 619 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 620 | struct ahci_host_priv *hpriv = host->private_data; |
| 621 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 622 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 623 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
| 624 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); |
| 625 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
| 626 | } |
| 627 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
| 629 | { |
| 630 | unsigned int sc_reg; |
| 631 | |
| 632 | switch (sc_reg_in) { |
| 633 | case SCR_STATUS: sc_reg = 0; break; |
| 634 | case SCR_CONTROL: sc_reg = 1; break; |
| 635 | case SCR_ERROR: sc_reg = 2; break; |
| 636 | case SCR_ACTIVE: sc_reg = 3; break; |
| 637 | default: |
| 638 | return 0xffffffffU; |
| 639 | } |
| 640 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 641 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | } |
| 643 | |
| 644 | |
| 645 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, |
| 646 | u32 val) |
| 647 | { |
| 648 | unsigned int sc_reg; |
| 649 | |
| 650 | switch (sc_reg_in) { |
| 651 | case SCR_STATUS: sc_reg = 0; break; |
| 652 | case SCR_CONTROL: sc_reg = 1; break; |
| 653 | case SCR_ERROR: sc_reg = 2; break; |
| 654 | case SCR_ACTIVE: sc_reg = 3; break; |
| 655 | default: |
| 656 | return; |
| 657 | } |
| 658 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 659 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | } |
| 661 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 662 | static void ahci_start_engine(struct ata_port *ap) |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 663 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 664 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 665 | u32 tmp; |
| 666 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 667 | /* start DMA */ |
Tejun Heo | 9f59205 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 668 | tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 669 | tmp |= PORT_CMD_START; |
| 670 | writel(tmp, port_mmio + PORT_CMD); |
| 671 | readl(port_mmio + PORT_CMD); /* flush */ |
| 672 | } |
| 673 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 674 | static int ahci_stop_engine(struct ata_port *ap) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 675 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 676 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 677 | u32 tmp; |
| 678 | |
| 679 | tmp = readl(port_mmio + PORT_CMD); |
| 680 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 681 | /* check if the HBA is idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 682 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
| 683 | return 0; |
| 684 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 685 | /* setting HBA to idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 686 | tmp &= ~PORT_CMD_START; |
| 687 | writel(tmp, port_mmio + PORT_CMD); |
| 688 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 689 | /* wait for engine to stop. This could be as long as 500 msec */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 690 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 691 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 692 | if (tmp & PORT_CMD_LIST_ON) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 693 | return -EIO; |
| 694 | |
| 695 | return 0; |
| 696 | } |
| 697 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 698 | static void ahci_start_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 699 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 700 | void __iomem *port_mmio = ahci_port_base(ap); |
| 701 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 702 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 703 | u32 tmp; |
| 704 | |
| 705 | /* set FIS registers */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 706 | if (hpriv->cap & HOST_CAP_64) |
| 707 | writel((pp->cmd_slot_dma >> 16) >> 16, |
| 708 | port_mmio + PORT_LST_ADDR_HI); |
| 709 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 710 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 711 | if (hpriv->cap & HOST_CAP_64) |
| 712 | writel((pp->rx_fis_dma >> 16) >> 16, |
| 713 | port_mmio + PORT_FIS_ADDR_HI); |
| 714 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 715 | |
| 716 | /* enable FIS reception */ |
| 717 | tmp = readl(port_mmio + PORT_CMD); |
| 718 | tmp |= PORT_CMD_FIS_RX; |
| 719 | writel(tmp, port_mmio + PORT_CMD); |
| 720 | |
| 721 | /* flush */ |
| 722 | readl(port_mmio + PORT_CMD); |
| 723 | } |
| 724 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 725 | static int ahci_stop_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 726 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 727 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 728 | u32 tmp; |
| 729 | |
| 730 | /* disable FIS reception */ |
| 731 | tmp = readl(port_mmio + PORT_CMD); |
| 732 | tmp &= ~PORT_CMD_FIS_RX; |
| 733 | writel(tmp, port_mmio + PORT_CMD); |
| 734 | |
| 735 | /* wait for completion, spec says 500ms, give it 1000 */ |
| 736 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, |
| 737 | PORT_CMD_FIS_ON, 10, 1000); |
| 738 | if (tmp & PORT_CMD_FIS_ON) |
| 739 | return -EBUSY; |
| 740 | |
| 741 | return 0; |
| 742 | } |
| 743 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 744 | static void ahci_power_up(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 745 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 746 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 747 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 748 | u32 cmd; |
| 749 | |
| 750 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
| 751 | |
| 752 | /* spin up device */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 753 | if (hpriv->cap & HOST_CAP_SSS) { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 754 | cmd |= PORT_CMD_SPIN_UP; |
| 755 | writel(cmd, port_mmio + PORT_CMD); |
| 756 | } |
| 757 | |
| 758 | /* wake up link */ |
| 759 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); |
| 760 | } |
| 761 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 762 | #ifdef CONFIG_PM |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 763 | static void ahci_power_down(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 764 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 765 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 766 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 767 | u32 cmd, scontrol; |
| 768 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 769 | if (!(hpriv->cap & HOST_CAP_SSS)) |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 770 | return; |
| 771 | |
| 772 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
| 773 | scontrol = readl(port_mmio + PORT_SCR_CTL); |
| 774 | scontrol &= ~0xf; |
| 775 | writel(scontrol, port_mmio + PORT_SCR_CTL); |
| 776 | |
| 777 | /* then set PxCMD.SUD to 0 */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 778 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 779 | cmd &= ~PORT_CMD_SPIN_UP; |
| 780 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 781 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 782 | #endif |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 783 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 784 | static void ahci_start_port(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 785 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 786 | /* enable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 787 | ahci_start_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 788 | |
| 789 | /* enable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 790 | ahci_start_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 791 | } |
| 792 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 793 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 794 | { |
| 795 | int rc; |
| 796 | |
| 797 | /* disable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 798 | rc = ahci_stop_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 799 | if (rc) { |
| 800 | *emsg = "failed to stop engine"; |
| 801 | return rc; |
| 802 | } |
| 803 | |
| 804 | /* disable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 805 | rc = ahci_stop_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 806 | if (rc) { |
| 807 | *emsg = "failed stop FIS RX"; |
| 808 | return rc; |
| 809 | } |
| 810 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 811 | return 0; |
| 812 | } |
| 813 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 814 | static int ahci_reset_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 815 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 816 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 817 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 818 | u32 tmp; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 819 | |
| 820 | /* global controller reset */ |
| 821 | tmp = readl(mmio + HOST_CTL); |
| 822 | if ((tmp & HOST_RESET) == 0) { |
| 823 | writel(tmp | HOST_RESET, mmio + HOST_CTL); |
| 824 | readl(mmio + HOST_CTL); /* flush */ |
| 825 | } |
| 826 | |
| 827 | /* reset must complete within 1 second, or |
| 828 | * the hardware should be considered fried. |
| 829 | */ |
| 830 | ssleep(1); |
| 831 | |
| 832 | tmp = readl(mmio + HOST_CTL); |
| 833 | if (tmp & HOST_RESET) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 834 | dev_printk(KERN_ERR, host->dev, |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 835 | "controller reset failed (0x%x)\n", tmp); |
| 836 | return -EIO; |
| 837 | } |
| 838 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 839 | /* turn on AHCI mode */ |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 840 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
| 841 | (void) readl(mmio + HOST_CTL); /* flush */ |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 842 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 843 | /* some registers might be cleared on reset. restore initial values */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 844 | ahci_restore_initial_config(host); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 845 | |
| 846 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 847 | u16 tmp16; |
| 848 | |
| 849 | /* configure PCS */ |
| 850 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 851 | tmp16 |= 0xf; |
| 852 | pci_write_config_word(pdev, 0x92, tmp16); |
| 853 | } |
| 854 | |
| 855 | return 0; |
| 856 | } |
| 857 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 858 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
| 859 | int port_no, void __iomem *mmio, |
| 860 | void __iomem *port_mmio) |
| 861 | { |
| 862 | const char *emsg = NULL; |
| 863 | int rc; |
| 864 | u32 tmp; |
| 865 | |
| 866 | /* make sure port is not active */ |
| 867 | rc = ahci_deinit_port(ap, &emsg); |
| 868 | if (rc) |
| 869 | dev_printk(KERN_WARNING, &pdev->dev, |
| 870 | "%s (%d)\n", emsg, rc); |
| 871 | |
| 872 | /* clear SError */ |
| 873 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 874 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); |
| 875 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 876 | |
| 877 | /* clear port IRQ */ |
| 878 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 879 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 880 | if (tmp) |
| 881 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 882 | |
| 883 | writel(1 << port_no, mmio + HOST_IRQ_STAT); |
| 884 | } |
| 885 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 886 | static void ahci_init_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 887 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 888 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 889 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 890 | int i; |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 891 | void __iomem *port_mmio; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 892 | u32 tmp; |
| 893 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 894 | if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) { |
| 895 | port_mmio = __ahci_port_base(host, 4); |
| 896 | |
| 897 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 898 | |
| 899 | /* clear port IRQ */ |
| 900 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 901 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 902 | if (tmp) |
| 903 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 904 | } |
| 905 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 906 | for (i = 0; i < host->n_ports; i++) { |
| 907 | struct ata_port *ap = host->ports[i]; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 908 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 909 | port_mmio = ahci_port_base(ap); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 910 | if (ata_port_is_dummy(ap)) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 911 | continue; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 912 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 913 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 914 | } |
| 915 | |
| 916 | tmp = readl(mmio + HOST_CTL); |
| 917 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 918 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 919 | tmp = readl(mmio + HOST_CTL); |
| 920 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 921 | } |
| 922 | |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 923 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 925 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 926 | struct ata_taskfile tf; |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 927 | u32 tmp; |
| 928 | |
| 929 | tmp = readl(port_mmio + PORT_SIG); |
| 930 | tf.lbah = (tmp >> 24) & 0xff; |
| 931 | tf.lbam = (tmp >> 16) & 0xff; |
| 932 | tf.lbal = (tmp >> 8) & 0xff; |
| 933 | tf.nsect = (tmp) & 0xff; |
| 934 | |
| 935 | return ata_dev_classify(&tf); |
| 936 | } |
| 937 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 938 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 939 | u32 opts) |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 940 | { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 941 | dma_addr_t cmd_tbl_dma; |
| 942 | |
| 943 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; |
| 944 | |
| 945 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); |
| 946 | pp->cmd_slot[tag].status = 0; |
| 947 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); |
| 948 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 949 | } |
| 950 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 951 | static int ahci_clo(struct ata_port *ap) |
| 952 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 953 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 954 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 955 | u32 tmp; |
| 956 | |
| 957 | if (!(hpriv->cap & HOST_CAP_CLO)) |
| 958 | return -EOPNOTSUPP; |
| 959 | |
| 960 | tmp = readl(port_mmio + PORT_CMD); |
| 961 | tmp |= PORT_CMD_CLO; |
| 962 | writel(tmp, port_mmio + PORT_CMD); |
| 963 | |
| 964 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 965 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); |
| 966 | if (tmp & PORT_CMD_CLO) |
| 967 | return -EIO; |
| 968 | |
| 969 | return 0; |
| 970 | } |
| 971 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 972 | static int ahci_softreset(struct ata_port *ap, unsigned int *class, |
| 973 | unsigned long deadline) |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 974 | { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 975 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 976 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 977 | const u32 cmd_fis_len = 5; /* five dwords */ |
| 978 | const char *reason = NULL; |
| 979 | struct ata_taskfile tf; |
Tejun Heo | 75fe180 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 980 | u32 tmp; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 981 | u8 *fis; |
| 982 | int rc; |
| 983 | |
| 984 | DPRINTK("ENTER\n"); |
| 985 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 986 | if (ata_port_offline(ap)) { |
Tejun Heo | c2a6585 | 2006-04-03 01:58:06 +0900 | [diff] [blame] | 987 | DPRINTK("PHY reports no device\n"); |
| 988 | *class = ATA_DEV_NONE; |
| 989 | return 0; |
| 990 | } |
| 991 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 992 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 993 | rc = ahci_stop_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 994 | if (rc) { |
| 995 | reason = "failed to stop engine"; |
| 996 | goto fail_restart; |
| 997 | } |
| 998 | |
| 999 | /* check BUSY/DRQ, perform Command List Override if necessary */ |
Tejun Heo | 1244a19 | 2006-11-01 17:19:18 +0900 | [diff] [blame] | 1000 | if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) { |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1001 | rc = ahci_clo(ap); |
| 1002 | |
| 1003 | if (rc == -EOPNOTSUPP) { |
| 1004 | reason = "port busy but CLO unavailable"; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1005 | goto fail_restart; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1006 | } else if (rc) { |
| 1007 | reason = "port busy but CLO failed"; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1008 | goto fail_restart; |
| 1009 | } |
| 1010 | } |
| 1011 | |
| 1012 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1013 | ahci_start_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1014 | |
Tejun Heo | 3373efd | 2006-05-15 20:57:53 +0900 | [diff] [blame] | 1015 | ata_tf_init(ap->device, &tf); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1016 | fis = pp->cmd_tbl; |
| 1017 | |
| 1018 | /* issue the first D2H Register FIS */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1019 | ahci_fill_cmd_slot(pp, 0, |
| 1020 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1021 | |
| 1022 | tf.ctl |= ATA_SRST; |
Tejun Heo | 9977126 | 2007-07-16 14:29:38 +0900 | [diff] [blame^] | 1023 | ata_tf_to_fis(&tf, 0, 0, fis); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1024 | |
| 1025 | writel(1, port_mmio + PORT_CMD_ISSUE); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1026 | |
Tejun Heo | 75fe180 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 1027 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
| 1028 | if (tmp & 0x1) { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1029 | rc = -EIO; |
| 1030 | reason = "1st FIS failed"; |
| 1031 | goto fail; |
| 1032 | } |
| 1033 | |
| 1034 | /* spec says at least 5us, but be generous and sleep for 1ms */ |
| 1035 | msleep(1); |
| 1036 | |
| 1037 | /* issue the second D2H Register FIS */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1038 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1039 | |
| 1040 | tf.ctl &= ~ATA_SRST; |
Tejun Heo | 9977126 | 2007-07-16 14:29:38 +0900 | [diff] [blame^] | 1041 | ata_tf_to_fis(&tf, 0, 0, fis); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1042 | |
| 1043 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 1044 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1045 | |
| 1046 | /* spec mandates ">= 2ms" before checking status. |
| 1047 | * We wait 150ms, because that was the magic delay used for |
| 1048 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time |
| 1049 | * between when the ATA command register is written, and then |
| 1050 | * status is checked. Because waiting for "a while" before |
| 1051 | * checking status is fine, post SRST, we perform this magic |
| 1052 | * delay here as well. |
| 1053 | */ |
| 1054 | msleep(150); |
| 1055 | |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1056 | rc = ata_wait_ready(ap, deadline); |
| 1057 | /* link occupied, -ENODEV too is an error */ |
| 1058 | if (rc) { |
| 1059 | reason = "device not ready"; |
| 1060 | goto fail; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1061 | } |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1062 | *class = ahci_dev_classify(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1063 | |
| 1064 | DPRINTK("EXIT, class=%u\n", *class); |
| 1065 | return 0; |
| 1066 | |
| 1067 | fail_restart: |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1068 | ahci_start_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1069 | fail: |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 1070 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1071 | return rc; |
| 1072 | } |
| 1073 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1074 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class, |
| 1075 | unsigned long deadline) |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1076 | { |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1077 | struct ahci_port_priv *pp = ap->private_data; |
| 1078 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1079 | struct ata_taskfile tf; |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1080 | int rc; |
| 1081 | |
| 1082 | DPRINTK("ENTER\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1084 | ahci_stop_engine(ap); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1085 | |
| 1086 | /* clear D2H reception area to properly wait for D2H FIS */ |
| 1087 | ata_tf_init(ap->device, &tf); |
Tejun Heo | dfd7a3d | 2007-01-26 15:37:20 +0900 | [diff] [blame] | 1088 | tf.command = 0x80; |
Tejun Heo | 9977126 | 2007-07-16 14:29:38 +0900 | [diff] [blame^] | 1089 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1090 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1091 | rc = sata_std_hardreset(ap, class, deadline); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1092 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1093 | ahci_start_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1094 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1095 | if (rc == 0 && ata_port_online(ap)) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1096 | *class = ahci_dev_classify(ap); |
| 1097 | if (*class == ATA_DEV_UNKNOWN) |
| 1098 | *class = ATA_DEV_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1099 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1100 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1101 | return rc; |
| 1102 | } |
| 1103 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1104 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class, |
| 1105 | unsigned long deadline) |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1106 | { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1107 | int rc; |
| 1108 | |
| 1109 | DPRINTK("ENTER\n"); |
| 1110 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1111 | ahci_stop_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1112 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1113 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context), |
| 1114 | deadline); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1115 | |
| 1116 | /* vt8251 needs SError cleared for the port to operate */ |
| 1117 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); |
| 1118 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1119 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1120 | |
| 1121 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1122 | |
| 1123 | /* vt8251 doesn't clear BSY on signature FIS reception, |
| 1124 | * request follow-up softreset. |
| 1125 | */ |
| 1126 | return rc ?: -EAGAIN; |
| 1127 | } |
| 1128 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1129 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
| 1130 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1131 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1132 | u32 new_tmp, tmp; |
| 1133 | |
| 1134 | ata_std_postreset(ap, class); |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1135 | |
| 1136 | /* Make sure port's ATAPI bit is set appropriately */ |
| 1137 | new_tmp = tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1138 | if (*class == ATA_DEV_ATAPI) |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1139 | new_tmp |= PORT_CMD_ATAPI; |
| 1140 | else |
| 1141 | new_tmp &= ~PORT_CMD_ATAPI; |
| 1142 | if (new_tmp != tmp) { |
| 1143 | writel(new_tmp, port_mmio + PORT_CMD); |
| 1144 | readl(port_mmio + PORT_CMD); /* flush */ |
| 1145 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | } |
| 1147 | |
| 1148 | static u8 ahci_check_status(struct ata_port *ap) |
| 1149 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1150 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1151 | |
| 1152 | return readl(mmio + PORT_TFDATA) & 0xFF; |
| 1153 | } |
| 1154 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1155 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 1156 | { |
| 1157 | struct ahci_port_priv *pp = ap->private_data; |
| 1158 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1159 | |
| 1160 | ata_tf_from_fis(d2h_fis, tf); |
| 1161 | } |
| 1162 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1163 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1165 | struct scatterlist *sg; |
| 1166 | struct ahci_sg *ahci_sg; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1167 | unsigned int n_sg = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | |
| 1169 | VPRINTK("ENTER\n"); |
| 1170 | |
| 1171 | /* |
| 1172 | * Next, the S/G list. |
| 1173 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1174 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1175 | ata_for_each_sg(sg, qc) { |
| 1176 | dma_addr_t addr = sg_dma_address(sg); |
| 1177 | u32 sg_len = sg_dma_len(sg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1178 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1179 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 1180 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 1181 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1182 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1183 | ahci_sg++; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1184 | n_sg++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1185 | } |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1186 | |
| 1187 | return n_sg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1188 | } |
| 1189 | |
| 1190 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
| 1191 | { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1192 | struct ata_port *ap = qc->ap; |
| 1193 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1194 | int is_atapi = is_atapi_taskfile(&qc->tf); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1195 | void *cmd_tbl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1196 | u32 opts; |
| 1197 | const u32 cmd_fis_len = 5; /* five dwords */ |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1198 | unsigned int n_elem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1199 | |
| 1200 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1201 | * Fill in command table information. First, the header, |
| 1202 | * a SATA Register - Host to Device command FIS. |
| 1203 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1204 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
| 1205 | |
Tejun Heo | 9977126 | 2007-07-16 14:29:38 +0900 | [diff] [blame^] | 1206 | ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1207 | if (is_atapi) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1208 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
| 1209 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1210 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1211 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1212 | n_elem = 0; |
| 1213 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1214 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1215 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1216 | /* |
| 1217 | * Fill in command slot information. |
| 1218 | */ |
| 1219 | opts = cmd_fis_len | n_elem << 16; |
| 1220 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 1221 | opts |= AHCI_CMD_WRITE; |
| 1222 | if (is_atapi) |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 1223 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1224 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1225 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1226 | } |
| 1227 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1228 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1230 | struct ahci_port_priv *pp = ap->private_data; |
| 1231 | struct ata_eh_info *ehi = &ap->eh_info; |
| 1232 | unsigned int err_mask = 0, action = 0; |
| 1233 | struct ata_queued_cmd *qc; |
| 1234 | u32 serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1236 | ata_ehi_clear_desc(ehi); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 1237 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1238 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
| 1239 | serror = ahci_scr_read(ap, SCR_ERROR); |
| 1240 | ahci_scr_write(ap, SCR_ERROR, serror); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1241 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1242 | /* analyze @irq_stat */ |
| 1243 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1244 | |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 1245 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
| 1246 | if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) |
| 1247 | irq_stat &= ~PORT_IRQ_IF_ERR; |
| 1248 | |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 1249 | if (irq_stat & PORT_IRQ_TF_ERR) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1250 | err_mask |= AC_ERR_DEV; |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 1251 | if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL) |
| 1252 | serror &= ~SERR_INTERNAL; |
| 1253 | } |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1254 | |
| 1255 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { |
| 1256 | err_mask |= AC_ERR_HOST_BUS; |
| 1257 | action |= ATA_EH_SOFTRESET; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1258 | } |
| 1259 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1260 | if (irq_stat & PORT_IRQ_IF_ERR) { |
| 1261 | err_mask |= AC_ERR_ATA_BUS; |
| 1262 | action |= ATA_EH_SOFTRESET; |
| 1263 | ata_ehi_push_desc(ehi, ", interface fatal error"); |
| 1264 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1265 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1266 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1267 | ata_ehi_hotplugged(ehi); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1268 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
| 1269 | "connection status changed" : "PHY RDY changed"); |
| 1270 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1271 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1272 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
| 1273 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1275 | err_mask |= AC_ERR_HSM; |
| 1276 | action |= ATA_EH_SOFTRESET; |
| 1277 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", |
| 1278 | unk[0], unk[1], unk[2], unk[3]); |
| 1279 | } |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 1280 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1281 | /* okay, let's hand over to EH */ |
| 1282 | ehi->serror |= serror; |
| 1283 | ehi->action |= action; |
| 1284 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1285 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1286 | if (qc) |
| 1287 | qc->err_mask |= err_mask; |
| 1288 | else |
| 1289 | ehi->err_mask |= err_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1290 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1291 | if (irq_stat & PORT_IRQ_FREEZE) |
| 1292 | ata_port_freeze(ap); |
| 1293 | else |
| 1294 | ata_port_abort(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1295 | } |
| 1296 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1297 | static void ahci_port_intr(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1298 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1299 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1300 | struct ata_eh_info *ehi = &ap->eh_info; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1301 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1302 | u32 status, qc_active; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1303 | int rc, known_irq = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1304 | |
| 1305 | status = readl(port_mmio + PORT_IRQ_STAT); |
| 1306 | writel(status, port_mmio + PORT_IRQ_STAT); |
| 1307 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1308 | if (unlikely(status & PORT_IRQ_ERROR)) { |
| 1309 | ahci_error_intr(ap, status); |
| 1310 | return; |
| 1311 | } |
| 1312 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1313 | if (ap->sactive) |
| 1314 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
| 1315 | else |
| 1316 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); |
| 1317 | |
| 1318 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); |
| 1319 | if (rc > 0) |
| 1320 | return; |
| 1321 | if (rc < 0) { |
| 1322 | ehi->err_mask |= AC_ERR_HSM; |
| 1323 | ehi->action |= ATA_EH_SOFTRESET; |
| 1324 | ata_port_freeze(ap); |
| 1325 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1326 | } |
| 1327 | |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 1328 | /* hmmm... a spurious interupt */ |
| 1329 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1330 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
| 1331 | * implementation for non-NCQ commands. |
| 1332 | */ |
| 1333 | if (!ap->sactive) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1334 | return; |
| 1335 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1336 | if (status & PORT_IRQ_D2H_REG_FIS) { |
| 1337 | if (!pp->ncq_saw_d2h) |
| 1338 | ata_port_printk(ap, KERN_INFO, |
| 1339 | "D2H reg with I during NCQ, " |
| 1340 | "this message won't be printed again\n"); |
| 1341 | pp->ncq_saw_d2h = 1; |
| 1342 | known_irq = 1; |
| 1343 | } |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 1344 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1345 | if (status & PORT_IRQ_DMAS_FIS) { |
| 1346 | if (!pp->ncq_saw_dmas) |
| 1347 | ata_port_printk(ap, KERN_INFO, |
| 1348 | "DMAS FIS during NCQ, " |
| 1349 | "this message won't be printed again\n"); |
| 1350 | pp->ncq_saw_dmas = 1; |
| 1351 | known_irq = 1; |
| 1352 | } |
| 1353 | |
Tejun Heo | a2bbd0c | 2007-02-21 16:34:25 +0900 | [diff] [blame] | 1354 | if (status & PORT_IRQ_SDB_FIS) { |
Al Viro | 04d4f7a | 2007-02-09 16:39:30 +0000 | [diff] [blame] | 1355 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1356 | |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 1357 | if (le32_to_cpu(f[1])) { |
| 1358 | /* SDB FIS containing spurious completions |
| 1359 | * might be dangerous, whine and fail commands |
| 1360 | * with HSM violation. EH will turn off NCQ |
| 1361 | * after several such failures. |
| 1362 | */ |
| 1363 | ata_ehi_push_desc(ehi, |
| 1364 | "spurious completions during NCQ " |
| 1365 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", |
| 1366 | readl(port_mmio + PORT_CMD_ISSUE), |
| 1367 | readl(port_mmio + PORT_SCR_ACT), |
| 1368 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); |
| 1369 | ehi->err_mask |= AC_ERR_HSM; |
| 1370 | ehi->action |= ATA_EH_SOFTRESET; |
| 1371 | ata_port_freeze(ap); |
| 1372 | } else { |
| 1373 | if (!pp->ncq_saw_sdb) |
| 1374 | ata_port_printk(ap, KERN_INFO, |
| 1375 | "spurious SDB FIS %08x:%08x during NCQ, " |
| 1376 | "this message won't be printed again\n", |
| 1377 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); |
| 1378 | pp->ncq_saw_sdb = 1; |
| 1379 | } |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1380 | known_irq = 1; |
| 1381 | } |
| 1382 | |
| 1383 | if (!known_irq) |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1384 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1385 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1386 | status, ap->active_tag, ap->sactive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | } |
| 1388 | |
| 1389 | static void ahci_irq_clear(struct ata_port *ap) |
| 1390 | { |
| 1391 | /* TODO */ |
| 1392 | } |
| 1393 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1394 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1395 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1396 | struct ata_host *host = dev_instance; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1397 | struct ahci_host_priv *hpriv; |
| 1398 | unsigned int i, handled = 0; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1399 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1400 | u32 irq_stat, irq_ack = 0; |
| 1401 | |
| 1402 | VPRINTK("ENTER\n"); |
| 1403 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1404 | hpriv = host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1405 | mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | |
| 1407 | /* sigh. 0xffffffff is a valid return from h/w */ |
| 1408 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
| 1409 | irq_stat &= hpriv->port_map; |
| 1410 | if (!irq_stat) |
| 1411 | return IRQ_NONE; |
| 1412 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1413 | spin_lock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1414 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1415 | for (i = 0; i < host->n_ports; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1416 | struct ata_port *ap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1417 | |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1418 | if (!(irq_stat & (1 << i))) |
| 1419 | continue; |
| 1420 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1421 | ap = host->ports[i]; |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1422 | if (ap) { |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1423 | ahci_port_intr(ap); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1424 | VPRINTK("port %u\n", i); |
| 1425 | } else { |
| 1426 | VPRINTK("port %u (no irq)\n", i); |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 1427 | if (ata_ratelimit()) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1428 | dev_printk(KERN_WARNING, host->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1429 | "interrupt on disabled port %u\n", i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1430 | } |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1431 | |
| 1432 | irq_ack |= (1 << i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1433 | } |
| 1434 | |
| 1435 | if (irq_ack) { |
| 1436 | writel(irq_ack, mmio + HOST_IRQ_STAT); |
| 1437 | handled = 1; |
| 1438 | } |
| 1439 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1440 | spin_unlock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1441 | |
| 1442 | VPRINTK("EXIT\n"); |
| 1443 | |
| 1444 | return IRQ_RETVAL(handled); |
| 1445 | } |
| 1446 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1447 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1448 | { |
| 1449 | struct ata_port *ap = qc->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1450 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1451 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1452 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 1453 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
| 1454 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1455 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1456 | |
| 1457 | return 0; |
| 1458 | } |
| 1459 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1460 | static void ahci_freeze(struct ata_port *ap) |
| 1461 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1462 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1463 | |
| 1464 | /* turn IRQ off */ |
| 1465 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 1466 | } |
| 1467 | |
| 1468 | static void ahci_thaw(struct ata_port *ap) |
| 1469 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1470 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1471 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1472 | u32 tmp; |
| 1473 | |
| 1474 | /* clear IRQ */ |
| 1475 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1476 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
Tejun Heo | a718728 | 2007-01-27 11:04:26 +0900 | [diff] [blame] | 1477 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1478 | |
| 1479 | /* turn IRQ back on */ |
| 1480 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); |
| 1481 | } |
| 1482 | |
| 1483 | static void ahci_error_handler(struct ata_port *ap) |
| 1484 | { |
Tejun Heo | b51e9e5 | 2006-06-29 01:29:30 +0900 | [diff] [blame] | 1485 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1486 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1487 | ahci_stop_engine(ap); |
| 1488 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1489 | } |
| 1490 | |
| 1491 | /* perform recovery */ |
Tejun Heo | 4aeb0e3 | 2006-11-01 17:58:33 +0900 | [diff] [blame] | 1492 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, |
Tejun Heo | f5914a4 | 2006-05-31 18:27:48 +0900 | [diff] [blame] | 1493 | ahci_postreset); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1494 | } |
| 1495 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1496 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
| 1497 | { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1498 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1499 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1500 | ahci_stop_engine(ap); |
| 1501 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1502 | } |
| 1503 | |
| 1504 | /* perform recovery */ |
| 1505 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, |
| 1506 | ahci_postreset); |
| 1507 | } |
| 1508 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1509 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
| 1510 | { |
| 1511 | struct ata_port *ap = qc->ap; |
| 1512 | |
Tejun Heo | a51d644 | 2007-03-20 15:24:11 +0900 | [diff] [blame] | 1513 | if (qc->flags & ATA_QCFLAG_FAILED) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1514 | /* make DMA engine forget about the failed command */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1515 | ahci_stop_engine(ap); |
| 1516 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1517 | } |
| 1518 | } |
| 1519 | |
Alexey Dobriyan | 028a259 | 2007-07-17 23:48:48 +0400 | [diff] [blame] | 1520 | static int ahci_port_resume(struct ata_port *ap) |
| 1521 | { |
| 1522 | ahci_power_up(ap); |
| 1523 | ahci_start_port(ap); |
| 1524 | |
| 1525 | return 0; |
| 1526 | } |
| 1527 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1528 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1529 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
| 1530 | { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1531 | const char *emsg = NULL; |
| 1532 | int rc; |
| 1533 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1534 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1535 | if (rc == 0) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1536 | ahci_power_down(ap); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1537 | else { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1538 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1539 | ahci_start_port(ap); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1540 | } |
| 1541 | |
| 1542 | return rc; |
| 1543 | } |
| 1544 | |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1545 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
| 1546 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1547 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1548 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1549 | u32 ctl; |
| 1550 | |
| 1551 | if (mesg.event == PM_EVENT_SUSPEND) { |
| 1552 | /* AHCI spec rev1.1 section 8.3.3: |
| 1553 | * Software must disable interrupts prior to requesting a |
| 1554 | * transition of the HBA to D3 state. |
| 1555 | */ |
| 1556 | ctl = readl(mmio + HOST_CTL); |
| 1557 | ctl &= ~HOST_IRQ_EN; |
| 1558 | writel(ctl, mmio + HOST_CTL); |
| 1559 | readl(mmio + HOST_CTL); /* flush */ |
| 1560 | } |
| 1561 | |
| 1562 | return ata_pci_device_suspend(pdev, mesg); |
| 1563 | } |
| 1564 | |
| 1565 | static int ahci_pci_device_resume(struct pci_dev *pdev) |
| 1566 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1567 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1568 | int rc; |
| 1569 | |
Tejun Heo | 553c4aa | 2006-12-26 19:39:50 +0900 | [diff] [blame] | 1570 | rc = ata_pci_device_do_resume(pdev); |
| 1571 | if (rc) |
| 1572 | return rc; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1573 | |
| 1574 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1575 | rc = ahci_reset_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1576 | if (rc) |
| 1577 | return rc; |
| 1578 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1579 | ahci_init_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1580 | } |
| 1581 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1582 | ata_host_resume(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1583 | |
| 1584 | return 0; |
| 1585 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1586 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1587 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1588 | static int ahci_port_start(struct ata_port *ap) |
| 1589 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1590 | struct device *dev = ap->host->dev; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1591 | struct ahci_port_priv *pp; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1592 | void *mem; |
| 1593 | dma_addr_t mem_dma; |
| 1594 | int rc; |
| 1595 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1596 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1597 | if (!pp) |
| 1598 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1599 | |
| 1600 | rc = ata_pad_alloc(ap, dev); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1601 | if (rc) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1602 | return rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1603 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1604 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
| 1605 | GFP_KERNEL); |
| 1606 | if (!mem) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1607 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1608 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 1609 | |
| 1610 | /* |
| 1611 | * First item in chunk of DMA memory: 32-slot command table, |
| 1612 | * 32 bytes each in size |
| 1613 | */ |
| 1614 | pp->cmd_slot = mem; |
| 1615 | pp->cmd_slot_dma = mem_dma; |
| 1616 | |
| 1617 | mem += AHCI_CMD_SLOT_SZ; |
| 1618 | mem_dma += AHCI_CMD_SLOT_SZ; |
| 1619 | |
| 1620 | /* |
| 1621 | * Second item: Received-FIS area |
| 1622 | */ |
| 1623 | pp->rx_fis = mem; |
| 1624 | pp->rx_fis_dma = mem_dma; |
| 1625 | |
| 1626 | mem += AHCI_RX_FIS_SZ; |
| 1627 | mem_dma += AHCI_RX_FIS_SZ; |
| 1628 | |
| 1629 | /* |
| 1630 | * Third item: data area for storing a single command |
| 1631 | * and its scatter-gather table |
| 1632 | */ |
| 1633 | pp->cmd_tbl = mem; |
| 1634 | pp->cmd_tbl_dma = mem_dma; |
| 1635 | |
| 1636 | ap->private_data = pp; |
| 1637 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1638 | /* engage engines, captain */ |
| 1639 | return ahci_port_resume(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1640 | } |
| 1641 | |
| 1642 | static void ahci_port_stop(struct ata_port *ap) |
| 1643 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1644 | const char *emsg = NULL; |
| 1645 | int rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1646 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1647 | /* de-initialize port */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1648 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1649 | if (rc) |
| 1650 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1651 | } |
| 1652 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1653 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1654 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1655 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1656 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1657 | if (using_dac && |
| 1658 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 1659 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 1660 | if (rc) { |
| 1661 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1662 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1663 | dev_printk(KERN_ERR, &pdev->dev, |
| 1664 | "64-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1665 | return rc; |
| 1666 | } |
| 1667 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1668 | } else { |
| 1669 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 1670 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1671 | dev_printk(KERN_ERR, &pdev->dev, |
| 1672 | "32-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1673 | return rc; |
| 1674 | } |
| 1675 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1676 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1677 | dev_printk(KERN_ERR, &pdev->dev, |
| 1678 | "32-bit consistent DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1679 | return rc; |
| 1680 | } |
| 1681 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1682 | return 0; |
| 1683 | } |
| 1684 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1685 | static void ahci_print_info(struct ata_host *host) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1686 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1687 | struct ahci_host_priv *hpriv = host->private_data; |
| 1688 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 1689 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1690 | u32 vers, cap, impl, speed; |
| 1691 | const char *speed_s; |
| 1692 | u16 cc; |
| 1693 | const char *scc_s; |
| 1694 | |
| 1695 | vers = readl(mmio + HOST_VERSION); |
| 1696 | cap = hpriv->cap; |
| 1697 | impl = hpriv->port_map; |
| 1698 | |
| 1699 | speed = (cap >> 20) & 0xf; |
| 1700 | if (speed == 1) |
| 1701 | speed_s = "1.5"; |
| 1702 | else if (speed == 2) |
| 1703 | speed_s = "3"; |
| 1704 | else |
| 1705 | speed_s = "?"; |
| 1706 | |
| 1707 | pci_read_config_word(pdev, 0x0a, &cc); |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1708 | if (cc == PCI_CLASS_STORAGE_IDE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1709 | scc_s = "IDE"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1710 | else if (cc == PCI_CLASS_STORAGE_SATA) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1711 | scc_s = "SATA"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1712 | else if (cc == PCI_CLASS_STORAGE_RAID) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1713 | scc_s = "RAID"; |
| 1714 | else |
| 1715 | scc_s = "unknown"; |
| 1716 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1717 | dev_printk(KERN_INFO, &pdev->dev, |
| 1718 | "AHCI %02x%02x.%02x%02x " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1719 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
| 1720 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1721 | |
| 1722 | (vers >> 24) & 0xff, |
| 1723 | (vers >> 16) & 0xff, |
| 1724 | (vers >> 8) & 0xff, |
| 1725 | vers & 0xff, |
| 1726 | |
| 1727 | ((cap >> 8) & 0x1f) + 1, |
| 1728 | (cap & 0x1f) + 1, |
| 1729 | speed_s, |
| 1730 | impl, |
| 1731 | scc_s); |
| 1732 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1733 | dev_printk(KERN_INFO, &pdev->dev, |
| 1734 | "flags: " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1735 | "%s%s%s%s%s%s" |
| 1736 | "%s%s%s%s%s%s%s\n" |
| 1737 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1738 | |
| 1739 | cap & (1 << 31) ? "64bit " : "", |
| 1740 | cap & (1 << 30) ? "ncq " : "", |
| 1741 | cap & (1 << 28) ? "ilck " : "", |
| 1742 | cap & (1 << 27) ? "stag " : "", |
| 1743 | cap & (1 << 26) ? "pm " : "", |
| 1744 | cap & (1 << 25) ? "led " : "", |
| 1745 | |
| 1746 | cap & (1 << 24) ? "clo " : "", |
| 1747 | cap & (1 << 19) ? "nz " : "", |
| 1748 | cap & (1 << 18) ? "only " : "", |
| 1749 | cap & (1 << 17) ? "pmp " : "", |
| 1750 | cap & (1 << 15) ? "pio " : "", |
| 1751 | cap & (1 << 14) ? "slum " : "", |
| 1752 | cap & (1 << 13) ? "part " : "" |
| 1753 | ); |
| 1754 | } |
| 1755 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1756 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1757 | { |
| 1758 | static int printed_version; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1759 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
| 1760 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1761 | struct device *dev = &pdev->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1762 | struct ahci_host_priv *hpriv; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1763 | struct ata_host *host; |
| 1764 | int i, rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1765 | |
| 1766 | VPRINTK("ENTER\n"); |
| 1767 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1768 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
| 1769 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1770 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1771 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1772 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1773 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1774 | rc = pcim_enable_device(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1775 | if (rc) |
| 1776 | return rc; |
| 1777 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1778 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
| 1779 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1780 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1781 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1782 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1783 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 1784 | if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev)) |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1785 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1786 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1787 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
| 1788 | if (!hpriv) |
| 1789 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1790 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1791 | /* save initial config */ |
| 1792 | ahci_save_initial_config(pdev, &pi, hpriv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1793 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1794 | /* prepare host */ |
| 1795 | if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ)) |
| 1796 | pi.flags |= ATA_FLAG_NCQ; |
| 1797 | |
| 1798 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
| 1799 | if (!host) |
| 1800 | return -ENOMEM; |
| 1801 | host->iomap = pcim_iomap_table(pdev); |
| 1802 | host->private_data = hpriv; |
| 1803 | |
| 1804 | for (i = 0; i < host->n_ports; i++) { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 1805 | struct ata_port *ap = host->ports[i]; |
| 1806 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1807 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 1808 | /* standard SATA port setup */ |
| 1809 | if (hpriv->port_map & (1 << i)) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1810 | ap->ioaddr.cmd_addr = port_mmio; |
| 1811 | ap->ioaddr.scr_addr = port_mmio + PORT_SCR; |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 1812 | } |
| 1813 | |
| 1814 | /* disabled/not-implemented port */ |
| 1815 | else |
| 1816 | ap->ops = &ata_dummy_port_ops; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1817 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1818 | |
| 1819 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1820 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1821 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1822 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1823 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1824 | rc = ahci_reset_controller(host); |
| 1825 | if (rc) |
| 1826 | return rc; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1827 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1828 | ahci_init_controller(host); |
| 1829 | ahci_print_info(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1830 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1831 | pci_set_master(pdev); |
| 1832 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, |
| 1833 | &ahci_sht); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1834 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1835 | |
| 1836 | static int __init ahci_init(void) |
| 1837 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 1838 | return pci_register_driver(&ahci_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1839 | } |
| 1840 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1841 | static void __exit ahci_exit(void) |
| 1842 | { |
| 1843 | pci_unregister_driver(&ahci_pci_driver); |
| 1844 | } |
| 1845 | |
| 1846 | |
| 1847 | MODULE_AUTHOR("Jeff Garzik"); |
| 1848 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); |
| 1849 | MODULE_LICENSE("GPL"); |
| 1850 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
Jeff Garzik | 6885433 | 2005-08-23 02:53:51 -0400 | [diff] [blame] | 1851 | MODULE_VERSION(DRV_VERSION); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1852 | |
| 1853 | module_init(ahci_init); |
| 1854 | module_exit(ahci_exit); |