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Rohit Vaswani3fc60342012-04-23 18:55:15 -07001/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Rohit Vaswani3fc60342012-04-23 18:55:15 -070013/include/ "skeleton.dtsi"
Mitchel Humpherysb3f40d12012-10-05 16:26:58 -070014/include/ "msm9625-ion.dtsi"
Rohit Vaswani3fc60342012-04-23 18:55:15 -070015
16/ {
17 model = "Qualcomm MSM 9625";
18 compatible = "qcom,msm9625";
19 interrupt-parent = <&intc>;
20
21 intc: interrupt-controller@F9000000 {
22 compatible = "qcom,msm-qgic2";
23 interrupt-controller;
24 #interrupt-cells = <3>;
25 reg = <0xF9000000 0x1000>,
26 <0xF9002000 0x1000>;
27 };
28
Abhimanyu Kapur490d20c2012-06-22 17:34:20 -070029 l2: cache-controller@f9040000 {
30 compatible = "arm,pl310-cache";
31 reg = <0xf9040000 0x1000>;
32 arm,data-latency = <1 1 1>;
33 arm,tag-latency = <1 1 1>;
34 cache-unified;
35 cache-level = <2>;
36 };
37
Rohit Vaswani3fc60342012-04-23 18:55:15 -070038 msmgpio: gpio@fd510000 {
39 compatible = "qcom,msm-gpio";
Rohit Vaswanib1cc4932012-07-23 21:30:11 -070040 gpio-controller;
41 #gpio-cells = <2>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070042 interrupt-controller;
43 #interrupt-cells = <2>;
44 reg = <0xfd510000 0x4000>;
45 };
46
Rohit Vaswania5129562012-06-12 20:11:23 -070047 timer: msm-qtimer@f9021000 {
Rohit Vaswani3fc60342012-04-23 18:55:15 -070048 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Rohit Vaswania5129562012-06-12 20:11:23 -070049 reg = <0xF9021000 0x1000>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070050 interrupts = <0 7 0>;
Rohit Vaswania5129562012-06-12 20:11:23 -070051 irq-is-not-percpu;
Abhimanyu Kapuraf4c4d52012-10-01 14:15:10 -070052 clock-frequency = <19200000>;
Rohit Vaswani3fc60342012-04-23 18:55:15 -070053 };
Jin Hong8d328582012-05-01 15:45:29 -070054
Yan He3cb97ba2012-05-13 16:45:24 -070055 qcom,sps@f9980000 {
56 compatible = "qcom,msm_sps";
57 reg = <0xf9984000 0x15000>,
58 <0xf9999000 0xb000>,
Yan He6f9ae712012-09-20 12:55:47 -070059 <0xfe803000 0x4800>;
Yan He3cb97ba2012-05-13 16:45:24 -070060 interrupts = <0 94 0>;
61 qcom,device-type = <2>;
62 };
63
Jin Hong8d328582012-05-01 15:45:29 -070064 serial@f991f000 {
65 compatible = "qcom,msm-lsuart-v14";
66 reg = <0xf991f000 0x1000>;
67 interrupts = <0 109 0>;
68 };
Sahitya Tummala9ba4b282012-06-19 11:41:51 +053069
Jack Phama01e9c12012-09-25 21:37:03 -070070 usb@f9a55000 {
71 compatible = "qcom,hsusb-otg";
72 reg = <0xf9a55000 0x400>;
73 interrupts = <0 134 0 0 140 0>;
74 interrupt-names = "core_irq", "async_irq";
75 HSUSB_VDDCX-supply = <&pm8019_l12>;
76 HSUSB_1p8-supply = <&pm8019_l2>;
77 HSUSB_3p3-supply = <&pm8019_l4>;
78
79 qcom,hsusb-otg-phy-type = <2>;
80 qcom,hsusb-otg-mode = <1>;
81 qcom,hsusb-otg-otg-control = <1>;
82 qcom,hsusb-otg-disable-reset;
83 };
84
85 android_usb@fc42b0c8 {
86 compatible = "qcom,android-usb";
87 reg = <0xfc42b0c8 0xc8>;
88 };
89
Sahitya Tummala9ba4b282012-06-19 11:41:51 +053090 qcom,nand@f9ac0000 {
91 compatible = "qcom,msm-nand";
92 reg = <0xf9ac0000 0x1000>,
93 <0xf9ac4000 0x8000>;
94 reg-names = "nand_phys",
95 "bam_phys";
96 interrupts = <0 247 0>;
97 interrupt-names = "bam_irq";
98 };
Rohit Vaswani0045df42012-06-29 16:21:48 -070099
100 spi@f9928000 {
101 compatible = "qcom,spi-qup-v2";
102 reg = <0xf9928000 0x1000>;
103 interrupts = <0 100 0>;
104 spi-max-frequency = <24000000>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 gpios = <&msmgpio 23 0>, /* CLK */
108 <&msmgpio 21 0>, /* MISO */
109 <&msmgpio 20 0>; /* MOSI */
110
111 cs-gpios = <&msmgpio 69 0>;
112
113 ethernet-switch@0 {
114 compatible = "simtec,ks8851";
115 reg = <0>;
116 interrupt-parent = <&msmgpio>;
117 interrupts = <75 0>;
118 spi-max-frequency = <5000000>;
119 };
120 };
Hanumant Singh6c4bf062012-09-06 15:51:10 -0700121
122 qcom,wdt@f9017000 {
123 compatible = "qcom,msm-watchdog";
124 reg = <0xf9017000 0x1000>;
125 interrupts = <1 2 0>, <1 1 0>;
126 qcom,bark-time = <11000>;
127 qcom,pet-time = <10000>;
128 qcom,ipi-ping = <0>;
129 };
Kenneth Heitkec2642402012-09-18 18:56:47 -0600130
Girish Mahadevanc65a7112012-09-19 11:15:56 -0600131 rpm_bus: qcom,rpm-smd {
132 compatible = "qcom,rpm-smd";
133 rpm-channel-name = "rpm_requests";
134 rpm-channel-type = <15>; /* SMD_APPS_RPM */
135 };
136
Kenneth Heitkec2642402012-09-18 18:56:47 -0600137 spmi_bus: qcom,spmi@fc4c0000 {
138 cell-index = <0>;
139 compatible = "qcom,spmi-pmic-arb";
140 reg = <0xfc4cf000 0x1000>,
141 <0Xfc4cb000 0x1000>;
142 /* 190,ee0_krait_hlos_spmi_periph_irq */
143 /* 187,channel_0_krait_hlos_trans_done_irq */
144 interrupts = <0 190 0 0 187 0>;
David Collins830de472012-09-24 16:26:35 -0700145 qcom,not-wakeup;
Kenneth Heitkec2642402012-09-18 18:56:47 -0600146 qcom,pmic-arb-ee = <0>;
147 qcom,pmic-arb-channel = <0>;
148 qcom,pmic-arb-ppid-map = <0x02400000>, /* TEMP_ALARM */
149 <0x03100001>, /* VADC1_USR */
150 <0x06100002>, /* RTC_ALARM */
151 <0x06200003>, /* RTC_TIMER */
152 <0x0a000004>, /* MPP1 */
153 <0x0a100005>, /* MPP2 */
154 <0x0a200006>, /* MPP3 */
155 <0x0a300007>, /* MPP4 */
156 <0x0a400008>, /* MPP5 */
157 <0x0a500009>, /* MPP6 */
158 <0x0c20000a>, /* GPIO3 */
159 <0x0c30000b>, /* GPIO4 */
160 <0x0c50000c>, /* GPIO6 */
161 <0x0080000d>; /* PON */
162 };
Rohit Vaswani3fc60342012-04-23 18:55:15 -0700163};
David Collinsa2b73f22012-09-13 17:32:16 -0700164
David Collins722a6512012-09-14 11:09:18 -0700165/include/ "msm-pm8019-rpm-regulator.dtsi"
David Collinsa2b73f22012-09-13 17:32:16 -0700166/include/ "msm-pm8019.dtsi"
David Collins56b41122012-09-24 17:09:23 -0700167/include/ "msm9625-regulator.dtsi"