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gerrit-public.fairphone.software / kernel / msm / 9daaf31a8cc9c98751b7b71198307e47d5bf6a4d / . / arch / arm / boot / dts / imx51.dtsi
blob: 327ab8e3a4c8ad63473a7121f743a9aeeeca9943 [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame^]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
20 };
21
22 tzic: tz-interrupt-controller@e0000000 {
23 compatible = "fsl,imx51-tzic", "fsl,tzic";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 reg = <0xe0000000 0x4000>;
27 };
28
29 clocks {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 ckil {
34 compatible = "fsl,imx-ckil", "fixed-clock";
35 clock-frequency = <32768>;
36 };
37
38 ckih1 {
39 compatible = "fsl,imx-ckih1", "fixed-clock";
40 clock-frequency = <22579200>;
41 };
42
43 ckih2 {
44 compatible = "fsl,imx-ckih2", "fixed-clock";
45 clock-frequency = <0>;
46 };
47
48 osc {
49 compatible = "fsl,imx-osc", "fixed-clock";
50 clock-frequency = <24000000>;
51 };
52 };
53
54 soc {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "simple-bus";
58 interrupt-parent = <&tzic>;
59 ranges;
60
61 aips@70000000 { /* AIPS1 */
62 compatible = "fsl,aips-bus", "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x70000000 0x10000000>;
66 ranges;
67
68 spba@70000000 {
69 compatible = "fsl,spba-bus", "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x70000000 0x40000>;
73 ranges;
74
75 esdhc@70004000 { /* ESDHC1 */
76 compatible = "fsl,imx51-esdhc";
77 reg = <0x70004000 0x4000>;
78 interrupts = <1>;
79 status = "disabled";
80 };
81
82 esdhc@70008000 { /* ESDHC2 */
83 compatible = "fsl,imx51-esdhc";
84 reg = <0x70008000 0x4000>;
85 interrupts = <2>;
86 status = "disabled";
87 };
88
89 uart2: uart@7000c000 { /* UART3 */
90 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
91 reg = <0x7000c000 0x4000>;
92 interrupts = <33>;
93 status = "disabled";
94 };
95
96 ecspi@70010000 { /* ECSPI1 */
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "fsl,imx51-ecspi";
100 reg = <0x70010000 0x4000>;
101 interrupts = <36>;
102 status = "disabled";
103 };
104
105 esdhc@70020000 { /* ESDHC3 */
106 compatible = "fsl,imx51-esdhc";
107 reg = <0x70020000 0x4000>;
108 interrupts = <3>;
109 status = "disabled";
110 };
111
112 esdhc@70024000 { /* ESDHC4 */
113 compatible = "fsl,imx51-esdhc";
114 reg = <0x70024000 0x4000>;
115 interrupts = <4>;
116 status = "disabled";
117 };
118 };
119
120 gpio0: gpio@73f84000 { /* GPIO1 */
121 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
122 reg = <0x73f84000 0x4000>;
123 interrupts = <50 51>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 };
129
130 gpio1: gpio@73f88000 { /* GPIO2 */
131 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
132 reg = <0x73f88000 0x4000>;
133 interrupts = <52 53>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 interrupt-controller;
137 #interrupt-cells = <1>;
138 };
139
140 gpio2: gpio@73f8c000 { /* GPIO3 */
141 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
142 reg = <0x73f8c000 0x4000>;
143 interrupts = <54 55>;
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <1>;
148 };
149
150 gpio3: gpio@73f90000 { /* GPIO4 */
151 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
152 reg = <0x73f90000 0x4000>;
153 interrupts = <56 57>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
157 #interrupt-cells = <1>;
158 };
159
160 wdog@73f98000 { /* WDOG1 */
161 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
162 reg = <0x73f98000 0x4000>;
163 interrupts = <58>;
164 status = "disabled";
165 };
166
167 wdog@73f9c000 { /* WDOG2 */
168 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
169 reg = <0x73f9c000 0x4000>;
170 interrupts = <59>;
171 status = "disabled";
172 };
173
174 uart0: uart@73fbc000 {
175 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
176 reg = <0x73fbc000 0x4000>;
177 interrupts = <31>;
178 status = "disabled";
179 };
180
181 uart1: uart@73fc0000 {
182 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
183 reg = <0x73fc0000 0x4000>;
184 interrupts = <32>;
185 status = "disabled";
186 };
187 };
188
189 aips@80000000 { /* AIPS2 */
190 compatible = "fsl,aips-bus", "simple-bus";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 reg = <0x80000000 0x10000000>;
194 ranges;
195
196 ecspi@83fac000 { /* ECSPI2 */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx51-ecspi";
200 reg = <0x83fac000 0x4000>;
201 interrupts = <37>;
202 status = "disabled";
203 };
204
205 sdma@83fb0000 {
206 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
207 reg = <0x83fb0000 0x4000>;
208 interrupts = <6>;
209 };
210
211 cspi@83fc0000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
215 reg = <0x83fc0000 0x4000>;
216 interrupts = <38>;
217 status = "disabled";
218 };
219
220 i2c@83fc4000 { /* I2C2 */
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
224 reg = <0x83fc4000 0x4000>;
225 interrupts = <63>;
226 status = "disabled";
227 };
228
229 i2c@83fc8000 { /* I2C1 */
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
233 reg = <0x83fc8000 0x4000>;
234 interrupts = <62>;
235 status = "disabled";
236 };
237
238 fec@83fec000 {
239 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
240 reg = <0x83fec000 0x4000>;
241 interrupts = <87>;
242 status = "disabled";
243 };
244 };
245 };
246};