Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/spinlock.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/mfd/pm8xxx/core.h> |
| 21 | #include <linux/mfd/pm8xxx/misc.h> |
| 22 | |
| 23 | /* PON CTRL 1 register */ |
| 24 | #define REG_PM8058_PON_CTRL_1 0x01C |
| 25 | #define REG_PM8921_PON_CTRL_1 0x01C |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 26 | #define REG_PM8018_PON_CTRL_1 0x01C |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 27 | |
| 28 | #define PON_CTRL_1_PULL_UP_MASK 0xE0 |
| 29 | #define PON_CTRL_1_USB_PWR_EN 0x10 |
| 30 | |
| 31 | #define PON_CTRL_1_WD_EN_MASK 0x08 |
| 32 | #define PON_CTRL_1_WD_EN_RESET 0x08 |
| 33 | #define PON_CTRL_1_WD_EN_PWR_OFF 0x00 |
| 34 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame^] | 35 | /* Regulator master enable addresses */ |
| 36 | #define REG_PM8058_VREG_EN_MSM 0x018 |
| 37 | #define REG_PM8058_VREG_EN_GRP_5_4 0x1C8 |
| 38 | |
| 39 | /* Regulator control registers for shutdown/reset */ |
| 40 | #define REG_PM8058_S0_CTRL 0x004 |
| 41 | #define REG_PM8058_S1_CTRL 0x005 |
| 42 | #define REG_PM8058_S3_CTRL 0x111 |
| 43 | #define REG_PM8058_L21_CTRL 0x120 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 44 | #define REG_PM8058_L22_CTRL 0x121 |
| 45 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame^] | 46 | #define PM8058_REGULATOR_ENABLE_MASK 0x80 |
| 47 | #define PM8058_REGULATOR_ENABLE 0x80 |
| 48 | #define PM8058_REGULATOR_DISABLE 0x00 |
| 49 | #define PM8058_REGULATOR_PULL_DOWN_MASK 0x40 |
| 50 | #define PM8058_REGULATOR_PULL_DOWN_EN 0x40 |
| 51 | |
| 52 | /* Buck CTRL register */ |
| 53 | #define PM8058_SMPS_LEGACY_VREF_SEL 0x20 |
| 54 | #define PM8058_SMPS_LEGACY_VPROG_MASK 0x1F |
| 55 | #define PM8058_SMPS_ADVANCED_BAND_MASK 0xC0 |
| 56 | #define PM8058_SMPS_ADVANCED_BAND_SHIFT 6 |
| 57 | #define PM8058_SMPS_ADVANCED_VPROG_MASK 0x3F |
| 58 | |
| 59 | /* Buck TEST2 registers for shutdown/reset */ |
| 60 | #define REG_PM8058_S0_TEST2 0x084 |
| 61 | #define REG_PM8058_S1_TEST2 0x085 |
| 62 | #define REG_PM8058_S3_TEST2 0x11A |
| 63 | |
| 64 | #define PM8058_REGULATOR_BANK_WRITE 0x80 |
| 65 | #define PM8058_REGULATOR_BANK_MASK 0x70 |
| 66 | #define PM8058_REGULATOR_BANK_SHIFT 4 |
| 67 | #define PM8058_REGULATOR_BANK_SEL(n) ((n) << PM8058_REGULATOR_BANK_SHIFT) |
| 68 | |
| 69 | /* Buck TEST2 register bank 1 */ |
| 70 | #define PM8058_SMPS_LEGACY_VLOW_SEL 0x01 |
| 71 | |
| 72 | /* Buck TEST2 register bank 7 */ |
| 73 | #define PM8058_SMPS_ADVANCED_MODE_MASK 0x02 |
| 74 | #define PM8058_SMPS_ADVANCED_MODE 0x02 |
| 75 | #define PM8058_SMPS_LEGACY_MODE 0x00 |
| 76 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 77 | /* SLEEP CTRL register */ |
| 78 | #define REG_PM8058_SLEEP_CTRL 0x02B |
| 79 | #define REG_PM8921_SLEEP_CTRL 0x10A |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 80 | #define REG_PM8018_SLEEP_CTRL 0x10A |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 81 | |
| 82 | #define SLEEP_CTRL_SMPL_EN_MASK 0x04 |
| 83 | #define SLEEP_CTRL_SMPL_EN_RESET 0x04 |
| 84 | #define SLEEP_CTRL_SMPL_EN_PWR_OFF 0x00 |
| 85 | |
| 86 | /* FTS regulator PMR registers */ |
| 87 | #define REG_PM8901_REGULATOR_S1_PMR 0xA7 |
| 88 | #define REG_PM8901_REGULATOR_S2_PMR 0xA8 |
| 89 | #define REG_PM8901_REGULATOR_S3_PMR 0xA9 |
| 90 | #define REG_PM8901_REGULATOR_S4_PMR 0xAA |
| 91 | |
| 92 | #define PM8901_REGULATOR_PMR_STATE_MASK 0x60 |
| 93 | #define PM8901_REGULATOR_PMR_STATE_OFF 0x20 |
| 94 | |
Anirudh Ghayal | 5213eb8 | 2011-10-24 14:44:58 +0530 | [diff] [blame] | 95 | /* GPIO UART MUX CTRL registers */ |
| 96 | #define REG_PM8XXX_GPIO_MUX_CTRL 0x1CC |
| 97 | |
| 98 | #define UART_PATH_SEL_MASK 0x60 |
| 99 | #define UART_PATH_SEL_SHIFT 0x5 |
| 100 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 101 | struct pm8xxx_misc_chip { |
| 102 | struct list_head link; |
| 103 | struct pm8xxx_misc_platform_data pdata; |
| 104 | struct device *dev; |
| 105 | enum pm8xxx_version version; |
| 106 | }; |
| 107 | |
| 108 | static LIST_HEAD(pm8xxx_misc_chips); |
| 109 | static DEFINE_SPINLOCK(pm8xxx_misc_chips_lock); |
| 110 | |
| 111 | static int pm8xxx_misc_masked_write(struct pm8xxx_misc_chip *chip, u16 addr, |
| 112 | u8 mask, u8 val) |
| 113 | { |
| 114 | int rc; |
| 115 | u8 reg; |
| 116 | |
| 117 | rc = pm8xxx_readb(chip->dev->parent, addr, ®); |
| 118 | if (rc) { |
| 119 | pr_err("pm8xxx_readb(0x%03X) failed, rc=%d\n", addr, rc); |
| 120 | return rc; |
| 121 | } |
| 122 | reg &= ~mask; |
| 123 | reg |= val & mask; |
| 124 | rc = pm8xxx_writeb(chip->dev->parent, addr, reg); |
| 125 | if (rc) |
| 126 | pr_err("pm8xxx_writeb(0x%03X)=0x%02X failed, rc=%d\n", addr, |
| 127 | reg, rc); |
| 128 | return rc; |
| 129 | } |
| 130 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame^] | 131 | /* |
| 132 | * Set an SMPS regulator to be disabled in its CTRL register, but enabled |
| 133 | * in the master enable register. Also set it's pull down enable bit. |
| 134 | * Take care to make sure that the output voltage doesn't change if switching |
| 135 | * from advanced mode to legacy mode. |
| 136 | */ |
| 137 | static int |
| 138 | __pm8058_disable_smps_locally_set_pull_down(struct pm8xxx_misc_chip *chip, |
| 139 | u16 ctrl_addr, u16 test2_addr, u16 master_enable_addr, |
| 140 | u8 master_enable_bit) |
| 141 | { |
| 142 | int rc = 0; |
| 143 | u8 vref_sel, vlow_sel, band, vprog, bank, reg; |
| 144 | |
| 145 | bank = PM8058_REGULATOR_BANK_SEL(7); |
| 146 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 147 | if (rc) { |
| 148 | pr_err("%s: pm8xxx_writeb(0x%03X) failed: rc=%d\n", __func__, |
| 149 | test2_addr, rc); |
| 150 | goto done; |
| 151 | } |
| 152 | |
| 153 | rc = pm8xxx_readb(chip->dev->parent, test2_addr, ®); |
| 154 | if (rc) { |
| 155 | pr_err("%s: FAIL pm8xxx_readb(0x%03X): rc=%d\n", |
| 156 | __func__, test2_addr, rc); |
| 157 | goto done; |
| 158 | } |
| 159 | |
| 160 | /* Check if in advanced mode. */ |
| 161 | if ((reg & PM8058_SMPS_ADVANCED_MODE_MASK) == |
| 162 | PM8058_SMPS_ADVANCED_MODE) { |
| 163 | /* Determine current output voltage. */ |
| 164 | rc = pm8xxx_readb(chip->dev->parent, ctrl_addr, ®); |
| 165 | if (rc) { |
| 166 | pr_err("%s: FAIL pm8xxx_readb(0x%03X): rc=%d\n", |
| 167 | __func__, ctrl_addr, rc); |
| 168 | goto done; |
| 169 | } |
| 170 | |
| 171 | band = (reg & PM8058_SMPS_ADVANCED_BAND_MASK) |
| 172 | >> PM8058_SMPS_ADVANCED_BAND_SHIFT; |
| 173 | switch (band) { |
| 174 | case 3: |
| 175 | vref_sel = 0; |
| 176 | vlow_sel = 0; |
| 177 | break; |
| 178 | case 2: |
| 179 | vref_sel = PM8058_SMPS_LEGACY_VREF_SEL; |
| 180 | vlow_sel = 0; |
| 181 | break; |
| 182 | case 1: |
| 183 | vref_sel = PM8058_SMPS_LEGACY_VREF_SEL; |
| 184 | vlow_sel = PM8058_SMPS_LEGACY_VLOW_SEL; |
| 185 | break; |
| 186 | default: |
| 187 | pr_err("%s: regulator already disabled\n", __func__); |
| 188 | return -EPERM; |
| 189 | } |
| 190 | vprog = (reg & PM8058_SMPS_ADVANCED_VPROG_MASK); |
| 191 | /* Round up if fine step is in use. */ |
| 192 | vprog = (vprog + 1) >> 1; |
| 193 | if (vprog > PM8058_SMPS_LEGACY_VPROG_MASK) |
| 194 | vprog = PM8058_SMPS_LEGACY_VPROG_MASK; |
| 195 | |
| 196 | /* Set VLOW_SEL bit. */ |
| 197 | bank = PM8058_REGULATOR_BANK_SEL(1); |
| 198 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 199 | if (rc) { |
| 200 | pr_err("%s: FAIL pm8xxx_writeb(0x%03X): rc=%d\n", |
| 201 | __func__, test2_addr, rc); |
| 202 | goto done; |
| 203 | } |
| 204 | |
| 205 | rc = pm8xxx_misc_masked_write(chip, test2_addr, |
| 206 | PM8058_REGULATOR_BANK_WRITE | PM8058_REGULATOR_BANK_MASK |
| 207 | | PM8058_SMPS_LEGACY_VLOW_SEL, |
| 208 | PM8058_REGULATOR_BANK_WRITE | |
| 209 | PM8058_REGULATOR_BANK_SEL(1) | vlow_sel); |
| 210 | if (rc) |
| 211 | goto done; |
| 212 | |
| 213 | /* Switch to legacy mode */ |
| 214 | bank = PM8058_REGULATOR_BANK_SEL(7); |
| 215 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 216 | if (rc) { |
| 217 | pr_err("%s: FAIL pm8xxx_writeb(0x%03X): rc=%d\n", |
| 218 | __func__, test2_addr, rc); |
| 219 | goto done; |
| 220 | } |
| 221 | rc = pm8xxx_misc_masked_write(chip, test2_addr, |
| 222 | PM8058_REGULATOR_BANK_WRITE | |
| 223 | PM8058_REGULATOR_BANK_MASK | |
| 224 | PM8058_SMPS_ADVANCED_MODE_MASK, |
| 225 | PM8058_REGULATOR_BANK_WRITE | |
| 226 | PM8058_REGULATOR_BANK_SEL(7) | |
| 227 | PM8058_SMPS_LEGACY_MODE); |
| 228 | if (rc) |
| 229 | goto done; |
| 230 | |
| 231 | /* Enable locally, enable pull down, keep voltage the same. */ |
| 232 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 233 | PM8058_REGULATOR_ENABLE_MASK | |
| 234 | PM8058_REGULATOR_PULL_DOWN_MASK | |
| 235 | PM8058_SMPS_LEGACY_VREF_SEL | |
| 236 | PM8058_SMPS_LEGACY_VPROG_MASK, |
| 237 | PM8058_REGULATOR_ENABLE | PM8058_REGULATOR_PULL_DOWN_EN |
| 238 | | vref_sel | vprog); |
| 239 | if (rc) |
| 240 | goto done; |
| 241 | } |
| 242 | |
| 243 | /* Enable in master control register. */ |
| 244 | rc = pm8xxx_misc_masked_write(chip, master_enable_addr, |
| 245 | master_enable_bit, master_enable_bit); |
| 246 | if (rc) |
| 247 | goto done; |
| 248 | |
| 249 | /* Disable locally and enable pull down. */ |
| 250 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 251 | PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK, |
| 252 | PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN); |
| 253 | |
| 254 | done: |
| 255 | return rc; |
| 256 | } |
| 257 | |
| 258 | static int |
| 259 | __pm8058_disable_ldo_locally_set_pull_down(struct pm8xxx_misc_chip *chip, |
| 260 | u16 ctrl_addr, u16 master_enable_addr, u8 master_enable_bit) |
| 261 | { |
| 262 | int rc; |
| 263 | |
| 264 | /* Enable LDO in master control register. */ |
| 265 | rc = pm8xxx_misc_masked_write(chip, master_enable_addr, |
| 266 | master_enable_bit, master_enable_bit); |
| 267 | if (rc) |
| 268 | goto done; |
| 269 | |
| 270 | /* Disable LDO in CTRL register and set pull down */ |
| 271 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 272 | PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK, |
| 273 | PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN); |
| 274 | |
| 275 | done: |
| 276 | return rc; |
| 277 | } |
| 278 | |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 279 | static int __pm8018_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 280 | { |
| 281 | int rc; |
| 282 | |
| 283 | /* Enable SMPL if resetting is desired. */ |
| 284 | rc = pm8xxx_misc_masked_write(chip, REG_PM8018_SLEEP_CTRL, |
| 285 | SLEEP_CTRL_SMPL_EN_MASK, |
| 286 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 287 | if (rc) { |
| 288 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 289 | return rc; |
| 290 | } |
| 291 | |
| 292 | /* |
| 293 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 294 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 295 | * USB charging is enabled. |
| 296 | */ |
| 297 | rc = pm8xxx_misc_masked_write(chip, REG_PM8018_PON_CTRL_1, |
| 298 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 299 | | PON_CTRL_1_WD_EN_MASK, |
| 300 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 301 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 302 | if (rc) |
| 303 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 304 | |
| 305 | return rc; |
| 306 | } |
| 307 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 308 | static int __pm8058_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 309 | { |
| 310 | int rc; |
| 311 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame^] | 312 | /* When shutting down, enable active pulldowns on important rails. */ |
| 313 | if (!reset) { |
| 314 | /* Disable SMPS's 0,1,3 locally and set pulldown enable bits. */ |
| 315 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 316 | REG_PM8058_S0_CTRL, REG_PM8058_S0_TEST2, |
| 317 | REG_PM8058_VREG_EN_MSM, BIT(7)); |
| 318 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 319 | REG_PM8058_S1_CTRL, REG_PM8058_S1_TEST2, |
| 320 | REG_PM8058_VREG_EN_MSM, BIT(6)); |
| 321 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 322 | REG_PM8058_S3_CTRL, REG_PM8058_S3_TEST2, |
| 323 | REG_PM8058_VREG_EN_GRP_5_4, BIT(7) | BIT(4)); |
| 324 | /* Disable LDO 21 locally and set pulldown enable bit. */ |
| 325 | __pm8058_disable_ldo_locally_set_pull_down(chip, |
| 326 | REG_PM8058_L21_CTRL, REG_PM8058_VREG_EN_GRP_5_4, |
| 327 | BIT(1)); |
| 328 | } |
| 329 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 330 | /* |
| 331 | * Fix-up: Set regulator LDO22 to 1.225 V in high power mode. Leave its |
| 332 | * pull-down state intact. This ensures a safe shutdown. |
| 333 | */ |
| 334 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_L22_CTRL, 0xBF, 0x93); |
| 335 | if (rc) { |
| 336 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 337 | goto read_write_err; |
| 338 | } |
| 339 | |
| 340 | /* Enable SMPL if resetting is desired. */ |
| 341 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_SLEEP_CTRL, |
| 342 | SLEEP_CTRL_SMPL_EN_MASK, |
| 343 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 344 | if (rc) { |
| 345 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 346 | goto read_write_err; |
| 347 | } |
| 348 | |
| 349 | /* |
| 350 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 351 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 352 | * USB charging is enabled. |
| 353 | */ |
| 354 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_PON_CTRL_1, |
| 355 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 356 | | PON_CTRL_1_WD_EN_MASK, |
| 357 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 358 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 359 | if (rc) { |
| 360 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 361 | goto read_write_err; |
| 362 | } |
| 363 | |
| 364 | read_write_err: |
| 365 | return rc; |
| 366 | } |
| 367 | |
| 368 | static int __pm8901_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 369 | { |
| 370 | int rc = 0, i; |
| 371 | u8 pmr_addr[4] = { |
| 372 | REG_PM8901_REGULATOR_S2_PMR, |
| 373 | REG_PM8901_REGULATOR_S3_PMR, |
| 374 | REG_PM8901_REGULATOR_S4_PMR, |
| 375 | REG_PM8901_REGULATOR_S1_PMR, |
| 376 | }; |
| 377 | |
| 378 | /* Fix-up: Turn off regulators S1, S2, S3, S4 when shutting down. */ |
| 379 | if (!reset) { |
| 380 | for (i = 0; i < 4; i++) { |
| 381 | rc = pm8xxx_misc_masked_write(chip, pmr_addr[i], |
| 382 | PM8901_REGULATOR_PMR_STATE_MASK, |
| 383 | PM8901_REGULATOR_PMR_STATE_OFF); |
| 384 | if (rc) { |
| 385 | pr_err("pm8xxx_misc_masked_write failed, " |
| 386 | "rc=%d\n", rc); |
| 387 | goto read_write_err; |
| 388 | } |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | read_write_err: |
| 393 | return rc; |
| 394 | } |
| 395 | |
| 396 | static int __pm8921_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 397 | { |
| 398 | int rc; |
| 399 | |
| 400 | /* Enable SMPL if resetting is desired. */ |
| 401 | rc = pm8xxx_misc_masked_write(chip, REG_PM8921_SLEEP_CTRL, |
| 402 | SLEEP_CTRL_SMPL_EN_MASK, |
| 403 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 404 | if (rc) { |
| 405 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 406 | goto read_write_err; |
| 407 | } |
| 408 | |
| 409 | /* |
| 410 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 411 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 412 | * USB charging is enabled. |
| 413 | */ |
| 414 | rc = pm8xxx_misc_masked_write(chip, REG_PM8921_PON_CTRL_1, |
| 415 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 416 | | PON_CTRL_1_WD_EN_MASK, |
| 417 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 418 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 419 | if (rc) { |
| 420 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 421 | goto read_write_err; |
| 422 | } |
| 423 | |
| 424 | read_write_err: |
| 425 | return rc; |
| 426 | } |
| 427 | |
| 428 | /** |
| 429 | * pm8xxx_reset_pwr_off - switch all PM8XXX PMIC chips attached to the system to |
| 430 | * either reset or shutdown when they are turned off |
| 431 | * @reset: 0 = shudown the PMICs, 1 = shutdown and then restart the PMICs |
| 432 | * |
| 433 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 434 | */ |
| 435 | int pm8xxx_reset_pwr_off(int reset) |
| 436 | { |
| 437 | struct pm8xxx_misc_chip *chip; |
| 438 | unsigned long flags; |
| 439 | int rc = 0; |
| 440 | |
| 441 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 442 | |
| 443 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 444 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 445 | switch (chip->version) { |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 446 | case PM8XXX_VERSION_8018: |
| 447 | rc = __pm8018_reset_pwr_off(chip, reset); |
| 448 | break; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 449 | case PM8XXX_VERSION_8058: |
| 450 | rc = __pm8058_reset_pwr_off(chip, reset); |
| 451 | break; |
| 452 | case PM8XXX_VERSION_8901: |
| 453 | rc = __pm8901_reset_pwr_off(chip, reset); |
| 454 | break; |
| 455 | case PM8XXX_VERSION_8921: |
| 456 | rc = __pm8921_reset_pwr_off(chip, reset); |
| 457 | break; |
| 458 | default: |
| 459 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 460 | break; |
| 461 | } |
| 462 | if (rc) { |
| 463 | pr_err("reset_pwr_off failed, rc=%d\n", rc); |
| 464 | break; |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 469 | |
| 470 | return rc; |
| 471 | } |
| 472 | EXPORT_SYMBOL_GPL(pm8xxx_reset_pwr_off); |
| 473 | |
Anirudh Ghayal | 5213eb8 | 2011-10-24 14:44:58 +0530 | [diff] [blame] | 474 | /** |
| 475 | * pm8xxx_uart_gpio_mux_ctrl - Mux configuration to select the UART |
| 476 | * |
| 477 | * @uart_path_sel: Input argument to select either UART1/2/3 |
| 478 | * |
| 479 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 480 | */ |
| 481 | int pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel) |
| 482 | { |
| 483 | struct pm8xxx_misc_chip *chip; |
| 484 | unsigned long flags; |
| 485 | int rc = 0; |
| 486 | |
| 487 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 488 | |
| 489 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 490 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 491 | switch (chip->version) { |
| 492 | case PM8XXX_VERSION_8018: |
| 493 | case PM8XXX_VERSION_8058: |
| 494 | case PM8XXX_VERSION_8921: |
| 495 | rc = pm8xxx_misc_masked_write(chip, |
| 496 | REG_PM8XXX_GPIO_MUX_CTRL, UART_PATH_SEL_MASK, |
| 497 | uart_path_sel << UART_PATH_SEL_SHIFT); |
| 498 | break; |
| 499 | default: |
| 500 | /* Functionality not supported */ |
| 501 | break; |
| 502 | } |
| 503 | if (rc) { |
| 504 | pr_err("uart_gpio_mux_ctrl failed, rc=%d\n", rc); |
| 505 | break; |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 510 | |
| 511 | return rc; |
| 512 | } |
| 513 | EXPORT_SYMBOL(pm8xxx_uart_gpio_mux_ctrl); |
| 514 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 515 | static int __devinit pm8xxx_misc_probe(struct platform_device *pdev) |
| 516 | { |
| 517 | const struct pm8xxx_misc_platform_data *pdata = pdev->dev.platform_data; |
| 518 | struct pm8xxx_misc_chip *chip; |
| 519 | struct pm8xxx_misc_chip *sibling; |
| 520 | struct list_head *prev; |
| 521 | unsigned long flags; |
| 522 | int rc = 0; |
| 523 | |
| 524 | if (!pdata) { |
| 525 | pr_err("missing platform data\n"); |
| 526 | return -EINVAL; |
| 527 | } |
| 528 | |
| 529 | chip = kzalloc(sizeof(struct pm8xxx_misc_chip), GFP_KERNEL); |
| 530 | if (!chip) { |
| 531 | pr_err("Cannot allocate %d bytes\n", |
| 532 | sizeof(struct pm8xxx_misc_chip)); |
| 533 | return -ENOMEM; |
| 534 | } |
| 535 | |
| 536 | chip->dev = &pdev->dev; |
| 537 | chip->version = pm8xxx_get_version(chip->dev->parent); |
| 538 | memcpy(&(chip->pdata), pdata, sizeof(struct pm8xxx_misc_platform_data)); |
| 539 | |
| 540 | /* Insert PMICs in priority order (lowest value first). */ |
| 541 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 542 | prev = &pm8xxx_misc_chips; |
| 543 | list_for_each_entry(sibling, &pm8xxx_misc_chips, link) { |
| 544 | if (chip->pdata.priority < sibling->pdata.priority) |
| 545 | break; |
| 546 | else |
| 547 | prev = &sibling->link; |
| 548 | } |
| 549 | list_add(&chip->link, prev); |
| 550 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 551 | |
| 552 | platform_set_drvdata(pdev, chip); |
| 553 | |
| 554 | return rc; |
| 555 | } |
| 556 | |
| 557 | static int __devexit pm8xxx_misc_remove(struct platform_device *pdev) |
| 558 | { |
| 559 | struct pm8xxx_misc_chip *chip = platform_get_drvdata(pdev); |
| 560 | unsigned long flags; |
| 561 | |
| 562 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 563 | list_del(&chip->link); |
| 564 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 565 | |
| 566 | platform_set_drvdata(pdev, NULL); |
| 567 | kfree(chip); |
| 568 | |
| 569 | return 0; |
| 570 | } |
| 571 | |
| 572 | static struct platform_driver pm8xxx_misc_driver = { |
| 573 | .probe = pm8xxx_misc_probe, |
| 574 | .remove = __devexit_p(pm8xxx_misc_remove), |
| 575 | .driver = { |
| 576 | .name = PM8XXX_MISC_DEV_NAME, |
| 577 | .owner = THIS_MODULE, |
| 578 | }, |
| 579 | }; |
| 580 | |
| 581 | static int __init pm8xxx_misc_init(void) |
| 582 | { |
| 583 | return platform_driver_register(&pm8xxx_misc_driver); |
| 584 | } |
| 585 | postcore_initcall(pm8xxx_misc_init); |
| 586 | |
| 587 | static void __exit pm8xxx_misc_exit(void) |
| 588 | { |
| 589 | platform_driver_unregister(&pm8xxx_misc_driver); |
| 590 | } |
| 591 | module_exit(pm8xxx_misc_exit); |
| 592 | |
| 593 | MODULE_LICENSE("GPL v2"); |
| 594 | MODULE_DESCRIPTION("PMIC 8XXX misc driver"); |
| 595 | MODULE_VERSION("1.0"); |
| 596 | MODULE_ALIAS("platform:" PM8XXX_MISC_DEV_NAME); |