| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: timer.h,v 1.3 2000/05/09 17:40:15 davem Exp $ |
| 2 | * timer.h: System timer definitions for sun5. |
| 3 | * |
| 4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) |
| 5 | */ |
| 6 | |
| 7 | #ifndef _SPARC64_TIMER_H |
| 8 | #define _SPARC64_TIMER_H |
| 9 | |
| 10 | #include <linux/types.h> |
| 11 | |
| 12 | /* How timers work: |
| 13 | * |
| 14 | * On uniprocessors we just use counter zero for the system wide |
| 15 | * ticker, this performs thread scheduling, clock book keeping, |
| 16 | * and runs timer based events. Previously we used the Ultra |
| 17 | * %tick interrupt for this purpose. |
| 18 | * |
| 19 | * On multiprocessors we pick one cpu as the master level 10 tick |
| 20 | * processor. Here this counter zero tick handles clock book |
| 21 | * keeping and timer events only. Each Ultra has it's level |
| 22 | * 14 %tick interrupt set to fire off as well, even the master |
| 23 | * tick cpu runs this locally. This ticker performs thread |
| 24 | * scheduling, system/user tick counting for the current thread, |
| 25 | * and also profiling if enabled. |
| 26 | */ |
| 27 | |
| 28 | #include <linux/config.h> |
| 29 | |
| 30 | /* Two timers, traditionally steered to PIL's 10 and 14 respectively. |
| 31 | * But since INO packets are used on sun5, we could use any PIL level |
| 32 | * we like, however for now we use the normal ones. |
| 33 | * |
| 34 | * The 'reg' and 'interrupts' properties for these live in nodes named |
| 35 | * 'counter-timer'. The first of three 'reg' properties describe where |
| 36 | * the sun5_timer registers are. The other two I have no idea. (XXX) |
| 37 | */ |
| 38 | struct sun5_timer { |
| 39 | u64 count0; |
| 40 | u64 limit0; |
| 41 | u64 count1; |
| 42 | u64 limit1; |
| 43 | }; |
| 44 | |
| 45 | #define SUN5_LIMIT_ENABLE 0x80000000 |
| 46 | #define SUN5_LIMIT_TOZERO 0x40000000 |
| 47 | #define SUN5_LIMIT_ZRESTART 0x20000000 |
| 48 | #define SUN5_LIMIT_CMASK 0x1fffffff |
| 49 | |
| 50 | /* Given a HZ value, set the limit register to so that the timer IRQ |
| 51 | * gets delivered that often. |
| 52 | */ |
| 53 | #define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz)) |
| 54 | |
| 55 | struct sparc64_tick_ops { |
| 56 | void (*init_tick)(unsigned long); |
| 57 | unsigned long (*get_tick)(void); |
| 58 | unsigned long (*get_compare)(void); |
| 59 | unsigned long (*add_tick)(unsigned long, unsigned long); |
| 60 | unsigned long (*add_compare)(unsigned long); |
| 61 | unsigned long softint_mask; |
| 62 | }; |
| 63 | |
| 64 | extern struct sparc64_tick_ops *tick_ops; |
| 65 | |
| 66 | #ifdef CONFIG_SMP |
| 67 | extern unsigned long timer_tick_offset; |
| 68 | struct pt_regs; |
| 69 | extern void timer_tick_interrupt(struct pt_regs *); |
| 70 | #endif |
| 71 | |
| 72 | extern unsigned long sparc64_get_clock_tick(unsigned int cpu); |
| 73 | |
| 74 | #endif /* _SPARC64_TIMER_H */ |