| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> |
| Amit Kucheria | a003708 | 2009-12-03 22:36:41 +0200 | [diff] [blame^] | 3 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| Sascha Hauer | a244909 | 2008-12-18 11:51:57 +0100 | [diff] [blame] | 12 | #include <mach/hardware.h> |
| 13 | |
| Darius Augulis | 479c901 | 2008-09-09 11:29:41 +0200 | [diff] [blame] | 14 | #define AVIC_NIMASK 0x04 |
| 15 | |
| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 16 | @ this macro disables fast irq (not implemented) |
| 17 | .macro disable_fiq |
| 18 | .endm |
| 19 | |
| 20 | .macro get_irqnr_preamble, base, tmp |
| Amit Kucheria | a003708 | 2009-12-03 22:36:41 +0200 | [diff] [blame^] | 21 | #ifndef CONFIG_MXC_TZIC |
| Sascha Hauer | 12b8eb8 | 2009-05-25 10:50:52 +0200 | [diff] [blame] | 22 | ldr \base, =avic_base |
| 23 | ldr \base, [\base] |
| Darius Augulis | 479c901 | 2008-09-09 11:29:41 +0200 | [diff] [blame] | 24 | #ifdef CONFIG_MXC_IRQ_PRIOR |
| 25 | ldr r4, [\base, #AVIC_NIMASK] |
| 26 | #endif |
| Amit Kucheria | a003708 | 2009-12-03 22:36:41 +0200 | [diff] [blame^] | 27 | #elif defined CONFIG_MXC_TZIC |
| 28 | ldr \base, =tzic_base |
| 29 | ldr \base, [\base] |
| 30 | #endif /* CONFIG_MXC_TZIC */ |
| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 31 | .endm |
| 32 | |
| 33 | .macro arch_ret_to_user, tmp1, tmp2 |
| 34 | .endm |
| 35 | |
| 36 | @ this macro checks which interrupt occured |
| 37 | @ and returns its number in irqnr |
| 38 | @ and returns if an interrupt occured in irqstat |
| 39 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| Amit Kucheria | a003708 | 2009-12-03 22:36:41 +0200 | [diff] [blame^] | 40 | #ifndef CONFIG_MXC_TZIC |
| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 41 | @ Load offset & priority of the highest priority |
| 42 | @ interrupt pending from AVIC_NIVECSR |
| 43 | ldr \irqstat, [\base, #0x40] |
| 44 | @ Shift to get the decoded IRQ number, using ASR so |
| 45 | @ 'no interrupt pending' becomes 0xffffffff |
| 46 | mov \irqnr, \irqstat, asr #16 |
| 47 | @ set zero flag if IRQ + 1 == 0 |
| 48 | adds \tmp, \irqnr, #1 |
| Darius Augulis | 479c901 | 2008-09-09 11:29:41 +0200 | [diff] [blame] | 49 | #ifdef CONFIG_MXC_IRQ_PRIOR |
| 50 | bicne \tmp, \irqstat, #0xFFFFFFE0 |
| 51 | strne \tmp, [\base, #AVIC_NIMASK] |
| 52 | streq r4, [\base, #AVIC_NIMASK] |
| 53 | #endif |
| Amit Kucheria | a003708 | 2009-12-03 22:36:41 +0200 | [diff] [blame^] | 54 | #elif defined CONFIG_MXC_TZIC |
| 55 | @ Load offset & priority of the highest priority |
| 56 | @ interrupt pending. |
| 57 | @ 0xD80 is HIPND0 register |
| 58 | mov \irqnr, #0 |
| 59 | mov \irqstat, #0x0D80 |
| 60 | 1000: |
| 61 | ldr \tmp, [\irqstat, \base] |
| 62 | cmp \tmp, #0 |
| 63 | bne 1001f |
| 64 | addeq \irqnr, \irqnr, #32 |
| 65 | addeq \irqstat, \irqstat, #4 |
| 66 | cmp \irqnr, #128 |
| 67 | blo 1000b |
| 68 | b 2001f |
| 69 | 1001: mov \irqstat, #1 |
| 70 | 1002: tst \tmp, \irqstat |
| 71 | bne 2002f |
| 72 | movs \tmp, \tmp, lsr #1 |
| 73 | addne \irqnr, \irqnr, #1 |
| 74 | bne 1002b |
| 75 | 2001: |
| 76 | mov \irqnr, #0 |
| 77 | 2002: |
| 78 | movs \irqnr, \irqnr |
| 79 | #endif |
| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 80 | .endm |
| 81 | |
| 82 | @ irq priority table (not used) |
| 83 | .macro irq_prio_table |
| 84 | .endm |