Xiantao Zhang | a4f5003 | 2008-04-01 16:00:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * kvm_minstate.h: min save macros |
| 3 | * Copyright (c) 2007, Intel Corporation. |
| 4 | * |
| 5 | * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com) |
| 6 | * Xiantao Zhang (xiantao.zhang@intel.com) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms and conditions of the GNU General Public License, |
| 10 | * version 2, as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
| 19 | * Place - Suite 330, Boston, MA 02111-1307 USA. |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | |
| 24 | #include <asm/asmmacro.h> |
| 25 | #include <asm/types.h> |
| 26 | #include <asm/kregs.h> |
Xiantao Zhang | a917f7a | 2008-10-23 14:56:44 +0800 | [diff] [blame] | 27 | #include <asm/kvm_host.h> |
| 28 | |
Xiantao Zhang | a4f5003 | 2008-04-01 16:00:24 +0800 | [diff] [blame] | 29 | #include "asm-offsets.h" |
| 30 | |
| 31 | #define KVM_MINSTATE_START_SAVE_MIN \ |
| 32 | mov ar.rsc = 0;/* set enforced lazy mode, pl 0, little-endian, loadrs=0 */\ |
| 33 | ;; \ |
| 34 | mov.m r28 = ar.rnat; \ |
| 35 | addl r22 = VMM_RBS_OFFSET,r1; /* compute base of RBS */ \ |
| 36 | ;; \ |
| 37 | lfetch.fault.excl.nt1 [r22]; \ |
Xiantao Zhang | a917f7a | 2008-10-23 14:56:44 +0800 | [diff] [blame] | 38 | addl r1 = KVM_STK_OFFSET-VMM_PT_REGS_SIZE, r1; \ |
Xiantao Zhang | a4f5003 | 2008-04-01 16:00:24 +0800 | [diff] [blame] | 39 | mov r23 = ar.bspstore; /* save ar.bspstore */ \ |
| 40 | ;; \ |
| 41 | mov ar.bspstore = r22; /* switch to kernel RBS */\ |
| 42 | ;; \ |
| 43 | mov r18 = ar.bsp; \ |
| 44 | mov ar.rsc = 0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ |
| 45 | |
| 46 | |
| 47 | |
| 48 | #define KVM_MINSTATE_END_SAVE_MIN \ |
| 49 | bsw.1; /* switch back to bank 1 (must be last in insn group) */\ |
| 50 | ;; |
| 51 | |
| 52 | |
| 53 | #define PAL_VSA_SYNC_READ \ |
| 54 | /* begin to call pal vps sync_read */ \ |
Xiantao Zhang | 81aec52 | 2008-09-12 20:23:11 +0800 | [diff] [blame] | 55 | {.mii; \ |
Xiantao Zhang | a4f5003 | 2008-04-01 16:00:24 +0800 | [diff] [blame] | 56 | add r25 = VMM_VPD_BASE_OFFSET, r21; \ |
Xiantao Zhang | a4f5003 | 2008-04-01 16:00:24 +0800 | [diff] [blame] | 57 | nop 0x0; \ |
Xiantao Zhang | 81aec52 | 2008-09-12 20:23:11 +0800 | [diff] [blame] | 58 | mov r24=ip; \ |
| 59 | ;; \ |
| 60 | } \ |
| 61 | {.mmb \ |
| 62 | add r24=0x20, r24; \ |
| 63 | ld8 r25 = [r25]; /* read vpd base */ \ |
| 64 | br.cond.sptk kvm_vps_sync_read; /*call the service*/ \ |
Xiantao Zhang | a4f5003 | 2008-04-01 16:00:24 +0800 | [diff] [blame] | 65 | ;; \ |
| 66 | }; \ |
Xiantao Zhang | a4f5003 | 2008-04-01 16:00:24 +0800 | [diff] [blame] | 67 | |
| 68 | |
| 69 | #define KVM_MINSTATE_GET_CURRENT(reg) mov reg=r21 |
| 70 | |
| 71 | /* |
| 72 | * KVM_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves |
| 73 | * the minimum state necessary that allows us to turn psr.ic back |
| 74 | * on. |
| 75 | * |
| 76 | * Assumed state upon entry: |
| 77 | * psr.ic: off |
| 78 | * r31: contains saved predicates (pr) |
| 79 | * |
| 80 | * Upon exit, the state is as follows: |
| 81 | * psr.ic: off |
| 82 | * r2 = points to &pt_regs.r16 |
| 83 | * r8 = contents of ar.ccv |
| 84 | * r9 = contents of ar.csd |
| 85 | * r10 = contents of ar.ssd |
| 86 | * r11 = FPSR_DEFAULT |
| 87 | * r12 = kernel sp (kernel virtual address) |
| 88 | * r13 = points to current task_struct (kernel virtual address) |
| 89 | * p15 = TRUE if psr.i is set in cr.ipsr |
| 90 | * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15: |
| 91 | * preserved |
| 92 | * |
| 93 | * Note that psr.ic is NOT turned on by this macro. This is so that |
| 94 | * we can pass interruption state as arguments to a handler. |
| 95 | */ |
| 96 | |
| 97 | |
| 98 | #define PT(f) (VMM_PT_REGS_##f##_OFFSET) |
| 99 | |
| 100 | #define KVM_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \ |
| 101 | KVM_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \ |
| 102 | mov r27 = ar.rsc; /* M */ \ |
| 103 | mov r20 = r1; /* A */ \ |
| 104 | mov r25 = ar.unat; /* M */ \ |
| 105 | mov r29 = cr.ipsr; /* M */ \ |
| 106 | mov r26 = ar.pfs; /* I */ \ |
| 107 | mov r18 = cr.isr; \ |
| 108 | COVER; /* B;; (or nothing) */ \ |
| 109 | ;; \ |
| 110 | tbit.z p0,p15 = r29,IA64_PSR_I_BIT; \ |
| 111 | mov r1 = r16; \ |
| 112 | /* mov r21=r16; */ \ |
| 113 | /* switch from user to kernel RBS: */ \ |
| 114 | ;; \ |
| 115 | invala; /* M */ \ |
| 116 | SAVE_IFS; \ |
| 117 | ;; \ |
| 118 | KVM_MINSTATE_START_SAVE_MIN \ |
| 119 | adds r17 = 2*L1_CACHE_BYTES,r1;/* cache-line size */ \ |
| 120 | adds r16 = PT(CR_IPSR),r1; \ |
| 121 | ;; \ |
| 122 | lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \ |
| 123 | st8 [r16] = r29; /* save cr.ipsr */ \ |
| 124 | ;; \ |
| 125 | lfetch.fault.excl.nt1 [r17]; \ |
| 126 | tbit.nz p15,p0 = r29,IA64_PSR_I_BIT; \ |
| 127 | mov r29 = b0 \ |
| 128 | ;; \ |
| 129 | adds r16 = PT(R8),r1; /* initialize first base pointer */\ |
| 130 | adds r17 = PT(R9),r1; /* initialize second base pointer */\ |
| 131 | ;; \ |
| 132 | .mem.offset 0,0; st8.spill [r16] = r8,16; \ |
| 133 | .mem.offset 8,0; st8.spill [r17] = r9,16; \ |
| 134 | ;; \ |
| 135 | .mem.offset 0,0; st8.spill [r16] = r10,24; \ |
| 136 | .mem.offset 8,0; st8.spill [r17] = r11,24; \ |
| 137 | ;; \ |
| 138 | mov r9 = cr.iip; /* M */ \ |
| 139 | mov r10 = ar.fpsr; /* M */ \ |
| 140 | ;; \ |
| 141 | st8 [r16] = r9,16; /* save cr.iip */ \ |
| 142 | st8 [r17] = r30,16; /* save cr.ifs */ \ |
| 143 | sub r18 = r18,r22; /* r18=RSE.ndirty*8 */ \ |
| 144 | ;; \ |
| 145 | st8 [r16] = r25,16; /* save ar.unat */ \ |
| 146 | st8 [r17] = r26,16; /* save ar.pfs */ \ |
| 147 | shl r18 = r18,16; /* calu ar.rsc used for "loadrs" */\ |
| 148 | ;; \ |
| 149 | st8 [r16] = r27,16; /* save ar.rsc */ \ |
| 150 | st8 [r17] = r28,16; /* save ar.rnat */ \ |
| 151 | ;; /* avoid RAW on r16 & r17 */ \ |
| 152 | st8 [r16] = r23,16; /* save ar.bspstore */ \ |
| 153 | st8 [r17] = r31,16; /* save predicates */ \ |
| 154 | ;; \ |
| 155 | st8 [r16] = r29,16; /* save b0 */ \ |
| 156 | st8 [r17] = r18,16; /* save ar.rsc value for "loadrs" */\ |
| 157 | ;; \ |
| 158 | .mem.offset 0,0; st8.spill [r16] = r20,16;/* save original r1 */ \ |
| 159 | .mem.offset 8,0; st8.spill [r17] = r12,16; \ |
| 160 | adds r12 = -16,r1; /* switch to kernel memory stack */ \ |
| 161 | ;; \ |
| 162 | .mem.offset 0,0; st8.spill [r16] = r13,16; \ |
| 163 | .mem.offset 8,0; st8.spill [r17] = r10,16; /* save ar.fpsr */\ |
| 164 | mov r13 = r21; /* establish `current' */ \ |
| 165 | ;; \ |
| 166 | .mem.offset 0,0; st8.spill [r16] = r15,16; \ |
| 167 | .mem.offset 8,0; st8.spill [r17] = r14,16; \ |
| 168 | ;; \ |
| 169 | .mem.offset 0,0; st8.spill [r16] = r2,16; \ |
| 170 | .mem.offset 8,0; st8.spill [r17] = r3,16; \ |
| 171 | adds r2 = VMM_PT_REGS_R16_OFFSET,r1; \ |
| 172 | ;; \ |
| 173 | adds r16 = VMM_VCPU_IIPA_OFFSET,r13; \ |
| 174 | adds r17 = VMM_VCPU_ISR_OFFSET,r13; \ |
| 175 | mov r26 = cr.iipa; \ |
| 176 | mov r27 = cr.isr; \ |
| 177 | ;; \ |
| 178 | st8 [r16] = r26; \ |
| 179 | st8 [r17] = r27; \ |
| 180 | ;; \ |
| 181 | EXTRA; \ |
| 182 | mov r8 = ar.ccv; \ |
| 183 | mov r9 = ar.csd; \ |
| 184 | mov r10 = ar.ssd; \ |
| 185 | movl r11 = FPSR_DEFAULT; /* L-unit */ \ |
| 186 | adds r17 = VMM_VCPU_GP_OFFSET,r13; \ |
| 187 | ;; \ |
| 188 | ld8 r1 = [r17];/* establish kernel global pointer */ \ |
| 189 | ;; \ |
| 190 | PAL_VSA_SYNC_READ \ |
| 191 | KVM_MINSTATE_END_SAVE_MIN |
| 192 | |
| 193 | /* |
| 194 | * SAVE_REST saves the remainder of pt_regs (with psr.ic on). |
| 195 | * |
| 196 | * Assumed state upon entry: |
| 197 | * psr.ic: on |
| 198 | * r2: points to &pt_regs.f6 |
| 199 | * r3: points to &pt_regs.f7 |
| 200 | * r8: contents of ar.ccv |
| 201 | * r9: contents of ar.csd |
| 202 | * r10: contents of ar.ssd |
| 203 | * r11: FPSR_DEFAULT |
| 204 | * |
| 205 | * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST. |
| 206 | */ |
| 207 | #define KVM_SAVE_REST \ |
| 208 | .mem.offset 0,0; st8.spill [r2] = r16,16; \ |
| 209 | .mem.offset 8,0; st8.spill [r3] = r17,16; \ |
| 210 | ;; \ |
| 211 | .mem.offset 0,0; st8.spill [r2] = r18,16; \ |
| 212 | .mem.offset 8,0; st8.spill [r3] = r19,16; \ |
| 213 | ;; \ |
| 214 | .mem.offset 0,0; st8.spill [r2] = r20,16; \ |
| 215 | .mem.offset 8,0; st8.spill [r3] = r21,16; \ |
| 216 | mov r18=b6; \ |
| 217 | ;; \ |
| 218 | .mem.offset 0,0; st8.spill [r2] = r22,16; \ |
| 219 | .mem.offset 8,0; st8.spill [r3] = r23,16; \ |
| 220 | mov r19 = b7; \ |
| 221 | ;; \ |
| 222 | .mem.offset 0,0; st8.spill [r2] = r24,16; \ |
| 223 | .mem.offset 8,0; st8.spill [r3] = r25,16; \ |
| 224 | ;; \ |
| 225 | .mem.offset 0,0; st8.spill [r2] = r26,16; \ |
| 226 | .mem.offset 8,0; st8.spill [r3] = r27,16; \ |
| 227 | ;; \ |
| 228 | .mem.offset 0,0; st8.spill [r2] = r28,16; \ |
| 229 | .mem.offset 8,0; st8.spill [r3] = r29,16; \ |
| 230 | ;; \ |
| 231 | .mem.offset 0,0; st8.spill [r2] = r30,16; \ |
| 232 | .mem.offset 8,0; st8.spill [r3] = r31,32; \ |
| 233 | ;; \ |
| 234 | mov ar.fpsr = r11; \ |
| 235 | st8 [r2] = r8,8; \ |
| 236 | adds r24 = PT(B6)-PT(F7),r3; \ |
| 237 | adds r25 = PT(B7)-PT(F7),r3; \ |
| 238 | ;; \ |
| 239 | st8 [r24] = r18,16; /* b6 */ \ |
| 240 | st8 [r25] = r19,16; /* b7 */ \ |
| 241 | adds r2 = PT(R4)-PT(F6),r2; \ |
| 242 | adds r3 = PT(R5)-PT(F7),r3; \ |
| 243 | ;; \ |
| 244 | st8 [r24] = r9; /* ar.csd */ \ |
| 245 | st8 [r25] = r10; /* ar.ssd */ \ |
| 246 | ;; \ |
| 247 | mov r18 = ar.unat; \ |
| 248 | adds r19 = PT(EML_UNAT)-PT(R4),r2; \ |
| 249 | ;; \ |
| 250 | st8 [r19] = r18; /* eml_unat */ \ |
| 251 | |
| 252 | |
| 253 | #define KVM_SAVE_EXTRA \ |
| 254 | .mem.offset 0,0; st8.spill [r2] = r4,16; \ |
| 255 | .mem.offset 8,0; st8.spill [r3] = r5,16; \ |
| 256 | ;; \ |
| 257 | .mem.offset 0,0; st8.spill [r2] = r6,16; \ |
| 258 | .mem.offset 8,0; st8.spill [r3] = r7; \ |
| 259 | ;; \ |
| 260 | mov r26 = ar.unat; \ |
| 261 | ;; \ |
| 262 | st8 [r2] = r26;/* eml_unat */ \ |
| 263 | |
| 264 | #define KVM_SAVE_MIN_WITH_COVER KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs,) |
| 265 | #define KVM_SAVE_MIN_WITH_COVER_R19 KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs, mov r15 = r19) |
| 266 | #define KVM_SAVE_MIN KVM_DO_SAVE_MIN( , mov r30 = r0, ) |