Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * arch/arm/mach-kirkwood/include/mach/kirkwood.h |
| 3 | * |
| 4 | * Generic definitions for Marvell Kirkwood SoC flavors: |
| 5 | * 88F6180, 88F6192 and 88F6281. |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public |
| 8 | * License version 2. This program is licensed "as is" without any |
| 9 | * warranty of any kind, whether express or implied. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __ASM_ARCH_KIRKWOOD_H |
| 13 | #define __ASM_ARCH_KIRKWOOD_H |
| 14 | |
| 15 | /* |
| 16 | * Marvell Kirkwood address maps. |
| 17 | * |
| 18 | * phys |
| 19 | * e0000000 PCIe Memory space |
| 20 | * f1000000 on-chip peripheral registers |
| 21 | * f2000000 PCIe I/O space |
| 22 | * f3000000 NAND controller address window |
| 23 | * |
| 24 | * virt phys size |
| 25 | * fee00000 f1000000 1M on-chip peripheral registers |
| 26 | * fef00000 f2000000 1M PCIe I/O space |
| 27 | */ |
| 28 | |
| 29 | #define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 |
| 30 | #define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K |
| 31 | * is the minimal window size |
| 32 | */ |
| 33 | |
| 34 | #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 |
| 35 | #define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 |
| 36 | #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 |
| 37 | #define KIRKWOOD_PCIE_IO_SIZE SZ_1M |
| 38 | |
| 39 | #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 |
| 40 | #define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 |
| 41 | #define KIRKWOOD_REGS_SIZE SZ_1M |
| 42 | |
| 43 | #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 |
| 44 | #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M |
| 45 | |
| 46 | /* |
| 47 | * MBUS bridge registers. |
| 48 | */ |
| 49 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) |
| 50 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) |
| 51 | #define CPU_RESET 0x00000002 |
| 52 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) |
| 53 | #define SOFT_RESET_OUT_EN 0x00000004 |
| 54 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) |
| 55 | #define SOFT_RESET 0x00000001 |
| 56 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) |
| 57 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) |
| 58 | #define BRIDGE_INT_TIMER0 0x0002 |
| 59 | #define BRIDGE_INT_TIMER1 0x0004 |
| 60 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 61 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) |
| 62 | #define IRQ_CAUSE_LOW_OFF 0x0000 |
| 63 | #define IRQ_MASK_LOW_OFF 0x0004 |
| 64 | #define IRQ_CAUSE_HIGH_OFF 0x0010 |
| 65 | #define IRQ_MASK_HIGH_OFF 0x0014 |
| 66 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) |
| 67 | #define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) |
| 68 | #define L2_WRITETHROUGH 0x00000010 |
| 69 | |
| 70 | /* |
| 71 | * Register Map |
| 72 | */ |
| 73 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) |
| 74 | #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) |
| 75 | |
| 76 | #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) |
| 77 | #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) |
| 78 | #define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) |
| 79 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) |
| 80 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) |
| 81 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) |
| 82 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 83 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) |
| 84 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) |
| 85 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) |
| 86 | |
| 87 | #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) |
| 88 | |
| 89 | #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) |
| 90 | |
| 91 | #define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) |
| 92 | #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) |
| 93 | |
| 94 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) |
| 95 | |
| 96 | |
| 97 | #define GPIO_MAX 50 |
| 98 | |
| 99 | |
| 100 | #endif |