| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * arch/arm/mach-mv78xx0/include/mach/mv78xx0.h |
| 3 | * |
| 4 | * Generic definitions for Marvell MV78xx0 SoC flavors: |
| 5 | * MV781x0 and MV782x0. |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public |
| 8 | * License version 2. This program is licensed "as is" without any |
| 9 | * warranty of any kind, whether express or implied. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __ASM_ARCH_MV78XX0_H |
| 13 | #define __ASM_ARCH_MV78XX0_H |
| 14 | |
| 15 | /* |
| 16 | * Marvell MV78xx0 address maps. |
| 17 | * |
| 18 | * phys |
| 19 | * c0000000 PCIe Memory space |
| 20 | * f0800000 PCIe #0 I/O space |
| 21 | * f0900000 PCIe #1 I/O space |
| 22 | * f0a00000 PCIe #2 I/O space |
| 23 | * f0b00000 PCIe #3 I/O space |
| 24 | * f0c00000 PCIe #4 I/O space |
| 25 | * f0d00000 PCIe #5 I/O space |
| 26 | * f0e00000 PCIe #6 I/O space |
| 27 | * f0f00000 PCIe #7 I/O space |
| 28 | * f1000000 on-chip peripheral registers |
| 29 | * |
| 30 | * virt phys size |
| 31 | * fe400000 f102x000 16K core-specific peripheral registers |
| 32 | * fe700000 f0800000 1M PCIe #0 I/O space |
| 33 | * fe800000 f0900000 1M PCIe #1 I/O space |
| 34 | * fe900000 f0a00000 1M PCIe #2 I/O space |
| 35 | * fea00000 f0b00000 1M PCIe #3 I/O space |
| 36 | * feb00000 f0c00000 1M PCIe #4 I/O space |
| 37 | * fec00000 f0d00000 1M PCIe #5 I/O space |
| 38 | * fed00000 f0e00000 1M PCIe #6 I/O space |
| 39 | * fee00000 f0f00000 1M PCIe #7 I/O space |
| 40 | * fef00000 f1000000 1M on-chip peripheral registers |
| 41 | */ |
| 42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 |
| 43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 |
| 44 | #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 |
| 45 | #define MV78XX0_CORE_REGS_SIZE SZ_16K |
| 46 | |
| 47 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) |
| 48 | #define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) |
| 49 | #define MV78XX0_PCIE_IO_SIZE SZ_1M |
| 50 | |
| 51 | #define MV78XX0_REGS_PHYS_BASE 0xf1000000 |
| 52 | #define MV78XX0_REGS_VIRT_BASE 0xfef00000 |
| 53 | #define MV78XX0_REGS_SIZE SZ_1M |
| 54 | |
| 55 | #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 |
| 56 | #define MV78XX0_PCIE_MEM_SIZE 0x30000000 |
| 57 | |
| 58 | /* |
| 59 | * Core-specific peripheral registers. |
| 60 | */ |
| 61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) |
| 62 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) |
| 63 | #define L2_WRITETHROUGH 0x00020000 |
| 64 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) |
| 65 | #define SOFT_RESET_OUT_EN 0x00000004 |
| 66 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) |
| 67 | #define SOFT_RESET 0x00000001 |
| 68 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) |
| 69 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) |
| 70 | #define BRIDGE_INT_TIMER0 0x0002 |
| 71 | #define BRIDGE_INT_TIMER1 0x0004 |
| 72 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 73 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) |
| 74 | #define IRQ_CAUSE_LOW_OFF 0x0004 |
| 75 | #define IRQ_CAUSE_HIGH_OFF 0x0008 |
| 76 | #define IRQ_MASK_LOW_OFF 0x0010 |
| 77 | #define IRQ_MASK_HIGH_OFF 0x0014 |
| 78 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) |
| 79 | |
| 80 | /* |
| 81 | * Register Map |
| 82 | */ |
| 83 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) |
| 84 | #define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) |
| 85 | #define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) |
| 86 | |
| 87 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) |
| 88 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) |
| 89 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) |
| 90 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) |
| 91 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 92 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) |
| 93 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) |
| 94 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) |
| 95 | #define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) |
| 96 | #define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) |
| 97 | #define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) |
| 98 | #define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) |
| 99 | |
| 100 | #define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) |
| 101 | #define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) |
| 102 | |
| 103 | #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) |
| 104 | #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) |
| 105 | #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) |
| 106 | #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) |
| 107 | |
| 108 | #define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) |
| 109 | #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) |
| 110 | #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) |
| 111 | |
| 112 | #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) |
| 113 | #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) |
| 114 | |
| 115 | #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) |
| 116 | #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) |
| 117 | #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) |
| 118 | #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) |
| 119 | |
| 120 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) |
| 121 | |
| 122 | |
| 123 | #define GPIO_MAX 32 |
| 124 | |
| 125 | |
| 126 | #endif |