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Vitaly Wool78818e42006-05-16 11:54:37 +01001/*
2 * arch/arm/mach-pnx4008/irq.c
3 *
4 * PNX4008 IRQ controller driver
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code received from Philips:
9 * Copyright (C) 2003 Philips Semiconductors
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/mm.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/device.h>
Vitaly Wool5904a7f2006-07-05 14:47:20 +010025#include <linux/irq.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010026#include <mach/hardware.h>
Vitaly Wool78818e42006-05-16 11:54:37 +010027#include <asm/io.h>
28#include <asm/setup.h>
Vitaly Wool78818e42006-05-16 11:54:37 +010029#include <asm/pgtable.h>
30#include <asm/page.h>
31#include <asm/system.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/irq.h>
34#include <asm/mach/map.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010035#include <mach/irq.h>
Vitaly Wool78818e42006-05-16 11:54:37 +010036
37static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
38
39static void pnx4008_mask_irq(unsigned int irq)
40{
41 __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
42}
43
44static void pnx4008_unmask_irq(unsigned int irq)
45{
46 __raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq)); /* unmask interrupt */
47}
48
49static void pnx4008_mask_ack_irq(unsigned int irq)
50{
51 __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
52 __raw_writel(INTC_BIT(irq), INTC_SR(irq)); /* clear interrupt status */
53}
54
55static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
56{
57 switch (type) {
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +010058 case IRQ_TYPE_EDGE_RISING:
Vitaly Wool78818e42006-05-16 11:54:37 +010059 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
60 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
Russell King10dd5ce2006-11-23 11:41:32 +000061 set_irq_handler(irq, handle_edge_irq);
Vitaly Wool78818e42006-05-16 11:54:37 +010062 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +010063 case IRQ_TYPE_EDGE_FALLING:
Vitaly Wool78818e42006-05-16 11:54:37 +010064 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
65 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
Russell King10dd5ce2006-11-23 11:41:32 +000066 set_irq_handler(irq, handle_edge_irq);
Vitaly Wool78818e42006-05-16 11:54:37 +010067 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +010068 case IRQ_TYPE_LEVEL_LOW:
Vitaly Wool78818e42006-05-16 11:54:37 +010069 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
70 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
Russell King10dd5ce2006-11-23 11:41:32 +000071 set_irq_handler(irq, handle_level_irq);
Vitaly Wool78818e42006-05-16 11:54:37 +010072 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +010073 case IRQ_TYPE_LEVEL_HIGH:
Vitaly Wool78818e42006-05-16 11:54:37 +010074 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
75 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
Russell King10dd5ce2006-11-23 11:41:32 +000076 set_irq_handler(irq, handle_level_irq);
Vitaly Wool78818e42006-05-16 11:54:37 +010077 break;
78
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +010079 /* IRQ_TYPE_EDGE_BOTH is not supported */
Vitaly Wool78818e42006-05-16 11:54:37 +010080 default:
81 printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
82 return -1;
83 }
84 return 0;
85}
86
Russell King10dd5ce2006-11-23 11:41:32 +000087static struct irq_chip pnx4008_irq_chip = {
Vitaly Wool78818e42006-05-16 11:54:37 +010088 .ack = pnx4008_mask_ack_irq,
89 .mask = pnx4008_mask_irq,
90 .unmask = pnx4008_unmask_irq,
91 .set_type = pnx4008_set_irq_type,
92};
93
94void __init pnx4008_init_irq(void)
95{
96 unsigned int i;
97
Vitaly Wool5904a7f2006-07-05 14:47:20 +010098 /* configure IRQ's */
99 for (i = 0; i < NR_IRQS; i++) {
100 set_irq_flags(i, IRQF_VALID);
101 set_irq_chip(i, &pnx4008_irq_chip);
102 pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
103 }
104
105 /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
Vitaly Wool78818e42006-05-16 11:54:37 +0100106 pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
107 pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
108 pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
109 pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
110
Vitaly Wool5904a7f2006-07-05 14:47:20 +0100111 /* mask all others */
Vitaly Wool78818e42006-05-16 11:54:37 +0100112 __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
113 (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
114 INTC_ER(MAIN_BASE_INT));
115 __raw_writel(0, INTC_ER(SIC1_BASE_INT));
116 __raw_writel(0, INTC_ER(SIC2_BASE_INT));
Vitaly Wool78818e42006-05-16 11:54:37 +0100117}
118