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Catalin Marinas4b172442007-02-14 19:20:28 +01001#ifndef __ASMARM_ARCH_SCU_H
2#define __ASMARM_ARCH_SCU_H
3
Catalin Marinasb7b0ba92008-04-18 22:43:08 +01004/*
5 * SCU registers
6 */
7#define SCU_CTRL 0x00
8#define SCU_CONFIG 0x04
9#define SCU_CPU_STATUS 0x08
10#define SCU_INVALIDATE 0x0c
11#define SCU_FPGA_REVISION 0x10
Catalin Marinas4b172442007-02-14 19:20:28 +010012
13#endif