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Russell Kinga09e64f2008-08-05 16:14:15 +01001/* arch/arm/mach-s3c2410/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef ___ASM_ARCH_REGS_IRQ_H
13#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
14
15/* interrupt controller */
16
17#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
18#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
19#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
20
21#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
22#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
23#define S3C2410_INTMSK S3C2410_IRQREG(0x008)
24#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
25#define S3C2410_INTPND S3C2410_IRQREG(0x010)
26#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
27#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
28#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
29
30/* mask: 0=enable, 1=disable
31 * 1 bit EINT, 4=EINT4, 23=EINT23
32 * EINT0,1,2,3 are not handled here.
33*/
34
35#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
36#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
37#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
38#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
39
40#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
41#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
42
43#endif /* ___ASM_ARCH_REGS_IRQ_H */