| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame^] | 1 | #ifndef __ASM_ARCH_CONTROL_H |
| 2 | #define __ASM_ARCH_CONTROL_H |
| 3 | |
| 4 | /* |
| 5 | * arch/arm/plat-omap/include/mach/control.h |
| 6 | * |
| 7 | * OMAP2/3 System Control Module definitions |
| 8 | * |
| 9 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 10 | * Copyright (C) 2007 Nokia Corporation |
| 11 | * |
| 12 | * Written by Paul Walmsley |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation. |
| 17 | */ |
| 18 | |
| 19 | #include <mach/io.h> |
| 20 | |
| 21 | #define OMAP242X_CTRL_REGADDR(reg) \ |
| 22 | (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
| 23 | #define OMAP243X_CTRL_REGADDR(reg) \ |
| 24 | (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
| 25 | #define OMAP343X_CTRL_REGADDR(reg) \ |
| 26 | (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
| 27 | |
| 28 | /* |
| 29 | * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for |
| 30 | * OMAP24XX and OMAP34XX. |
| 31 | */ |
| 32 | |
| 33 | /* Control submodule offsets */ |
| 34 | |
| 35 | #define OMAP2_CONTROL_INTERFACE 0x000 |
| 36 | #define OMAP2_CONTROL_PADCONFS 0x030 |
| 37 | #define OMAP2_CONTROL_GENERAL 0x270 |
| 38 | #define OMAP343X_CONTROL_MEM_WKUP 0x600 |
| 39 | #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 |
| 40 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 |
| 41 | |
| 42 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ |
| 43 | |
| 44 | #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) |
| 45 | |
| 46 | /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ |
| 47 | #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) |
| 48 | #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) |
| 49 | #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) |
| 50 | #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) |
| 51 | #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) |
| 52 | #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) |
| 53 | #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) |
| 54 | #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) |
| 55 | #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) |
| 56 | #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) |
| 57 | #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) |
| 58 | #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) |
| 59 | |
| 60 | /* 242x-only CONTROL_GENERAL register offsets */ |
| 61 | #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ |
| 62 | #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) |
| 63 | |
| 64 | /* 243x-only CONTROL_GENERAL register offsets */ |
| 65 | /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ |
| 66 | #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) |
| 67 | #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) |
| 68 | #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
| 69 | #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) |
| 70 | #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) |
| 71 | |
| 72 | /* 24xx-only CONTROL_GENERAL register offsets */ |
| 73 | #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) |
| 74 | #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) |
| 75 | #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) |
| 76 | #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) |
| 77 | #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) |
| 78 | #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) |
| 79 | #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) |
| 80 | #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) |
| 81 | #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) |
| 82 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) |
| 83 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) |
| 84 | #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) |
| 85 | #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) |
| 86 | #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) |
| 87 | #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) |
| 88 | #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) |
| 89 | #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) |
| 90 | #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) |
| 91 | #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) |
| 92 | #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) |
| 93 | #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) |
| 94 | #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) |
| 95 | #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) |
| 96 | #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) |
| 97 | #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) |
| 98 | #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) |
| 99 | #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) |
| 100 | #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) |
| 101 | #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) |
| 102 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) |
| 103 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) |
| 104 | |
| 105 | /* 34xx-only CONTROL_GENERAL register offsets */ |
| 106 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) |
| 107 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) |
| 108 | #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) |
| 109 | #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) |
| 110 | #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) |
| 111 | #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) |
| 112 | #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) |
| 113 | #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) |
| 114 | #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) |
| 115 | #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) |
| 116 | #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) |
| 117 | #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) |
| 118 | #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) |
| 119 | #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) |
| 120 | #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) |
| 121 | #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) |
| 122 | #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) |
| 123 | #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) |
| 124 | #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) |
| 125 | #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) |
| 126 | #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) |
| 127 | #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) |
| 128 | #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) |
| 129 | #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) |
| 130 | #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) |
| 131 | #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) |
| 132 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) |
| 133 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) |
| 134 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) |
| 135 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
| 136 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) |
| 137 | |
| 138 | /* |
| 139 | * REVISIT: This list of registers is not comprehensive - there are more |
| 140 | * that should be added. |
| 141 | */ |
| 142 | |
| 143 | /* |
| 144 | * Control module register bit defines - these should eventually go into |
| 145 | * their own regbits file. Some of these will be complicated, depending |
| 146 | * on the device type (general-purpose, emulator, test, secure, bad, other) |
| 147 | * and the security mode (secure, non-secure, don't care) |
| 148 | */ |
| 149 | /* CONTROL_DEVCONF0 bits */ |
| 150 | #define OMAP24XX_USBSTANDBYCTRL (1 << 15) |
| 151 | #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) |
| 152 | #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) |
| 153 | |
| 154 | /* CONTROL_DEVCONF1 bits */ |
| 155 | #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ |
| 156 | #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ |
| 157 | #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ |
| 158 | |
| 159 | /* CONTROL_STATUS bits */ |
| 160 | #define OMAP2_DEVICETYPE_MASK (0x7 << 8) |
| 161 | #define OMAP2_SYSBOOT_5_MASK (1 << 5) |
| 162 | #define OMAP2_SYSBOOT_4_MASK (1 << 4) |
| 163 | #define OMAP2_SYSBOOT_3_MASK (1 << 3) |
| 164 | #define OMAP2_SYSBOOT_2_MASK (1 << 2) |
| 165 | #define OMAP2_SYSBOOT_1_MASK (1 << 1) |
| 166 | #define OMAP2_SYSBOOT_0_MASK (1 << 0) |
| 167 | |
| 168 | #ifndef __ASSEMBLY__ |
| 169 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 170 | extern void __iomem *omap_ctrl_base_get(void); |
| 171 | extern u8 omap_ctrl_readb(u16 offset); |
| 172 | extern u16 omap_ctrl_readw(u16 offset); |
| 173 | extern u32 omap_ctrl_readl(u16 offset); |
| 174 | extern void omap_ctrl_writeb(u8 val, u16 offset); |
| 175 | extern void omap_ctrl_writew(u16 val, u16 offset); |
| 176 | extern void omap_ctrl_writel(u32 val, u16 offset); |
| 177 | #else |
| 178 | #define omap_ctrl_base_get() 0 |
| 179 | #define omap_ctrl_readb(x) 0 |
| 180 | #define omap_ctrl_readw(x) 0 |
| 181 | #define omap_ctrl_readl(x) 0 |
| 182 | #define omap_ctrl_writeb(x, y) WARN_ON(1) |
| 183 | #define omap_ctrl_writew(x, y) WARN_ON(1) |
| 184 | #define omap_ctrl_writel(x, y) WARN_ON(1) |
| 185 | #endif |
| 186 | #endif /* __ASSEMBLY__ */ |
| 187 | |
| 188 | #endif /* __ASM_ARCH_CONTROL_H */ |
| 189 | |