blob: 02f9320f3efcf25000393284e7823f9089d0b7f3 [file] [log] [blame]
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001/*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21
22#include <asm/io.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010023#include <mach/board.h>
24#include <mach/gpio.h>
25#include <mach/cpu.h>
David Brownellbb2d1c32007-02-20 13:58:19 -080026
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080027#include "atmel_spi.h"
28
29/*
30 * The core SPI transfer engine just talks to a register bank to set up
31 * DMA transfers; transfer queue progress is driven by IRQs. The clock
32 * framework provides the base clock, subdivided for each spi_device.
33 *
34 * Newer controllers, marked with "new_1" flag, have:
35 * - CR.LASTXFER
36 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
37 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
38 * - SPI_CSRx.CSAAT
39 * - SPI_CSRx.SBCR allows faster clocking
40 */
41struct atmel_spi {
42 spinlock_t lock;
43
44 void __iomem *regs;
45 int irq;
46 struct clk *clk;
47 struct platform_device *pdev;
48 unsigned new_1:1;
David Brownelldefbd3b2007-07-17 04:04:08 -070049 struct spi_device *stay;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080050
51 u8 stopping;
52 struct list_head queue;
53 struct spi_transfer *current_transfer;
Silvester Erdeg154443c2008-02-06 01:38:12 -080054 unsigned long current_remaining_bytes;
55 struct spi_transfer *next_transfer;
56 unsigned long next_remaining_bytes;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080057
58 void *buffer;
59 dma_addr_t buffer_dma;
60};
61
62#define BUFFER_SIZE PAGE_SIZE
63#define INVALID_DMA_ADDRESS 0xffffffff
64
65/*
66 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
67 * they assume that spi slave device state will not change on deselect, so
David Brownelldefbd3b2007-07-17 04:04:08 -070068 * that automagic deselection is OK. ("NPCSx rises if no data is to be
69 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
70 * controllers have CSAAT and friends.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080071 *
David Brownelldefbd3b2007-07-17 04:04:08 -070072 * Since the CSAAT functionality is a bit weird on newer controllers as
73 * well, we use GPIO to control nCSx pins on all controllers, updating
74 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
75 * support active-high chipselects despite the controller's belief that
76 * only active-low devices/systems exists.
77 *
78 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
79 * right when driven with GPIO. ("Mode Fault does not allow more than one
80 * Master on Chip Select 0.") No workaround exists for that ... so for
81 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
82 * and (c) will trigger that first erratum in some cases.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080083 */
84
David Brownelldefbd3b2007-07-17 04:04:08 -070085static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080086{
87 unsigned gpio = (unsigned) spi->controller_data;
88 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -070089 u32 mr;
Atsushi Nemotof6febcc2008-02-23 15:23:39 -080090 int i;
91 u32 csr;
92 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
93
94 /* Make sure clock polarity is correct */
95 for (i = 0; i < spi->master->num_chipselect; i++) {
96 csr = spi_readl(as, CSR0 + 4 * i);
97 if ((csr ^ cpol) & SPI_BIT(CPOL))
98 spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
99 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800100
David Brownelldefbd3b2007-07-17 04:04:08 -0700101 mr = spi_readl(as, MR);
102 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
103
104 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
105 gpio, active ? " (high)" : "",
106 mr);
107
108 if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
109 gpio_set_value(gpio, active);
110 spi_writel(as, MR, mr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800111}
112
David Brownelldefbd3b2007-07-17 04:04:08 -0700113static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800114{
115 unsigned gpio = (unsigned) spi->controller_data;
116 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700117 u32 mr;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800118
David Brownelldefbd3b2007-07-17 04:04:08 -0700119 /* only deactivate *this* device; sometimes transfers to
120 * another device may be active when this routine is called.
121 */
122 mr = spi_readl(as, MR);
123 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
124 mr = SPI_BFINS(PCS, 0xf, mr);
125 spi_writel(as, MR, mr);
126 }
127
128 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
129 gpio, active ? " (low)" : "",
130 mr);
131
132 if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
133 gpio_set_value(gpio, !active);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800134}
135
Silvester Erdeg154443c2008-02-06 01:38:12 -0800136static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
137 struct spi_transfer *xfer)
138{
139 return msg->transfers.prev == &xfer->transfer_list;
140}
141
142static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
143{
144 return xfer->delay_usecs == 0 && !xfer->cs_change;
145}
146
147static void atmel_spi_next_xfer_data(struct spi_master *master,
148 struct spi_transfer *xfer,
149 dma_addr_t *tx_dma,
150 dma_addr_t *rx_dma,
151 u32 *plen)
152{
153 struct atmel_spi *as = spi_master_get_devdata(master);
154 u32 len = *plen;
155
156 /* use scratch buffer only when rx or tx data is unspecified */
157 if (xfer->rx_buf)
158 *rx_dma = xfer->rx_dma + xfer->len - len;
159 else {
160 *rx_dma = as->buffer_dma;
161 if (len > BUFFER_SIZE)
162 len = BUFFER_SIZE;
163 }
164 if (xfer->tx_buf)
165 *tx_dma = xfer->tx_dma + xfer->len - len;
166 else {
167 *tx_dma = as->buffer_dma;
168 if (len > BUFFER_SIZE)
169 len = BUFFER_SIZE;
170 memset(as->buffer, 0, len);
171 dma_sync_single_for_device(&as->pdev->dev,
172 as->buffer_dma, len, DMA_TO_DEVICE);
173 }
174
175 *plen = len;
176}
177
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800178/*
179 * Submit next transfer for DMA.
180 * lock is held, spi irq is blocked
181 */
182static void atmel_spi_next_xfer(struct spi_master *master,
183 struct spi_message *msg)
184{
185 struct atmel_spi *as = spi_master_get_devdata(master);
186 struct spi_transfer *xfer;
Gerard Kamdc329442008-08-04 13:41:12 -0700187 u32 len, remaining;
188 u32 ieval;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800189 dma_addr_t tx_dma, rx_dma;
190
Silvester Erdeg154443c2008-02-06 01:38:12 -0800191 if (!as->current_transfer)
192 xfer = list_entry(msg->transfers.next,
193 struct spi_transfer, transfer_list);
194 else if (!as->next_transfer)
195 xfer = list_entry(as->current_transfer->transfer_list.next,
196 struct spi_transfer, transfer_list);
197 else
198 xfer = NULL;
199
200 if (xfer) {
Gerard Kamdc329442008-08-04 13:41:12 -0700201 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
202
Silvester Erdeg154443c2008-02-06 01:38:12 -0800203 len = xfer->len;
204 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
205 remaining = xfer->len - len;
206
207 spi_writel(as, RPR, rx_dma);
208 spi_writel(as, TPR, tx_dma);
209
210 if (msg->spi->bits_per_word > 8)
211 len >>= 1;
212 spi_writel(as, RCR, len);
213 spi_writel(as, TCR, len);
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800214
215 dev_dbg(&msg->spi->dev,
216 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
217 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
218 xfer->rx_buf, xfer->rx_dma);
Silvester Erdeg154443c2008-02-06 01:38:12 -0800219 } else {
220 xfer = as->next_transfer;
221 remaining = as->next_remaining_bytes;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800222 }
223
Silvester Erdeg154443c2008-02-06 01:38:12 -0800224 as->current_transfer = xfer;
225 as->current_remaining_bytes = remaining;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800226
Silvester Erdeg154443c2008-02-06 01:38:12 -0800227 if (remaining > 0)
228 len = remaining;
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800229 else if (!atmel_spi_xfer_is_last(msg, xfer)
230 && atmel_spi_xfer_can_be_chained(xfer)) {
Silvester Erdeg154443c2008-02-06 01:38:12 -0800231 xfer = list_entry(xfer->transfer_list.next,
232 struct spi_transfer, transfer_list);
233 len = xfer->len;
234 } else
235 xfer = NULL;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800236
Silvester Erdeg154443c2008-02-06 01:38:12 -0800237 as->next_transfer = xfer;
238
239 if (xfer) {
Gerard Kamdc329442008-08-04 13:41:12 -0700240 u32 total;
241
Silvester Erdeg154443c2008-02-06 01:38:12 -0800242 total = len;
243 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
244 as->next_remaining_bytes = total - len;
245
246 spi_writel(as, RNPR, rx_dma);
247 spi_writel(as, TNPR, tx_dma);
248
249 if (msg->spi->bits_per_word > 8)
250 len >>= 1;
251 spi_writel(as, RNCR, len);
252 spi_writel(as, TNCR, len);
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800253
254 dev_dbg(&msg->spi->dev,
255 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
256 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
257 xfer->rx_buf, xfer->rx_dma);
Gerard Kamdc329442008-08-04 13:41:12 -0700258 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
Silvester Erdeg154443c2008-02-06 01:38:12 -0800259 } else {
260 spi_writel(as, RNCR, 0);
261 spi_writel(as, TNCR, 0);
Gerard Kamdc329442008-08-04 13:41:12 -0700262 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800263 }
264
Silvester Erdeg154443c2008-02-06 01:38:12 -0800265 /* REVISIT: We're waiting for ENDRX before we start the next
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800266 * transfer because we need to handle some difficult timing
267 * issues otherwise. If we wait for ENDTX in one transfer and
268 * then starts waiting for ENDRX in the next, it's difficult
269 * to tell the difference between the ENDRX interrupt we're
270 * actually waiting for and the ENDRX interrupt of the
271 * previous transfer.
272 *
273 * It should be doable, though. Just not now...
274 */
Gerard Kamdc329442008-08-04 13:41:12 -0700275 spi_writel(as, IER, ieval);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800276 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
277}
278
279static void atmel_spi_next_message(struct spi_master *master)
280{
281 struct atmel_spi *as = spi_master_get_devdata(master);
282 struct spi_message *msg;
David Brownelldefbd3b2007-07-17 04:04:08 -0700283 struct spi_device *spi;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800284
285 BUG_ON(as->current_transfer);
286
287 msg = list_entry(as->queue.next, struct spi_message, queue);
David Brownelldefbd3b2007-07-17 04:04:08 -0700288 spi = msg->spi;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800289
Tony Jones49dce682007-10-16 01:27:48 -0700290 dev_dbg(master->dev.parent, "start message %p for %s\n",
David Brownelldefbd3b2007-07-17 04:04:08 -0700291 msg, spi->dev.bus_id);
292
293 /* select chip if it's not still active */
294 if (as->stay) {
295 if (as->stay != spi) {
296 cs_deactivate(as, as->stay);
297 cs_activate(as, spi);
298 }
299 as->stay = NULL;
300 } else
301 cs_activate(as, spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800302
303 atmel_spi_next_xfer(master, msg);
304}
305
David Brownell8da08592007-07-17 04:04:07 -0700306/*
307 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
308 * - The buffer is either valid for CPU access, else NULL
309 * - If the buffer is valid, so is its DMA addresss
310 *
311 * This driver manages the dma addresss unless message->is_dma_mapped.
312 */
313static int
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800314atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
315{
David Brownell8da08592007-07-17 04:04:07 -0700316 struct device *dev = &as->pdev->dev;
317
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800318 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
David Brownell8da08592007-07-17 04:04:07 -0700319 if (xfer->tx_buf) {
320 xfer->tx_dma = dma_map_single(dev,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800321 (void *) xfer->tx_buf, xfer->len,
322 DMA_TO_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700323 if (dma_mapping_error(dev, xfer->tx_dma))
David Brownell8da08592007-07-17 04:04:07 -0700324 return -ENOMEM;
325 }
326 if (xfer->rx_buf) {
327 xfer->rx_dma = dma_map_single(dev,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800328 xfer->rx_buf, xfer->len,
329 DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700330 if (dma_mapping_error(dev, xfer->rx_dma)) {
David Brownell8da08592007-07-17 04:04:07 -0700331 if (xfer->tx_buf)
332 dma_unmap_single(dev,
333 xfer->tx_dma, xfer->len,
334 DMA_TO_DEVICE);
335 return -ENOMEM;
336 }
337 }
338 return 0;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800339}
340
341static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
342 struct spi_transfer *xfer)
343{
344 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -0700345 dma_unmap_single(master->dev.parent, xfer->tx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800346 xfer->len, DMA_TO_DEVICE);
347 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -0700348 dma_unmap_single(master->dev.parent, xfer->rx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800349 xfer->len, DMA_FROM_DEVICE);
350}
351
352static void
353atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
David Brownelldefbd3b2007-07-17 04:04:08 -0700354 struct spi_message *msg, int status, int stay)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800355{
David Brownelldefbd3b2007-07-17 04:04:08 -0700356 if (!stay || status < 0)
357 cs_deactivate(as, msg->spi);
358 else
359 as->stay = msg->spi;
360
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800361 list_del(&msg->queue);
362 msg->status = status;
363
Tony Jones49dce682007-10-16 01:27:48 -0700364 dev_dbg(master->dev.parent,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800365 "xfer complete: %u bytes transferred\n",
366 msg->actual_length);
367
368 spin_unlock(&as->lock);
369 msg->complete(msg->context);
370 spin_lock(&as->lock);
371
372 as->current_transfer = NULL;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800373 as->next_transfer = NULL;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800374
375 /* continue if needed */
376 if (list_empty(&as->queue) || as->stopping)
377 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
378 else
379 atmel_spi_next_message(master);
380}
381
382static irqreturn_t
383atmel_spi_interrupt(int irq, void *dev_id)
384{
385 struct spi_master *master = dev_id;
386 struct atmel_spi *as = spi_master_get_devdata(master);
387 struct spi_message *msg;
388 struct spi_transfer *xfer;
389 u32 status, pending, imr;
390 int ret = IRQ_NONE;
391
392 spin_lock(&as->lock);
393
394 xfer = as->current_transfer;
395 msg = list_entry(as->queue.next, struct spi_message, queue);
396
397 imr = spi_readl(as, IMR);
398 status = spi_readl(as, SR);
399 pending = status & imr;
400
401 if (pending & SPI_BIT(OVRES)) {
402 int timeout;
403
404 ret = IRQ_HANDLED;
405
Gerard Kamdc329442008-08-04 13:41:12 -0700406 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800407 | SPI_BIT(OVRES)));
408
409 /*
410 * When we get an overrun, we disregard the current
411 * transfer. Data will not be copied back from any
412 * bounce buffer and msg->actual_len will not be
413 * updated with the last xfer.
414 *
415 * We will also not process any remaning transfers in
416 * the message.
417 *
418 * First, stop the transfer and unmap the DMA buffers.
419 */
420 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
421 if (!msg->is_dma_mapped)
422 atmel_spi_dma_unmap_xfer(master, xfer);
423
424 /* REVISIT: udelay in irq is unfriendly */
425 if (xfer->delay_usecs)
426 udelay(xfer->delay_usecs);
427
Gerard Kamdc329442008-08-04 13:41:12 -0700428 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800429 spi_readl(as, TCR), spi_readl(as, RCR));
430
431 /*
432 * Clean up DMA registers and make sure the data
433 * registers are empty.
434 */
435 spi_writel(as, RNCR, 0);
436 spi_writel(as, TNCR, 0);
437 spi_writel(as, RCR, 0);
438 spi_writel(as, TCR, 0);
439 for (timeout = 1000; timeout; timeout--)
440 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
441 break;
442 if (!timeout)
Tony Jones49dce682007-10-16 01:27:48 -0700443 dev_warn(master->dev.parent,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800444 "timeout waiting for TXEMPTY");
445 while (spi_readl(as, SR) & SPI_BIT(RDRF))
446 spi_readl(as, RDR);
447
448 /* Clear any overrun happening while cleaning up */
449 spi_readl(as, SR);
450
David Brownelldefbd3b2007-07-17 04:04:08 -0700451 atmel_spi_msg_done(master, as, msg, -EIO, 0);
Gerard Kamdc329442008-08-04 13:41:12 -0700452 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800453 ret = IRQ_HANDLED;
454
455 spi_writel(as, IDR, pending);
456
Silvester Erdeg154443c2008-02-06 01:38:12 -0800457 if (as->current_remaining_bytes == 0) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800458 msg->actual_length += xfer->len;
459
460 if (!msg->is_dma_mapped)
461 atmel_spi_dma_unmap_xfer(master, xfer);
462
463 /* REVISIT: udelay in irq is unfriendly */
464 if (xfer->delay_usecs)
465 udelay(xfer->delay_usecs);
466
Silvester Erdeg154443c2008-02-06 01:38:12 -0800467 if (atmel_spi_xfer_is_last(msg, xfer)) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800468 /* report completed message */
David Brownelldefbd3b2007-07-17 04:04:08 -0700469 atmel_spi_msg_done(master, as, msg, 0,
470 xfer->cs_change);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800471 } else {
472 if (xfer->cs_change) {
David Brownelldefbd3b2007-07-17 04:04:08 -0700473 cs_deactivate(as, msg->spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800474 udelay(1);
David Brownelldefbd3b2007-07-17 04:04:08 -0700475 cs_activate(as, msg->spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800476 }
477
478 /*
479 * Not done yet. Submit the next transfer.
480 *
481 * FIXME handle protocol options for xfer
482 */
483 atmel_spi_next_xfer(master, msg);
484 }
485 } else {
486 /*
487 * Keep going, we still have data to send in
488 * the current transfer.
489 */
490 atmel_spi_next_xfer(master, msg);
491 }
492 }
493
494 spin_unlock(&as->lock);
495
496 return ret;
497}
498
David Brownelldccd5732007-07-17 04:04:02 -0700499/* the spi->mode bits understood by this driver: */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800500#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
501
502static int atmel_spi_setup(struct spi_device *spi)
503{
504 struct atmel_spi *as;
505 u32 scbr, csr;
506 unsigned int bits = spi->bits_per_word;
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700507 unsigned long bus_hz;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800508 unsigned int npcs_pin;
509 int ret;
510
511 as = spi_master_get_devdata(spi->master);
512
513 if (as->stopping)
514 return -ESHUTDOWN;
515
516 if (spi->chip_select > spi->master->num_chipselect) {
517 dev_dbg(&spi->dev,
518 "setup: invalid chipselect %u (%u defined)\n",
519 spi->chip_select, spi->master->num_chipselect);
520 return -EINVAL;
521 }
522
523 if (bits == 0)
524 bits = 8;
525 if (bits < 8 || bits > 16) {
526 dev_dbg(&spi->dev,
527 "setup: invalid bits_per_word %u (8 to 16)\n",
528 bits);
529 return -EINVAL;
530 }
531
532 if (spi->mode & ~MODEBITS) {
533 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
534 spi->mode & ~MODEBITS);
535 return -EINVAL;
536 }
537
David Brownelldefbd3b2007-07-17 04:04:08 -0700538 /* see notes above re chipselect */
539 if (cpu_is_at91rm9200()
540 && spi->chip_select == 0
541 && (spi->mode & SPI_CS_HIGH)) {
542 dev_dbg(&spi->dev, "setup: can't be active-high\n");
543 return -EINVAL;
544 }
545
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700546 /*
547 * Pre-new_1 chips start out at half the peripheral
548 * bus speed.
549 */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800550 bus_hz = clk_get_rate(as->clk);
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700551 if (!as->new_1)
552 bus_hz /= 2;
553
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800554 if (spi->max_speed_hz) {
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700555 /*
556 * Calculate the lowest divider that satisfies the
557 * constraint, assuming div32/fdiv/mbz == 0.
558 */
559 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
560
561 /*
562 * If the resulting divider doesn't fit into the
563 * register bitfield, we can't satisfy the constraint.
564 */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800565 if (scbr >= (1 << SPI_SCBR_SIZE)) {
David Brownell8da08592007-07-17 04:04:07 -0700566 dev_dbg(&spi->dev,
567 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
568 spi->max_speed_hz, scbr, bus_hz/255);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800569 return -EINVAL;
570 }
571 } else
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700572 /* speed zero means "as slow as possible" */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800573 scbr = 0xff;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800574
575 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
576 if (spi->mode & SPI_CPOL)
577 csr |= SPI_BIT(CPOL);
578 if (!(spi->mode & SPI_CPHA))
579 csr |= SPI_BIT(NCPHA);
580
Haavard Skinnemoen1eed29d2008-02-06 01:38:11 -0800581 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
582 *
583 * DLYBCT would add delays between words, slowing down transfers.
584 * It could potentially be useful to cope with DMA bottlenecks, but
585 * in those cases it's probably best to just use a lower bitrate.
586 */
587 csr |= SPI_BF(DLYBS, 0);
588 csr |= SPI_BF(DLYBCT, 0);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800589
590 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
591 npcs_pin = (unsigned int)spi->controller_data;
592 if (!spi->controller_state) {
David Brownell65f97a52007-11-28 16:21:10 -0800593 ret = gpio_request(npcs_pin, spi->dev.bus_id);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800594 if (ret)
595 return ret;
596 spi->controller_state = (void *)npcs_pin;
David Brownell28735a72007-03-16 13:38:14 -0800597 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
David Brownelldefbd3b2007-07-17 04:04:08 -0700598 } else {
599 unsigned long flags;
600
601 spin_lock_irqsave(&as->lock, flags);
602 if (as->stay == spi)
603 as->stay = NULL;
604 cs_deactivate(as, spi);
605 spin_unlock_irqrestore(&as->lock, flags);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800606 }
607
608 dev_dbg(&spi->dev,
609 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700610 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800611
612 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
613
614 return 0;
615}
616
617static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
618{
619 struct atmel_spi *as;
620 struct spi_transfer *xfer;
621 unsigned long flags;
Tony Jones49dce682007-10-16 01:27:48 -0700622 struct device *controller = spi->master->dev.parent;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800623
624 as = spi_master_get_devdata(spi->master);
625
626 dev_dbg(controller, "new message %p submitted for %s\n",
627 msg, spi->dev.bus_id);
628
629 if (unlikely(list_empty(&msg->transfers)
630 || !spi->max_speed_hz))
631 return -EINVAL;
632
633 if (as->stopping)
634 return -ESHUTDOWN;
635
636 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Atsushi Nemoto06719812008-04-28 02:14:19 -0700637 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800638 dev_dbg(&spi->dev, "missing rx or tx buf\n");
639 return -EINVAL;
640 }
641
642 /* FIXME implement these protocol options!! */
643 if (xfer->bits_per_word || xfer->speed_hz) {
644 dev_dbg(&spi->dev, "no protocol options yet\n");
645 return -ENOPROTOOPT;
646 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800647
David Brownell8da08592007-07-17 04:04:07 -0700648 /*
649 * DMA map early, for performance (empties dcache ASAP) and
650 * better fault reporting. This is a DMA-only driver.
651 *
652 * NOTE that if dma_unmap_single() ever starts to do work on
653 * platforms supported by this driver, we would need to clean
654 * up mappings for previously-mapped transfers.
655 */
656 if (!msg->is_dma_mapped) {
657 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
658 return -ENOMEM;
659 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800660 }
661
David Brownelldefbd3b2007-07-17 04:04:08 -0700662#ifdef VERBOSE
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800663 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
664 dev_dbg(controller,
665 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
666 xfer, xfer->len,
667 xfer->tx_buf, xfer->tx_dma,
668 xfer->rx_buf, xfer->rx_dma);
669 }
David Brownelldefbd3b2007-07-17 04:04:08 -0700670#endif
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800671
672 msg->status = -EINPROGRESS;
673 msg->actual_length = 0;
674
675 spin_lock_irqsave(&as->lock, flags);
676 list_add_tail(&msg->queue, &as->queue);
677 if (!as->current_transfer)
678 atmel_spi_next_message(spi->master);
679 spin_unlock_irqrestore(&as->lock, flags);
680
681 return 0;
682}
683
David Brownellbb2d1c32007-02-20 13:58:19 -0800684static void atmel_spi_cleanup(struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800685{
David Brownelldefbd3b2007-07-17 04:04:08 -0700686 struct atmel_spi *as = spi_master_get_devdata(spi->master);
687 unsigned gpio = (unsigned) spi->controller_data;
688 unsigned long flags;
689
690 if (!spi->controller_state)
691 return;
692
693 spin_lock_irqsave(&as->lock, flags);
694 if (as->stay == spi) {
695 as->stay = NULL;
696 cs_deactivate(as, spi);
697 }
698 spin_unlock_irqrestore(&as->lock, flags);
699
700 gpio_free(gpio);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800701}
702
703/*-------------------------------------------------------------------------*/
704
705static int __init atmel_spi_probe(struct platform_device *pdev)
706{
707 struct resource *regs;
708 int irq;
709 struct clk *clk;
710 int ret;
711 struct spi_master *master;
712 struct atmel_spi *as;
713
714 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
715 if (!regs)
716 return -ENXIO;
717
718 irq = platform_get_irq(pdev, 0);
719 if (irq < 0)
720 return irq;
721
722 clk = clk_get(&pdev->dev, "spi_clk");
723 if (IS_ERR(clk))
724 return PTR_ERR(clk);
725
726 /* setup spi core then atmel-specific driver state */
727 ret = -ENOMEM;
728 master = spi_alloc_master(&pdev->dev, sizeof *as);
729 if (!master)
730 goto out_free;
731
732 master->bus_num = pdev->id;
733 master->num_chipselect = 4;
734 master->setup = atmel_spi_setup;
735 master->transfer = atmel_spi_transfer;
736 master->cleanup = atmel_spi_cleanup;
737 platform_set_drvdata(pdev, master);
738
739 as = spi_master_get_devdata(master);
740
David Brownell8da08592007-07-17 04:04:07 -0700741 /*
742 * Scratch buffer is used for throwaway rx and tx data.
743 * It's coherent to minimize dcache pollution.
744 */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800745 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
746 &as->buffer_dma, GFP_KERNEL);
747 if (!as->buffer)
748 goto out_free;
749
750 spin_lock_init(&as->lock);
751 INIT_LIST_HEAD(&as->queue);
752 as->pdev = pdev;
753 as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
754 if (!as->regs)
755 goto out_free_buffer;
756 as->irq = irq;
757 as->clk = clk;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800758 if (!cpu_is_at91rm9200())
759 as->new_1 = 1;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800760
761 ret = request_irq(irq, atmel_spi_interrupt, 0,
762 pdev->dev.bus_id, master);
763 if (ret)
764 goto out_unmap_regs;
765
766 /* Initialize the hardware */
767 clk_enable(clk);
768 spi_writel(as, CR, SPI_BIT(SWRST));
769 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
770 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
771 spi_writel(as, CR, SPI_BIT(SPIEN));
772
773 /* go! */
774 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
775 (unsigned long)regs->start, irq);
776
777 ret = spi_register_master(master);
778 if (ret)
779 goto out_reset_hw;
780
781 return 0;
782
783out_reset_hw:
784 spi_writel(as, CR, SPI_BIT(SWRST));
785 clk_disable(clk);
786 free_irq(irq, master);
787out_unmap_regs:
788 iounmap(as->regs);
789out_free_buffer:
790 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
791 as->buffer_dma);
792out_free:
793 clk_put(clk);
794 spi_master_put(master);
795 return ret;
796}
797
798static int __exit atmel_spi_remove(struct platform_device *pdev)
799{
800 struct spi_master *master = platform_get_drvdata(pdev);
801 struct atmel_spi *as = spi_master_get_devdata(master);
802 struct spi_message *msg;
803
804 /* reset the hardware and block queue progress */
805 spin_lock_irq(&as->lock);
806 as->stopping = 1;
807 spi_writel(as, CR, SPI_BIT(SWRST));
808 spi_readl(as, SR);
809 spin_unlock_irq(&as->lock);
810
811 /* Terminate remaining queued transfers */
812 list_for_each_entry(msg, &as->queue, queue) {
813 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
814 * but we shouldn't depend on that...
815 */
816 msg->status = -ESHUTDOWN;
817 msg->complete(msg->context);
818 }
819
820 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
821 as->buffer_dma);
822
823 clk_disable(as->clk);
824 clk_put(as->clk);
825 free_irq(as->irq, master);
826 iounmap(as->regs);
827
828 spi_unregister_master(master);
829
830 return 0;
831}
832
833#ifdef CONFIG_PM
834
835static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
836{
837 struct spi_master *master = platform_get_drvdata(pdev);
838 struct atmel_spi *as = spi_master_get_devdata(master);
839
840 clk_disable(as->clk);
841 return 0;
842}
843
844static int atmel_spi_resume(struct platform_device *pdev)
845{
846 struct spi_master *master = platform_get_drvdata(pdev);
847 struct atmel_spi *as = spi_master_get_devdata(master);
848
849 clk_enable(as->clk);
850 return 0;
851}
852
853#else
854#define atmel_spi_suspend NULL
855#define atmel_spi_resume NULL
856#endif
857
858
859static struct platform_driver atmel_spi_driver = {
860 .driver = {
861 .name = "atmel_spi",
862 .owner = THIS_MODULE,
863 },
864 .suspend = atmel_spi_suspend,
865 .resume = atmel_spi_resume,
866 .remove = __exit_p(atmel_spi_remove),
867};
868
869static int __init atmel_spi_init(void)
870{
871 return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
872}
873module_init(atmel_spi_init);
874
875static void __exit atmel_spi_exit(void)
876{
877 platform_driver_unregister(&atmel_spi_driver);
878}
879module_exit(atmel_spi_exit);
880
881MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
882MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
883MODULE_LICENSE("GPL");
Kay Sievers7e38c3c2008-04-10 21:29:20 -0700884MODULE_ALIAS("platform:atmel_spi");