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Ben Dooks7fba5342006-05-20 15:00:18 -07001/* linux/drivers/spi/spi_s3c24xx.c
2 *
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11*/
12
Ben Dooks7fba5342006-05-20 15:00:18 -070013#include <linux/init.h>
14#include <linux/spinlock.h>
15#include <linux/workqueue.h>
16#include <linux/interrupt.h>
17#include <linux/delay.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/platform_device.h>
22
23#include <linux/spi/spi.h>
24#include <linux/spi/spi_bitbang.h>
25
26#include <asm/io.h>
27#include <asm/dma.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010028#include <mach/hardware.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070029
Russell Kinga09e64f2008-08-05 16:14:15 +010030#include <mach/regs-gpio.h>
Ben Dooks47572b82007-07-26 10:40:59 -070031#include <asm/plat-s3c24xx/regs-spi.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010032#include <mach/spi.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070033
34struct s3c24xx_spi {
35 /* bitbang has to be first */
36 struct spi_bitbang bitbang;
37 struct completion done;
38
39 void __iomem *regs;
40 int irq;
41 int len;
42 int count;
43
Arnaud Patard (Rtp6c912a32007-03-16 13:38:36 -080044 void (*set_cs)(struct s3c2410_spi_info *spi,
Ben Dooks8736b922007-01-26 00:56:43 -080045 int cs, int pol);
46
Ben Dooks7fba5342006-05-20 15:00:18 -070047 /* data buffers */
48 const unsigned char *tx;
49 unsigned char *rx;
50
51 struct clk *clk;
52 struct resource *ioarea;
53 struct spi_master *master;
54 struct spi_device *curdev;
55 struct device *dev;
56 struct s3c2410_spi_info *pdata;
57};
58
59#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
60#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
61
62static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
63{
64 return spi_master_get_devdata(sdev->master);
65}
66
Ben Dooks8736b922007-01-26 00:56:43 -080067static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
68{
69 s3c2410_gpio_setpin(spi->pin_cs, pol);
70}
71
Ben Dooks7fba5342006-05-20 15:00:18 -070072static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
73{
74 struct s3c24xx_spi *hw = to_hw(spi);
75 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
76 unsigned int spcon;
77
78 switch (value) {
79 case BITBANG_CS_INACTIVE:
Ben Dooks3d2c5b42007-04-16 22:53:22 -070080 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
Ben Dooks7fba5342006-05-20 15:00:18 -070081 break;
82
83 case BITBANG_CS_ACTIVE:
84 spcon = readb(hw->regs + S3C2410_SPCON);
85
86 if (spi->mode & SPI_CPHA)
87 spcon |= S3C2410_SPCON_CPHA_FMTB;
88 else
89 spcon &= ~S3C2410_SPCON_CPHA_FMTB;
90
91 if (spi->mode & SPI_CPOL)
92 spcon |= S3C2410_SPCON_CPOL_HIGH;
93 else
94 spcon &= ~S3C2410_SPCON_CPOL_HIGH;
95
96 spcon |= S3C2410_SPCON_ENSCK;
97
98 /* write new configration */
99
100 writeb(spcon, hw->regs + S3C2410_SPCON);
Ben Dooks3d2c5b42007-04-16 22:53:22 -0700101 hw->set_cs(hw->pdata, spi->chip_select, cspol);
Ben Dooks7fba5342006-05-20 15:00:18 -0700102
103 break;
Ben Dooks7fba5342006-05-20 15:00:18 -0700104 }
105}
106
107static int s3c24xx_spi_setupxfer(struct spi_device *spi,
108 struct spi_transfer *t)
109{
110 struct s3c24xx_spi *hw = to_hw(spi);
111 unsigned int bpw;
112 unsigned int hz;
113 unsigned int div;
114
115 bpw = t ? t->bits_per_word : spi->bits_per_word;
116 hz = t ? t->speed_hz : spi->max_speed_hz;
117
118 if (bpw != 8) {
119 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
120 return -EINVAL;
121 }
122
123 div = clk_get_rate(hw->clk) / hz;
124
125 /* is clk = pclk / (2 * (pre+1)), or is it
126 * clk = (pclk * 2) / ( pre + 1) */
127
Matthew Wilcox0d34aa42008-05-01 04:35:04 -0700128 div /= 2;
Ben Dooks7fba5342006-05-20 15:00:18 -0700129
Matthew Wilcox0d34aa42008-05-01 04:35:04 -0700130 if (div > 0)
131 div -= 1;
Ben Dooks7fba5342006-05-20 15:00:18 -0700132
133 if (div > 255)
134 div = 255;
135
136 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
137 writeb(div, hw->regs + S3C2410_SPPRE);
138
139 spin_lock(&hw->bitbang.lock);
140 if (!hw->bitbang.busy) {
141 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
142 /* need to ndelay for 0.5 clocktick ? */
143 }
144 spin_unlock(&hw->bitbang.lock);
145
146 return 0;
147}
148
David Brownelldccd5732007-07-17 04:04:02 -0700149/* the spi->mode bits understood by this driver: */
150#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
151
Ben Dooks7fba5342006-05-20 15:00:18 -0700152static int s3c24xx_spi_setup(struct spi_device *spi)
153{
154 int ret;
155
156 if (!spi->bits_per_word)
157 spi->bits_per_word = 8;
158
David Brownelldccd5732007-07-17 04:04:02 -0700159 if (spi->mode & ~MODEBITS) {
160 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
161 spi->mode & ~MODEBITS);
Ben Dooks7fba5342006-05-20 15:00:18 -0700162 return -EINVAL;
David Brownelldccd5732007-07-17 04:04:02 -0700163 }
Ben Dooks7fba5342006-05-20 15:00:18 -0700164
165 ret = s3c24xx_spi_setupxfer(spi, NULL);
166 if (ret < 0) {
167 dev_err(&spi->dev, "setupxfer returned %d\n", ret);
168 return ret;
169 }
170
171 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
Harvey Harrisonb687d2a2008-04-28 02:14:19 -0700172 __func__, spi->mode, spi->bits_per_word,
Ben Dooks7fba5342006-05-20 15:00:18 -0700173 spi->max_speed_hz);
174
175 return 0;
176}
177
178static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
179{
David Brownell4b1badf2006-12-29 16:48:39 -0800180 return hw->tx ? hw->tx[count] : 0;
Ben Dooks7fba5342006-05-20 15:00:18 -0700181}
182
183static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
184{
185 struct s3c24xx_spi *hw = to_hw(spi);
186
187 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
188 t->tx_buf, t->rx_buf, t->len);
189
190 hw->tx = t->tx_buf;
191 hw->rx = t->rx_buf;
192 hw->len = t->len;
193 hw->count = 0;
194
Ben Dooks4bb5eba2008-04-15 14:34:44 -0700195 init_completion(&hw->done);
196
Ben Dooks7fba5342006-05-20 15:00:18 -0700197 /* send the first byte */
198 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
Ben Dooks4bb5eba2008-04-15 14:34:44 -0700199
Ben Dooks7fba5342006-05-20 15:00:18 -0700200 wait_for_completion(&hw->done);
201
202 return hw->count;
203}
204
David Howells7d12e782006-10-05 14:55:46 +0100205static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700206{
207 struct s3c24xx_spi *hw = dev;
208 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
209 unsigned int count = hw->count;
210
211 if (spsta & S3C2410_SPSTA_DCOL) {
212 dev_dbg(hw->dev, "data-collision\n");
213 complete(&hw->done);
214 goto irq_done;
215 }
216
217 if (!(spsta & S3C2410_SPSTA_READY)) {
218 dev_dbg(hw->dev, "spi not ready for tx?\n");
219 complete(&hw->done);
220 goto irq_done;
221 }
222
223 hw->count++;
224
225 if (hw->rx)
226 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
227
228 count++;
229
230 if (count < hw->len)
231 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
232 else
233 complete(&hw->done);
234
235 irq_done:
236 return IRQ_HANDLED;
237}
238
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700239static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
240{
241 /* for the moment, permanently enable the clock */
242
243 clk_enable(hw->clk);
244
245 /* program defaults into the registers */
246
247 writeb(0xff, hw->regs + S3C2410_SPPRE);
248 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
249 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
250}
251
David Brownelld1e44d92007-10-16 01:27:46 -0700252static int __init s3c24xx_spi_probe(struct platform_device *pdev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700253{
Ben Dooks50f426b2008-04-15 14:34:45 -0700254 struct s3c2410_spi_info *pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700255 struct s3c24xx_spi *hw;
256 struct spi_master *master;
Ben Dooks7fba5342006-05-20 15:00:18 -0700257 struct resource *res;
258 int err = 0;
Ben Dooks7fba5342006-05-20 15:00:18 -0700259
260 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
261 if (master == NULL) {
262 dev_err(&pdev->dev, "No memory for spi_master\n");
263 err = -ENOMEM;
264 goto err_nomem;
265 }
266
267 hw = spi_master_get_devdata(master);
268 memset(hw, 0, sizeof(struct s3c24xx_spi));
269
270 hw->master = spi_master_get(master);
Ben Dooks50f426b2008-04-15 14:34:45 -0700271 hw->pdata = pdata = pdev->dev.platform_data;
Ben Dooks7fba5342006-05-20 15:00:18 -0700272 hw->dev = &pdev->dev;
273
Ben Dooks50f426b2008-04-15 14:34:45 -0700274 if (pdata == NULL) {
Ben Dooks7fba5342006-05-20 15:00:18 -0700275 dev_err(&pdev->dev, "No platform data supplied\n");
276 err = -ENOENT;
277 goto err_no_pdata;
278 }
279
280 platform_set_drvdata(pdev, hw);
281 init_completion(&hw->done);
282
Ben Dooksd1e77802008-04-15 14:34:46 -0700283 /* setup the master state. */
284
285 master->num_chipselect = hw->pdata->num_cs;
Ben Dookscb1d0a72008-07-28 15:46:33 -0700286 master->bus_num = pdata->bus_num;
Ben Dooksd1e77802008-04-15 14:34:46 -0700287
Ben Dooks7fba5342006-05-20 15:00:18 -0700288 /* setup the state for the bitbang driver */
289
290 hw->bitbang.master = hw->master;
291 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
292 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
293 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
294 hw->bitbang.master->setup = s3c24xx_spi_setup;
295
296 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
297
298 /* find and map our resources */
299
300 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
301 if (res == NULL) {
302 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
303 err = -ENOENT;
304 goto err_no_iores;
305 }
306
307 hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
308 pdev->name);
309
310 if (hw->ioarea == NULL) {
311 dev_err(&pdev->dev, "Cannot reserve region\n");
312 err = -ENXIO;
313 goto err_no_iores;
314 }
315
316 hw->regs = ioremap(res->start, (res->end - res->start)+1);
317 if (hw->regs == NULL) {
318 dev_err(&pdev->dev, "Cannot map IO\n");
319 err = -ENXIO;
320 goto err_no_iomap;
321 }
322
323 hw->irq = platform_get_irq(pdev, 0);
324 if (hw->irq < 0) {
325 dev_err(&pdev->dev, "No IRQ specified\n");
326 err = -ENOENT;
327 goto err_no_irq;
328 }
329
330 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
331 if (err) {
332 dev_err(&pdev->dev, "Cannot claim IRQ\n");
333 goto err_no_irq;
334 }
335
336 hw->clk = clk_get(&pdev->dev, "spi");
337 if (IS_ERR(hw->clk)) {
338 dev_err(&pdev->dev, "No clock for device\n");
339 err = PTR_ERR(hw->clk);
340 goto err_no_clk;
341 }
342
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700343 s3c24xx_spi_initialsetup(hw);
Ben Dooks7fba5342006-05-20 15:00:18 -0700344
345 /* setup any gpio we can */
346
Ben Dooks50f426b2008-04-15 14:34:45 -0700347 if (!pdata->set_cs) {
Ben Dooks8736b922007-01-26 00:56:43 -0800348 hw->set_cs = s3c24xx_spi_gpiocs;
349
Ben Dooks50f426b2008-04-15 14:34:45 -0700350 s3c2410_gpio_setpin(pdata->pin_cs, 1);
351 s3c2410_gpio_cfgpin(pdata->pin_cs, S3C2410_GPIO_OUTPUT);
Ben Dooks8736b922007-01-26 00:56:43 -0800352 } else
Ben Dooks50f426b2008-04-15 14:34:45 -0700353 hw->set_cs = pdata->set_cs;
Ben Dooks7fba5342006-05-20 15:00:18 -0700354
355 /* register our spi controller */
356
357 err = spi_bitbang_start(&hw->bitbang);
358 if (err) {
359 dev_err(&pdev->dev, "Failed to register SPI master\n");
360 goto err_register;
361 }
362
Ben Dooks7fba5342006-05-20 15:00:18 -0700363 return 0;
364
365 err_register:
366 clk_disable(hw->clk);
367 clk_put(hw->clk);
368
369 err_no_clk:
370 free_irq(hw->irq, hw);
371
372 err_no_irq:
373 iounmap(hw->regs);
374
375 err_no_iomap:
376 release_resource(hw->ioarea);
377 kfree(hw->ioarea);
378
379 err_no_iores:
380 err_no_pdata:
381 spi_master_put(hw->master);;
382
383 err_nomem:
384 return err;
385}
386
David Brownelld1e44d92007-10-16 01:27:46 -0700387static int __exit s3c24xx_spi_remove(struct platform_device *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700388{
389 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
390
391 platform_set_drvdata(dev, NULL);
392
393 spi_unregister_master(hw->master);
394
395 clk_disable(hw->clk);
396 clk_put(hw->clk);
397
398 free_irq(hw->irq, hw);
399 iounmap(hw->regs);
400
401 release_resource(hw->ioarea);
402 kfree(hw->ioarea);
403
404 spi_master_put(hw->master);
405 return 0;
406}
407
408
409#ifdef CONFIG_PM
410
411static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
412{
Ben Dooksac88bcf2006-05-25 18:44:25 -0700413 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
Ben Dooks7fba5342006-05-20 15:00:18 -0700414
415 clk_disable(hw->clk);
416 return 0;
417}
418
419static int s3c24xx_spi_resume(struct platform_device *pdev)
420{
Ben Dooksac88bcf2006-05-25 18:44:25 -0700421 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
Ben Dooks7fba5342006-05-20 15:00:18 -0700422
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700423 s3c24xx_spi_initialsetup(hw);
Ben Dooks7fba5342006-05-20 15:00:18 -0700424 return 0;
425}
426
427#else
428#define s3c24xx_spi_suspend NULL
429#define s3c24xx_spi_resume NULL
430#endif
431
Kay Sievers7e38c3c2008-04-10 21:29:20 -0700432MODULE_ALIAS("platform:s3c2410-spi");
Ben Dooks7fba5342006-05-20 15:00:18 -0700433static struct platform_driver s3c24xx_spidrv = {
David Brownelld1e44d92007-10-16 01:27:46 -0700434 .remove = __exit_p(s3c24xx_spi_remove),
Ben Dooks7fba5342006-05-20 15:00:18 -0700435 .suspend = s3c24xx_spi_suspend,
436 .resume = s3c24xx_spi_resume,
437 .driver = {
438 .name = "s3c2410-spi",
439 .owner = THIS_MODULE,
440 },
441};
442
443static int __init s3c24xx_spi_init(void)
444{
David Brownelld1e44d92007-10-16 01:27:46 -0700445 return platform_driver_probe(&s3c24xx_spidrv, s3c24xx_spi_probe);
Ben Dooks7fba5342006-05-20 15:00:18 -0700446}
447
448static void __exit s3c24xx_spi_exit(void)
449{
450 platform_driver_unregister(&s3c24xx_spidrv);
451}
452
453module_init(s3c24xx_spi_init);
454module_exit(s3c24xx_spi_exit);
455
456MODULE_DESCRIPTION("S3C24XX SPI Driver");
457MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
458MODULE_LICENSE("GPL");