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gerrit-public.fairphone.software / kernel / msm / a1b81a84fff05dbfef45b7012c26e1fee9973e5d / . / include / asm-arm / arch-pnx4008 / entry-macro.S
blob: f11731974e5d5a2b2b3123783b16cb8b7bc19375 [file] [log] [blame]
Vitaly Woola5a50302006-05-16 11:54:36 +0100[diff] [blame]1/*
2 * include/asm-arm/arch-pnx4008/entry-macro.S
3 *
4 * Low-level IRQ helper macros for PNX4008-based platforms
5 *
6 * 2005-2006 (c) MontaVista Software, Inc.
7 * Author: Vitaly Wool <vwool@ru.mvista.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include "platform.h"
14
15#define IO_BASE 0xF0000000
16#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
17
18#define INTRC_MASK 0x00
19#define INTRC_RAW_STAT 0x04
20#define INTRC_STAT 0x08
21#define INTRC_POLAR 0x0C
22#define INTRC_ACT_TYPE 0x10
23#define INTRC_TYPE 0x14
24
25#define SIC1_BASE_INT 32
26#define SIC2_BASE_INT 64
27
28 .macro disable_fiq
29 .endm
30
Dan Williamsf80dff92007-02-16 22:16:32 +0100[diff] [blame]31 .macro get_irqnr_preamble, base, tmp
32 .endm
33
34 .macro arch_ret_to_user, tmp1, tmp2
35 .endm
36
Vitaly Woola5a50302006-05-16 11:54:36 +0100[diff] [blame]37 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
38/* decode the MIC interrupt numbers */
39 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
40 ldr \irqstat, [\base, #INTRC_STAT]
41
42 cmp \irqstat,#1<<16
43 movhs \irqnr,#16
44 movlo \irqnr,#0
45 movhs \irqstat,\irqstat,lsr#16
46 cmp \irqstat,#1<<8
47 addhs \irqnr,\irqnr,#8
48 movhs \irqstat,\irqstat,lsr#8
49 cmp \irqstat,#1<<4
50 addhs \irqnr,\irqnr,#4
51 movhs \irqstat,\irqstat,lsr#4
52 cmp \irqstat,#1<<2
53 addhs \irqnr,\irqnr,#2
54 movhs \irqstat,\irqstat,lsr#2
55 cmp \irqstat,#1<<1
56 addhs \irqnr,\irqnr,#1
57
58/* was there an interrupt ? if not then drop out with EQ status */
59 teq \irqstat,#0
60 beq 1003f
61
62/* and now check for extended IRQ reasons */
63 cmp \irqnr,#1
64 bls 1003f
65 cmp \irqnr,#30
66 blo 1002f
67
68/* IRQ 31,30 : High priority cascade IRQ handle */
69/* read the correct SIC */
70/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
71/* set the base IRQ number */
72 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
73 moveq \irqnr,#SIC1_BASE_INT
74 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
75 movne \irqnr,#SIC2_BASE_INT
76 ldr \irqstat, [\base, #INTRC_STAT]
77 ldr \tmp, [\base, #INTRC_TYPE]
78/* and with inverted mask : low priority interrupts */
79 and \irqstat,\irqstat,\tmp
80 b 1004f
81
821003:
83/* IRQ 1,0 : Low priority cascade IRQ handle */
84/* read the correct SIC */
85/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
86/* read the correct SIC */
87/* set the base IRQ number */
88 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
89 movne \irqnr,#SIC1_BASE_INT
90 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
91 moveq \irqnr,#SIC2_BASE_INT
92 ldr \irqstat, [\base, #INTRC_STAT]
93 ldr \tmp, [\base, #INTRC_TYPE]
94/* and with inverted mask : low priority interrupts */
95 bic \irqstat,\irqstat,\tmp
96
971004:
98
99 cmp \irqstat,#1<<16
100 addhs \irqnr,\irqnr,#16
101 movhs \irqstat,\irqstat,lsr#16
102 cmp \irqstat,#1<<8
103 addhs \irqnr,\irqnr,#8
104 movhs \irqstat,\irqstat,lsr#8
105 cmp \irqstat,#1<<4
106 addhs \irqnr,\irqnr,#4
107 movhs \irqstat,\irqstat,lsr#4
108 cmp \irqstat,#1<<2
109 addhs \irqnr,\irqnr,#2
110 movhs \irqstat,\irqstat,lsr#2
111 cmp \irqstat,#1<<1
112 addhs \irqnr,\irqnr,#1
113
114
115/* is irqstat not zero */
116
1171002:
118/* we assert that irqstat is not equal to zero and return ne status if true*/
119 teq \irqstat,#0
1201003:
121 .endm
122
123
124 .macro irq_prio_table
125 .endm
126
127