blob: fae868a8d499257caaedc3be66391cf25310af82 [file] [log] [blame]
David Brownella30d46c2008-10-20 23:46:28 +02001/*
2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 */
29
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/kthread.h>
34
35#include <linux/i2c/twl4030.h>
36
37
38/*
39 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
40 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
41 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
42 * SIH modules are more traditional IRQ components, which support per-IRQ
43 * enable/disable and trigger controls; they do most of the work.
44 *
45 * These chips are designed to support IRQ handling from two different
46 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
47 * and mask registers in the PIH and SIH modules.
48 *
49 * We set up IRQs starting at a platform-specified base, always starting
50 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
51 * base + 0 .. base + 7 PIH
52 * base + 8 .. base + 15 SIH for PWR_INT
53 * base + 16 .. base + 33 SIH for GPIO
54 */
55
56/* PIH register offsets */
57#define REG_PIH_ISR_P1 0x01
58#define REG_PIH_ISR_P2 0x02
59#define REG_PIH_SIR 0x03 /* for testing */
60
61
62/* Linux could (eventually) use either IRQ line */
63static int irq_line;
64
65struct sih {
66 char name[8];
67 u8 module; /* module id */
68 u8 control_offset; /* for SIH_CTRL */
69 bool set_cor;
70
71 u8 bits; /* valid in isr/imr */
72 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
73
74 u8 edr_offset;
75 u8 bytes_edr; /* bytelen of EDR */
76
77 /* SIR ignored -- set interrupt, for testing only */
78 struct irq_data {
79 u8 isr_offset;
80 u8 imr_offset;
81 } mask[2];
82 /* + 2 bytes padding */
83};
84
85#define SIH_INITIALIZER(modname, nbits) \
86 .module = TWL4030_MODULE_ ## modname, \
87 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
88 .bits = nbits, \
89 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
90 .edr_offset = TWL4030_ ## modname ## _EDR, \
91 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
92 .mask = { { \
93 .isr_offset = TWL4030_ ## modname ## _ISR1, \
94 .imr_offset = TWL4030_ ## modname ## _IMR1, \
95 }, \
96 { \
97 .isr_offset = TWL4030_ ## modname ## _ISR2, \
98 .imr_offset = TWL4030_ ## modname ## _IMR2, \
99 }, },
100
101/* register naming policies are inconsistent ... */
102#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
103#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
104#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
105
106
107/* Order in this table matches order in PIH_ISR. That is,
108 * BIT(n) in PIH_ISR is sih_modules[n].
109 */
110static const struct sih sih_modules[6] = {
111 [0] = {
112 .name = "gpio",
113 .module = TWL4030_MODULE_GPIO,
114 .control_offset = REG_GPIO_SIH_CTRL,
115 .set_cor = true,
116 .bits = TWL4030_GPIO_MAX,
117 .bytes_ixr = 3,
118 /* Note: *all* of these IRQs default to no-trigger */
119 .edr_offset = REG_GPIO_EDR1,
120 .bytes_edr = 5,
121 .mask = { {
122 .isr_offset = REG_GPIO_ISR1A,
123 .imr_offset = REG_GPIO_IMR1A,
124 }, {
125 .isr_offset = REG_GPIO_ISR1B,
126 .imr_offset = REG_GPIO_IMR1B,
127 }, },
128 },
129 [1] = {
130 .name = "keypad",
131 .set_cor = true,
132 SIH_INITIALIZER(KEYPAD_KEYP, 4)
133 },
134 [2] = {
135 .name = "bci",
136 .module = TWL4030_MODULE_INTERRUPTS,
137 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
138 .bits = 12,
139 .bytes_ixr = 2,
140 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
141 /* Note: most of these IRQs default to no-trigger */
142 .bytes_edr = 3,
143 .mask = { {
144 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
145 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
146 }, {
147 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
148 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
149 }, },
150 },
151 [3] = {
152 .name = "madc",
153 SIH_INITIALIZER(MADC, 4)
154 },
155 [4] = {
156 /* USB doesn't use the same SIH organization */
157 .name = "usb",
158 },
159 [5] = {
160 .name = "power",
161 .set_cor = true,
162 SIH_INITIALIZER(INT_PWR, 8)
163 },
164 /* there are no SIH modules #6 or #7 ... */
165};
166
167#undef TWL4030_MODULE_KEYPAD_KEYP
168#undef TWL4030_MODULE_INT_PWR
169#undef TWL4030_INT_PWR_EDR
170
171/*----------------------------------------------------------------------*/
172
173static unsigned twl4030_irq_base;
174
175static struct completion irq_event;
176
177/*
178 * This thread processes interrupts reported by the Primary Interrupt Handler.
179 */
180static int twl4030_irq_thread(void *data)
181{
182 long irq = (long)data;
183 irq_desc_t *desc = irq_desc + irq;
184 static unsigned i2c_errors;
185 const static unsigned max_i2c_errors = 100;
186
187 current->flags |= PF_NOFREEZE;
188
189 while (!kthread_should_stop()) {
190 int ret;
191 int module_irq;
192 u8 pih_isr;
193
194 /* Wait for IRQ, then read PIH irq status (also blocking) */
195 wait_for_completion_interruptible(&irq_event);
196
197 ret = twl4030_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
198 REG_PIH_ISR_P1);
199 if (ret) {
200 pr_warning("twl4030: I2C error %d reading PIH ISR\n",
201 ret);
202 if (++i2c_errors >= max_i2c_errors) {
203 printk(KERN_ERR "Maximum I2C error count"
204 " exceeded. Terminating %s.\n",
205 __func__);
206 break;
207 }
208 complete(&irq_event);
209 continue;
210 }
211
212 /* these handlers deal with the relevant SIH irq status */
213 local_irq_disable();
214 for (module_irq = twl4030_irq_base;
215 pih_isr;
216 pih_isr >>= 1, module_irq++) {
217 if (pih_isr & 0x1) {
218 irq_desc_t *d = irq_desc + module_irq;
219
220 /* These can't be masked ... always warn
221 * if we get any surprises.
222 */
223 if (d->status & IRQ_DISABLED)
224 note_interrupt(module_irq, d,
225 IRQ_NONE);
226 else
227 d->handle_irq(module_irq, d);
228 }
229 }
230 local_irq_enable();
231
232 desc->chip->unmask(irq);
233 }
234
235 return 0;
236}
237
238/*
239 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
240 * This is a chained interrupt, so there is no desc->action method for it.
241 * Now we need to query the interrupt controller in the twl4030 to determine
242 * which module is generating the interrupt request. However, we can't do i2c
243 * transactions in interrupt context, so we must defer that work to a kernel
244 * thread. All we do here is acknowledge and mask the interrupt and wakeup
245 * the kernel thread.
246 */
247static void handle_twl4030_pih(unsigned int irq, irq_desc_t *desc)
248{
249 /* Acknowledge, clear *AND* mask the interrupt... */
250 desc->chip->ack(irq);
251 complete(&irq_event);
252}
253
254static struct task_struct *start_twl4030_irq_thread(long irq)
255{
256 struct task_struct *thread;
257
258 init_completion(&irq_event);
259 thread = kthread_run(twl4030_irq_thread, (void *)irq, "twl4030-irq");
260 if (!thread)
261 pr_err("twl4030: could not create irq %ld thread!\n", irq);
262
263 return thread;
264}
265
266/*----------------------------------------------------------------------*/
267
268/*
269 * twl4030_init_sih_modules() ... start from a known state where no
270 * IRQs will be coming in, and where we can quickly enable them then
271 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
272 *
273 * NOTE: we don't touch EDR registers here; they stay with hardware
274 * defaults or whatever the last value was. Note that when both EDR
275 * bits for an IRQ are clear, that's as if its IMR bit is set...
276 */
277static int twl4030_init_sih_modules(unsigned line)
278{
279 const struct sih *sih;
280 u8 buf[4];
281 int i;
282 int status;
283
284 /* line 0 == int1_n signal; line 1 == int2_n signal */
285 if (line > 1)
286 return -EINVAL;
287
288 irq_line = line;
289
290 /* disable all interrupts on our line */
291 memset(buf, 0xff, sizeof buf);
292 sih = sih_modules;
293 for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) {
294
295 /* skip USB -- it's funky */
296 if (!sih->bytes_ixr)
297 continue;
298
299 status = twl4030_i2c_write(sih->module, buf,
300 sih->mask[line].imr_offset, sih->bytes_ixr);
301 if (status < 0)
302 pr_err("twl4030: err %d initializing %s %s\n",
303 status, sih->name, "IMR");
304
305 /* Maybe disable "exclusive" mode; buffer second pending irq;
306 * set Clear-On-Read (COR) bit.
307 *
308 * NOTE that sometimes COR polarity is documented as being
309 * inverted: for MADC and BCI, COR=1 means "clear on write".
310 * And for PWR_INT it's not documented...
311 */
312 if (sih->set_cor) {
313 status = twl4030_i2c_write_u8(sih->module,
314 TWL4030_SIH_CTRL_COR_MASK,
315 sih->control_offset);
316 if (status < 0)
317 pr_err("twl4030: err %d initializing %s %s\n",
318 status, sih->name, "SIH_CTRL");
319 }
320 }
321
322 sih = sih_modules;
323 for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) {
324 u8 rxbuf[4];
325 int j;
326
327 /* skip USB */
328 if (!sih->bytes_ixr)
329 continue;
330
331 /* Clear pending interrupt status. Either the read was
332 * enough, or we need to write those bits. Repeat, in
333 * case an IRQ is pending (PENDDIS=0) ... that's not
334 * uncommon with PWR_INT.PWRON.
335 */
336 for (j = 0; j < 2; j++) {
337 status = twl4030_i2c_read(sih->module, rxbuf,
338 sih->mask[line].isr_offset, sih->bytes_ixr);
339 if (status < 0)
340 pr_err("twl4030: err %d initializing %s %s\n",
341 status, sih->name, "ISR");
342
343 if (!sih->set_cor)
344 status = twl4030_i2c_write(sih->module, buf,
345 sih->mask[line].isr_offset,
346 sih->bytes_ixr);
347 /* else COR=1 means read sufficed.
348 * (for most SIH modules...)
349 */
350 }
351 }
352
353 return 0;
354}
355
356static inline void activate_irq(int irq)
357{
358#ifdef CONFIG_ARM
359 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
360 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
361 */
362 set_irq_flags(irq, IRQF_VALID);
363#else
364 /* same effect on other architectures */
365 set_irq_noprobe(irq);
366#endif
367}
368
369/*----------------------------------------------------------------------*/
370
371static DEFINE_SPINLOCK(sih_agent_lock);
372
373static struct workqueue_struct *wq;
374
375struct sih_agent {
376 int irq_base;
377 const struct sih *sih;
378
379 u32 imr;
380 bool imr_change_pending;
381 struct work_struct mask_work;
382
383 u32 edge_change;
384 struct work_struct edge_work;
385};
386
387static void twl4030_sih_do_mask(struct work_struct *work)
388{
389 struct sih_agent *agent;
390 const struct sih *sih;
391 union {
392 u8 bytes[4];
393 u32 word;
394 } imr;
395 int status;
396
397 agent = container_of(work, struct sih_agent, mask_work);
398
399 /* see what work we have */
400 spin_lock_irq(&sih_agent_lock);
401 if (agent->imr_change_pending) {
402 sih = agent->sih;
403 /* byte[0] gets overwritten as we write ... */
404 imr.word = cpu_to_le32(agent->imr << 8);
405 agent->imr_change_pending = false;
406 } else
407 sih = NULL;
408 spin_unlock_irq(&sih_agent_lock);
409 if (!sih)
410 return;
411
412 /* write the whole mask ... simpler than subsetting it */
413 status = twl4030_i2c_write(sih->module, imr.bytes,
414 sih->mask[irq_line].imr_offset, sih->bytes_ixr);
415 if (status)
416 pr_err("twl4030: %s, %s --> %d\n", __func__,
417 "write", status);
418}
419
420static void twl4030_sih_do_edge(struct work_struct *work)
421{
422 struct sih_agent *agent;
423 const struct sih *sih;
424 u8 bytes[6];
425 u32 edge_change;
426 int status;
427
428 agent = container_of(work, struct sih_agent, edge_work);
429
430 /* see what work we have */
431 spin_lock_irq(&sih_agent_lock);
432 edge_change = agent->edge_change;
433 agent->edge_change = 0;;
434 sih = edge_change ? agent->sih : NULL;
435 spin_unlock_irq(&sih_agent_lock);
436 if (!sih)
437 return;
438
439 /* Read, reserving first byte for write scratch. Yes, this
440 * could be cached for some speedup ... but be careful about
441 * any processor on the other IRQ line, EDR registers are
442 * shared.
443 */
444 status = twl4030_i2c_read(sih->module, bytes + 1,
445 sih->edr_offset, sih->bytes_edr);
446 if (status) {
447 pr_err("twl4030: %s, %s --> %d\n", __func__,
448 "read", status);
449 return;
450 }
451
452 /* Modify only the bits we know must change */
453 while (edge_change) {
454 int i = fls(edge_change) - 1;
455 struct irq_desc *d = irq_desc + i + agent->irq_base;
456 int byte = 1 + (i >> 2);
457 int off = (i & 0x3) * 2;
458
459 bytes[byte] &= ~(0x03 << off);
460
461 spin_lock_irq(&d->lock);
462 if (d->status & IRQ_TYPE_EDGE_RISING)
463 bytes[byte] |= BIT(off + 1);
464 if (d->status & IRQ_TYPE_EDGE_FALLING)
465 bytes[byte] |= BIT(off + 0);
466 spin_unlock_irq(&d->lock);
467
468 edge_change &= ~BIT(i);
469 }
470
471 /* Write */
472 status = twl4030_i2c_write(sih->module, bytes,
473 sih->edr_offset, sih->bytes_edr);
474 if (status)
475 pr_err("twl4030: %s, %s --> %d\n", __func__,
476 "write", status);
477}
478
479/*----------------------------------------------------------------------*/
480
481/*
482 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
483 * which can't perform the underlying I2C operations (because they sleep).
484 * So we must hand them off to a thread (workqueue) and cope with asynch
485 * completion, potentially including some re-ordering, of these requests.
486 */
487
488static void twl4030_sih_mask(unsigned irq)
489{
490 struct sih_agent *sih = get_irq_chip_data(irq);
491 unsigned long flags;
492
493 spin_lock_irqsave(&sih_agent_lock, flags);
494 sih->imr |= BIT(irq - sih->irq_base);
495 sih->imr_change_pending = true;
496 queue_work(wq, &sih->mask_work);
497 spin_unlock_irqrestore(&sih_agent_lock, flags);
498}
499
500static void twl4030_sih_unmask(unsigned irq)
501{
502 struct sih_agent *sih = get_irq_chip_data(irq);
503 unsigned long flags;
504
505 spin_lock_irqsave(&sih_agent_lock, flags);
506 sih->imr &= ~BIT(irq - sih->irq_base);
507 sih->imr_change_pending = true;
508 queue_work(wq, &sih->mask_work);
509 spin_unlock_irqrestore(&sih_agent_lock, flags);
510}
511
512static int twl4030_sih_set_type(unsigned irq, unsigned trigger)
513{
514 struct sih_agent *sih = get_irq_chip_data(irq);
515 struct irq_desc *desc = irq_desc + irq;
516 unsigned long flags;
517
518 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
519 return -EINVAL;
520
521 spin_lock_irqsave(&sih_agent_lock, flags);
522 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) {
523 desc->status &= ~IRQ_TYPE_SENSE_MASK;
524 desc->status |= trigger;
525 sih->edge_change |= BIT(irq - sih->irq_base);
526 queue_work(wq, &sih->edge_work);
527 }
528 spin_unlock_irqrestore(&sih_agent_lock, flags);
529 return 0;
530}
531
532static struct irq_chip twl4030_sih_irq_chip = {
533 .name = "twl4030",
534 .mask = twl4030_sih_mask,
535 .unmask = twl4030_sih_unmask,
536 .set_type = twl4030_sih_set_type,
537};
538
539/*----------------------------------------------------------------------*/
540
541static inline int sih_read_isr(const struct sih *sih)
542{
543 int status;
544 union {
545 u8 bytes[4];
546 u32 word;
547 } isr;
548
549 /* FIXME need retry-on-error ... */
550
551 isr.word = 0;
552 status = twl4030_i2c_read(sih->module, isr.bytes,
553 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
554
555 return (status < 0) ? status : le32_to_cpu(isr.word);
556}
557
558/*
559 * Generic handler for SIH interrupts ... we "know" this is called
560 * in task context, with IRQs enabled.
561 */
562static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
563{
564 struct sih_agent *agent = get_irq_data(irq);
565 const struct sih *sih = agent->sih;
566 int isr;
567
568 /* reading ISR acks the IRQs, using clear-on-read mode */
569 local_irq_enable();
570 isr = sih_read_isr(sih);
571 local_irq_disable();
572
573 if (isr < 0) {
574 pr_err("twl4030: %s SIH, read ISR error %d\n",
575 sih->name, isr);
576 /* REVISIT: recover; eventually mask it all, etc */
577 return;
578 }
579
580 while (isr) {
581 irq = fls(isr);
582 irq--;
583 isr &= ~BIT(irq);
584
585 if (irq < sih->bits)
586 generic_handle_irq(agent->irq_base + irq);
587 else
588 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
589 sih->name, irq);
590 }
591}
592
593static unsigned twl4030_irq_next;
594
595/* returns the first IRQ used by this SIH bank,
596 * or negative errno
597 */
598int twl4030_sih_setup(int module)
599{
600 int sih_mod;
601 const struct sih *sih = NULL;
602 struct sih_agent *agent;
603 int i, irq;
604 int status = -EINVAL;
605 unsigned irq_base = twl4030_irq_next;
606
607 /* only support modules with standard clear-on-read for now */
608 for (sih_mod = 0, sih = sih_modules;
609 sih_mod < ARRAY_SIZE(sih_modules);
610 sih_mod++, sih++) {
611 if (sih->module == module && sih->set_cor) {
612 if (!WARN((irq_base + sih->bits) > NR_IRQS,
613 "irq %d for %s too big\n",
614 irq_base + sih->bits,
615 sih->name))
616 status = 0;
617 break;
618 }
619 }
620 if (status < 0)
621 return status;
622
623 agent = kzalloc(sizeof *agent, GFP_KERNEL);
624 if (!agent)
625 return -ENOMEM;
626
627 status = 0;
628
629 agent->irq_base = irq_base;
630 agent->sih = sih;
631 agent->imr = ~0;
632 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask);
633 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge);
634
635 for (i = 0; i < sih->bits; i++) {
636 irq = irq_base + i;
637
638 set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip,
639 handle_edge_irq);
640 set_irq_chip_data(irq, agent);
641 activate_irq(irq);
642 }
643
644 status = irq_base;
645 twl4030_irq_next += i;
646
647 /* replace generic PIH handler (handle_simple_irq) */
648 irq = sih_mod + twl4030_irq_base;
649 set_irq_data(irq, agent);
650 set_irq_chained_handler(irq, handle_twl4030_sih);
651
652 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
653 irq, irq_base, twl4030_irq_next - 1);
654
655 return status;
656}
657
658/* FIXME need a call to reverse twl4030_sih_setup() ... */
659
660
661/*----------------------------------------------------------------------*/
662
663/* FIXME pass in which interrupt line we'll use ... */
664#define twl_irq_line 0
665
666int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
667{
668 static struct irq_chip twl4030_irq_chip;
669
670 int status;
671 int i;
672 struct task_struct *task;
673
674 /*
675 * Mask and clear all TWL4030 interrupts since initially we do
676 * not have any TWL4030 module interrupt handlers present
677 */
678 status = twl4030_init_sih_modules(twl_irq_line);
679 if (status < 0)
680 return status;
681
682 wq = create_singlethread_workqueue("twl4030-irqchip");
683 if (!wq) {
684 pr_err("twl4030: workqueue FAIL\n");
685 return -ESRCH;
686 }
687
688 twl4030_irq_base = irq_base;
689
690 /* install an irq handler for each of the SIH modules;
691 * clone dummy irq_chip since PIH can't *do* anything
692 */
693 twl4030_irq_chip = dummy_irq_chip;
694 twl4030_irq_chip.name = "twl4030";
695
696 twl4030_sih_irq_chip.ack = dummy_irq_chip.ack;
697
698 for (i = irq_base; i < irq_end; i++) {
699 set_irq_chip_and_handler(i, &twl4030_irq_chip,
700 handle_simple_irq);
701 activate_irq(i);
702 }
703 twl4030_irq_next = i;
704 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
705 irq_num, irq_base, twl4030_irq_next - 1);
706
707 /* ... and the PWR_INT module ... */
708 status = twl4030_sih_setup(TWL4030_MODULE_INT);
709 if (status < 0) {
710 pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
711 goto fail;
712 }
713
714 /* install an irq handler to demultiplex the TWL4030 interrupt */
715 task = start_twl4030_irq_thread(irq_num);
716 if (!task) {
717 pr_err("twl4030: irq thread FAIL\n");
718 status = -ESRCH;
719 goto fail;
720 }
721
722 set_irq_data(irq_num, task);
723 set_irq_chained_handler(irq_num, handle_twl4030_pih);
724
725 return status;
726
727fail:
728 for (i = irq_base; i < irq_end; i++)
729 set_irq_chip_and_handler(i, NULL, NULL);
730 destroy_workqueue(wq);
731 wq = NULL;
732 return status;
733}
734
735int twl_exit_irq(void)
736{
737 /* FIXME undo twl_init_irq() */
738 if (twl4030_irq_base) {
739 pr_err("twl4030: can't yet clean up IRQs?\n");
740 return -ENOSYS;
741 }
742 return 0;
743}