Rudolf Marek | d58ee05 | 2007-05-08 17:22:02 +0200 | [diff] [blame] | 1 | Kernel driver coretemp |
| 2 | ====================== |
| 3 | |
| 4 | Supported chips: |
| 5 | * All Intel Core family |
| 6 | Prefix: 'coretemp' |
Rudolf Marek | eccfed4 | 2009-09-23 22:59:42 +0200 | [diff] [blame] | 7 | CPUID: family 0x6, models 0xe (Pentium M DC), 0xf (Core 2 DC 65nm), |
| 8 | 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm), |
Huaxu Wan | fa08acd | 2009-09-23 22:59:43 +0200 | [diff] [blame] | 9 | 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield) |
Rudolf Marek | d58ee05 | 2007-05-08 17:22:02 +0200 | [diff] [blame] | 10 | Datasheet: Intel 64 and IA-32 Architectures Software Developer's Manual |
| 11 | Volume 3A: System Programming Guide |
Rudolf Marek | ae77015 | 2008-01-18 00:50:04 +0100 | [diff] [blame] | 12 | http://softwarecommunity.intel.com/Wiki/Mobility/720.htm |
Rudolf Marek | d58ee05 | 2007-05-08 17:22:02 +0200 | [diff] [blame] | 13 | |
| 14 | Author: Rudolf Marek |
| 15 | |
| 16 | Description |
| 17 | ----------- |
Durgadoss R | 199e0de | 2011-05-20 01:29:35 +0530 | [diff] [blame] | 18 | This driver permits reading the DTS (Digital Temperature Sensor) embedded |
| 19 | inside Intel CPUs. This driver can read both the per-core and per-package |
| 20 | temperature using the appropriate sensors. The per-package sensor is new; |
| 21 | as of now, it is present only in the SandyBridge platform. The driver will |
| 22 | show the temperature of all cores inside a package under a single device |
| 23 | directory inside hwmon. |
Rudolf Marek | d58ee05 | 2007-05-08 17:22:02 +0200 | [diff] [blame] | 24 | |
Rudolf Marek | d58ee05 | 2007-05-08 17:22:02 +0200 | [diff] [blame] | 25 | Temperature is measured in degrees Celsius and measurement resolution is |
| 26 | 1 degree C. Valid temperatures are from 0 to TjMax degrees C, because |
| 27 | the actual value of temperature register is in fact a delta from TjMax. |
| 28 | |
Chen Gong | f3cffe4 | 2010-08-09 17:21:10 -0700 | [diff] [blame] | 29 | Temperature known as TjMax is the maximum junction temperature of processor, |
| 30 | which depends on the CPU model. See table below. At this temperature, protection |
Rudolf Marek | d58ee05 | 2007-05-08 17:22:02 +0200 | [diff] [blame] | 31 | mechanism will perform actions to forcibly cool down the processor. Alarm |
| 32 | may be raised, if the temperature grows enough (more than TjMax) to trigger |
| 33 | the Out-Of-Spec bit. Following table summarizes the exported sysfs files: |
| 34 | |
Durgadoss R | 199e0de | 2011-05-20 01:29:35 +0530 | [diff] [blame] | 35 | All Sysfs entries are named with their core_id (represented here by 'X'). |
| 36 | tempX_input - Core temperature (in millidegrees Celsius). |
| 37 | tempX_max - All cooling devices should be turned on (on Core2). |
Durgadoss R | c814a4c | 2011-07-12 07:07:16 -0400 | [diff] [blame] | 38 | Initialized with IA32_THERM_INTERRUPT. When the CPU |
| 39 | temperature reaches this temperature, an interrupt is |
| 40 | generated and tempX_max_alarm is set. |
| 41 | tempX_max_hyst - If the CPU temperature falls below than temperature, |
| 42 | an interrupt is generated and tempX_max_alarm is reset. |
| 43 | tempX_max_alarm - Set if the temperature reaches or exceeds tempX_max. |
| 44 | Reset if the temperature drops to or below tempX_max_hyst. |
Durgadoss R | 199e0de | 2011-05-20 01:29:35 +0530 | [diff] [blame] | 45 | tempX_crit - Maximum junction temperature (in millidegrees Celsius). |
| 46 | tempX_crit_alarm - Set when Out-of-spec bit is set, never clears. |
Rudolf Marek | d58ee05 | 2007-05-08 17:22:02 +0200 | [diff] [blame] | 47 | Correct CPU operation is no longer guaranteed. |
Durgadoss R | 199e0de | 2011-05-20 01:29:35 +0530 | [diff] [blame] | 48 | tempX_label - Contains string "Core X", where X is processor |
| 49 | number. For Package temp, this will be "Physical id Y", |
| 50 | where Y is the package number. |
Rudolf Marek | d58ee05 | 2007-05-08 17:22:02 +0200 | [diff] [blame] | 51 | |
Jean Delvare | a45a8c8 | 2011-09-16 21:24:02 +0200 | [diff] [blame^] | 52 | On CPU models which support it, TjMax is read from a model-specific register. |
| 53 | On other models, it is set to an arbitrary value based on weak heuristics. |
| 54 | If these heuristics don't work for you, you can pass the correct TjMax value |
| 55 | as a module parameter (tjmax). |
Chen Gong | f3cffe4 | 2010-08-09 17:21:10 -0700 | [diff] [blame] | 56 | |
| 57 | Appendix A. Known TjMax lists (TBD): |
| 58 | Some information comes from ark.intel.com |
| 59 | |
| 60 | Process Processor TjMax(C) |
| 61 | |
| 62 | 32nm Core i3/i5/i7 Processors |
| 63 | i7 660UM/640/620, 640LM/620, 620M, 610E 105 |
| 64 | i5 540UM/520/430, 540M/520/450/430 105 |
| 65 | i3 330E, 370M/350/330 90 rPGA, 105 BGA |
| 66 | i3 330UM 105 |
| 67 | |
| 68 | 32nm Core i7 Extreme Processors |
| 69 | 980X 100 |
| 70 | |
| 71 | 32nm Celeron Processors |
| 72 | U3400 105 |
| 73 | P4505/P4500 90 |
| 74 | |
| 75 | 45nm Xeon Processors 5400 Quad-Core |
| 76 | X5492, X5482, X5472, X5470, X5460, X5450 85 |
| 77 | E5472, E5462, E5450/40/30/20/10/05 85 |
| 78 | L5408 95 |
| 79 | L5430, L5420, L5410 70 |
| 80 | |
| 81 | 45nm Xeon Processors 5200 Dual-Core |
| 82 | X5282, X5272, X5270, X5260 90 |
| 83 | E5240 90 |
| 84 | E5205, E5220 70, 90 |
| 85 | L5240 70 |
| 86 | L5238, L5215 95 |
| 87 | |
| 88 | 45nm Atom Processors |
| 89 | D525/510/425/410 100 |
| 90 | Z560/550/540/530P/530/520PT/520/515/510PT/510P 90 |
| 91 | Z510/500 90 |
| 92 | N475/470/455/450 100 |
| 93 | N280/270 90 |
| 94 | 330/230 125 |
| 95 | |
| 96 | 45nm Core2 Processors |
| 97 | Solo ULV SU3500/3300 100 |
| 98 | T9900/9800/9600/9550/9500/9400/9300/8300/8100 105 |
| 99 | T6670/6500/6400 105 |
| 100 | T6600 90 |
| 101 | SU9600/9400/9300 105 |
| 102 | SP9600/9400 105 |
| 103 | SL9600/9400/9380/9300 105 |
| 104 | P9700/9600/9500/8800/8700/8600/8400/7570 105 |
| 105 | P7550/7450 90 |
| 106 | |
| 107 | 45nm Core2 Quad Processors |
| 108 | Q9100/9000 100 |
| 109 | |
| 110 | 45nm Core2 Extreme Processors |
| 111 | X9100/9000 105 |
| 112 | QX9300 100 |
| 113 | |
| 114 | 45nm Core i3/i5/i7 Processors |
| 115 | i7 940XM/920 100 |
| 116 | i7 840QM/820/740/720 100 |
| 117 | |
| 118 | 45nm Celeron Processors |
| 119 | SU2300 100 |
| 120 | 900 105 |
| 121 | |
| 122 | 65nm Core2 Duo Processors |
| 123 | Solo U2200, U2100 100 |
| 124 | U7700/7600/7500 100 |
| 125 | T7800/7700/7600/7500/7400/7300/7250/7200/7100 100 |
| 126 | T5870/5670/5600/5550/5500/5470/5450/5300/5270 100 |
| 127 | T5250 100 |
| 128 | T5800/5750/5200 85 |
| 129 | L7700/7500/7400/7300/7200 100 |
| 130 | |
| 131 | 65nm Core2 Extreme Processors |
| 132 | X7900/7800 100 |
| 133 | |
| 134 | 65nm Core Duo Processors |
| 135 | U2500/2400 100 |
| 136 | T2700/2600/2450/2400/2350/2300E/2300/2250/2050 100 |
| 137 | L2500/2400/2300 100 |
| 138 | |
| 139 | 65nm Core Solo Processors |
| 140 | U1500/1400/1300 100 |
| 141 | T1400/1350/1300/1250 100 |
| 142 | |
| 143 | 65nm Xeon Processors 5000 Quad-Core |
| 144 | X5000 90-95 |
| 145 | E5000 80 |
| 146 | L5000 70 |
| 147 | L5318 95 |
| 148 | |
| 149 | 65nm Xeon Processors 5000 Dual-Core |
| 150 | 5080, 5063, 5060, 5050, 5030 80-90 |
| 151 | 5160, 5150, 5148, 5140, 5130, 5120, 5110 80 |
| 152 | L5138 100 |
| 153 | |
| 154 | 65nm Celeron Processors |
| 155 | T1700/1600 100 |
| 156 | 560/550/540/530 100 |