| Ralf Baechle | 38b18f7 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 1 | config SIBYTE_SB1250 |
| 2 | bool |
| 3 | select HW_HAS_PCI |
| 4 | select SIBYTE_HAS_LDT |
| 5 | select SIBYTE_SB1xxx_SOC |
| 6 | |
| 7 | config SIBYTE_BCM1120 |
| 8 | bool |
| 9 | select SIBYTE_BCM112X |
| 10 | select SIBYTE_SB1xxx_SOC |
| 11 | |
| 12 | config SIBYTE_BCM1125 |
| 13 | bool |
| 14 | select HW_HAS_PCI |
| 15 | select SIBYTE_BCM112X |
| 16 | select SIBYTE_SB1xxx_SOC |
| 17 | |
| 18 | config SIBYTE_BCM1125H |
| 19 | bool |
| 20 | select HW_HAS_PCI |
| 21 | select SIBYTE_BCM112X |
| 22 | select SIBYTE_HAS_LDT |
| 23 | select SIBYTE_SB1xxx_SOC |
| 24 | |
| 25 | config SIBYTE_BCM112X |
| 26 | bool |
| 27 | select SIBYTE_SB1xxx_SOC |
| 28 | |
| Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 29 | config SIBYTE_BCM1x80 |
| 30 | bool |
| 31 | select HW_HAS_PCI |
| 32 | select SIBYTE_SB1xxx_SOC |
| 33 | |
| 34 | config SIBYTE_BCM1x55 |
| 35 | bool |
| 36 | select HW_HAS_PCI |
| 37 | select SIBYTE_SB1xxx_SOC |
| 38 | |
| Ralf Baechle | 38b18f7 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 39 | config SIBYTE_SB1xxx_SOC |
| 40 | bool |
| 41 | depends on EXPERIMENTAL |
| 42 | select DMA_COHERENT |
| 43 | select SIBYTE_CFE |
| 44 | select SWAP_IO_SPACE |
| 45 | select SYS_SUPPORTS_32BIT_KERNEL |
| 46 | select SYS_SUPPORTS_64BIT_KERNEL |
| 47 | |
| 48 | choice |
| 49 | prompt "SiByte SOC Stepping" |
| 50 | depends on SIBYTE_SB1xxx_SOC |
| 51 | |
| 52 | config CPU_SB1_PASS_1 |
| 53 | bool "1250 Pass1" |
| 54 | depends on SIBYTE_SB1250 |
| 55 | select CPU_HAS_PREFETCH |
| 56 | |
| 57 | config CPU_SB1_PASS_2_1250 |
| 58 | bool "1250 An" |
| 59 | depends on SIBYTE_SB1250 |
| 60 | select CPU_SB1_PASS_2 |
| 61 | help |
| 62 | Also called BCM1250 Pass 2 |
| 63 | |
| 64 | config CPU_SB1_PASS_2_2 |
| 65 | bool "1250 Bn" |
| 66 | depends on SIBYTE_SB1250 |
| 67 | select CPU_HAS_PREFETCH |
| 68 | help |
| 69 | Also called BCM1250 Pass 2.2 |
| 70 | |
| 71 | config CPU_SB1_PASS_4 |
| 72 | bool "1250 Cn" |
| 73 | depends on SIBYTE_SB1250 |
| 74 | select CPU_HAS_PREFETCH |
| 75 | help |
| 76 | Also called BCM1250 Pass 3 |
| 77 | |
| 78 | config CPU_SB1_PASS_2_112x |
| 79 | bool "112x Hybrid" |
| 80 | depends on SIBYTE_BCM112X |
| 81 | select CPU_SB1_PASS_2 |
| 82 | |
| 83 | config CPU_SB1_PASS_3 |
| 84 | bool "112x An" |
| 85 | depends on SIBYTE_BCM112X |
| 86 | select CPU_HAS_PREFETCH |
| 87 | |
| 88 | endchoice |
| 89 | |
| 90 | config CPU_SB1_PASS_2 |
| 91 | bool |
| 92 | |
| 93 | config SIBYTE_HAS_LDT |
| 94 | bool |
| 95 | depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H) |
| 96 | default y |
| 97 | |
| 98 | config SIMULATION |
| 99 | bool "Running under simulation" |
| 100 | depends on SIBYTE_SB1xxx_SOC |
| 101 | help |
| 102 | Build a kernel suitable for running under the GDB simulator. |
| 103 | Primarily adjusts the kernel's notion of time. |
| 104 | |
| Andrew Isaacson | a4b5bd9 | 2005-10-19 23:57:40 -0700 | [diff] [blame^] | 105 | config CONFIG_SB1_CEX_ALWAYS_FATAL |
| 106 | bool "All cache exceptions considered fatal (no recovery attempted)" |
| 107 | depends on SIBYTE_SB1xxx_SOC |
| 108 | |
| 109 | config CONFIG_SB1_CERR_STALL |
| 110 | bool "Stall (rather than panic) on fatal cache error" |
| 111 | depends on SIBYTE_SB1xxx_SOC |
| 112 | |
| Ralf Baechle | 38b18f7 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 113 | config SIBYTE_CFE |
| 114 | bool "Booting from CFE" |
| 115 | depends on SIBYTE_SB1xxx_SOC |
| 116 | help |
| 117 | Make use of the CFE API for enumerating available memory, |
| 118 | controlling secondary CPUs, and possibly console output. |
| 119 | |
| 120 | config SIBYTE_CFE_CONSOLE |
| 121 | bool "Use firmware console" |
| 122 | depends on SIBYTE_CFE |
| 123 | help |
| 124 | Use the CFE API's console write routines during boot. Other console |
| 125 | options (VT console, sb1250 duart console, etc.) should not be |
| 126 | configured. |
| 127 | |
| 128 | config SIBYTE_STANDALONE |
| 129 | bool |
| 130 | depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE |
| 131 | default y |
| 132 | |
| 133 | config SIBYTE_STANDALONE_RAM_SIZE |
| 134 | int "Memory size (in megabytes)" |
| 135 | depends on SIBYTE_STANDALONE |
| 136 | default "32" |
| 137 | |
| 138 | config SIBYTE_BUS_WATCHER |
| 139 | bool "Support for Bus Watcher statistics" |
| 140 | depends on SIBYTE_SB1xxx_SOC |
| 141 | help |
| 142 | Handle and keep statistics on the bus error interrupts (COR_ECC, |
| 143 | BAD_ECC, IO_BUS). |
| 144 | |
| 145 | config SIBYTE_BW_TRACE |
| 146 | bool "Capture bus trace before bus error" |
| 147 | depends on SIBYTE_BUS_WATCHER |
| 148 | help |
| 149 | Run a continuous bus trace, dumping the raw data as soon as |
| 150 | a ZBbus error is detected. Cannot work if ZBbus profiling |
| 151 | is turned on, and also will interfere with JTAG-based trace |
| 152 | buffer activity. Raw buffer data is dumped to console, and |
| 153 | must be processed off-line. |
| 154 | |
| 155 | config SIBYTE_SB1250_PROF |
| 156 | bool "Support for SB1/SOC profiling - SB1/SCD perf counters" |
| 157 | depends on SIBYTE_SB1xxx_SOC |
| 158 | |
| 159 | config SIBYTE_TBPROF |
| 160 | bool "Support for ZBbus profiling" |
| 161 | depends on SIBYTE_SB1xxx_SOC |