Muralidharan Karicheri | 7b140b8 | 2009-06-19 09:20:16 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Texas Instruments. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 17 | * |
| 18 | * common vpss driver for all video drivers. |
| 19 | */ |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/sched.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/spinlock.h> |
| 26 | #include <linux/compiler.h> |
| 27 | #include <linux/io.h> |
| 28 | #include <mach/hardware.h> |
| 29 | #include <media/davinci/vpss.h> |
| 30 | |
| 31 | MODULE_LICENSE("GPL"); |
| 32 | MODULE_DESCRIPTION("VPSS Driver"); |
| 33 | MODULE_AUTHOR("Texas Instruments"); |
| 34 | |
| 35 | /* DM644x defines */ |
| 36 | #define DM644X_SBL_PCR_VPSS (4) |
| 37 | |
| 38 | /* vpss BL register offsets */ |
| 39 | #define DM355_VPSSBL_CCDCMUX 0x1c |
| 40 | /* vpss CLK register offsets */ |
| 41 | #define DM355_VPSSCLK_CLKCTRL 0x04 |
| 42 | /* masks and shifts */ |
| 43 | #define VPSS_HSSISEL_SHIFT 4 |
| 44 | |
| 45 | /* |
| 46 | * vpss operations. Depends on platform. Not all functions are available |
| 47 | * on all platforms. The api, first check if a functio is available before |
| 48 | * invoking it. In the probe, the function ptrs are intialized based on |
| 49 | * vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc. |
| 50 | */ |
| 51 | struct vpss_hw_ops { |
| 52 | /* enable clock */ |
| 53 | int (*enable_clock)(enum vpss_clock_sel clock_sel, int en); |
| 54 | /* select input to ccdc */ |
| 55 | void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel); |
| 56 | /* clear wbl overlflow bit */ |
| 57 | int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel); |
| 58 | }; |
| 59 | |
| 60 | /* vpss configuration */ |
| 61 | struct vpss_oper_config { |
| 62 | __iomem void *vpss_bl_regs_base; |
| 63 | __iomem void *vpss_regs_base; |
| 64 | struct resource *r1; |
| 65 | resource_size_t len1; |
| 66 | struct resource *r2; |
| 67 | resource_size_t len2; |
| 68 | char vpss_name[32]; |
| 69 | spinlock_t vpss_lock; |
| 70 | struct vpss_hw_ops hw_ops; |
| 71 | }; |
| 72 | |
| 73 | static struct vpss_oper_config oper_cfg; |
| 74 | |
| 75 | /* register access routines */ |
| 76 | static inline u32 bl_regr(u32 offset) |
| 77 | { |
| 78 | return __raw_readl(oper_cfg.vpss_bl_regs_base + offset); |
| 79 | } |
| 80 | |
| 81 | static inline void bl_regw(u32 val, u32 offset) |
| 82 | { |
| 83 | __raw_writel(val, oper_cfg.vpss_bl_regs_base + offset); |
| 84 | } |
| 85 | |
| 86 | static inline u32 vpss_regr(u32 offset) |
| 87 | { |
| 88 | return __raw_readl(oper_cfg.vpss_regs_base + offset); |
| 89 | } |
| 90 | |
| 91 | static inline void vpss_regw(u32 val, u32 offset) |
| 92 | { |
| 93 | __raw_writel(val, oper_cfg.vpss_regs_base + offset); |
| 94 | } |
| 95 | |
| 96 | static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel) |
| 97 | { |
| 98 | bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX); |
| 99 | } |
| 100 | |
| 101 | int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel) |
| 102 | { |
| 103 | if (!oper_cfg.hw_ops.select_ccdc_source) |
| 104 | return -1; |
| 105 | |
| 106 | dm355_select_ccdc_source(src_sel); |
| 107 | return 0; |
| 108 | } |
| 109 | EXPORT_SYMBOL(vpss_select_ccdc_source); |
| 110 | |
| 111 | static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel) |
| 112 | { |
| 113 | u32 mask = 1, val; |
| 114 | |
| 115 | if (wbl_sel < VPSS_PCR_AEW_WBL_0 || |
| 116 | wbl_sel > VPSS_PCR_CCDC_WBL_O) |
| 117 | return -1; |
| 118 | |
| 119 | /* writing a 0 clear the overflow */ |
| 120 | mask = ~(mask << wbl_sel); |
| 121 | val = bl_regr(DM644X_SBL_PCR_VPSS) & mask; |
| 122 | bl_regw(val, DM644X_SBL_PCR_VPSS); |
| 123 | return 0; |
| 124 | } |
| 125 | |
| 126 | int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel) |
| 127 | { |
| 128 | if (!oper_cfg.hw_ops.clear_wbl_overflow) |
| 129 | return -1; |
| 130 | |
| 131 | return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel); |
| 132 | } |
| 133 | EXPORT_SYMBOL(vpss_clear_wbl_overflow); |
| 134 | |
| 135 | /* |
| 136 | * dm355_enable_clock - Enable VPSS Clock |
| 137 | * @clock_sel: CLock to be enabled/disabled |
| 138 | * @en: enable/disable flag |
| 139 | * |
| 140 | * This is called to enable or disable a vpss clock |
| 141 | */ |
| 142 | static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en) |
| 143 | { |
| 144 | unsigned long flags; |
| 145 | u32 utemp, mask = 0x1, shift = 0; |
| 146 | |
| 147 | switch (clock_sel) { |
| 148 | case VPSS_VPBE_CLOCK: |
| 149 | /* nothing since lsb */ |
| 150 | break; |
| 151 | case VPSS_VENC_CLOCK_SEL: |
| 152 | shift = 2; |
| 153 | break; |
| 154 | case VPSS_CFALD_CLOCK: |
| 155 | shift = 3; |
| 156 | break; |
| 157 | case VPSS_H3A_CLOCK: |
| 158 | shift = 4; |
| 159 | break; |
| 160 | case VPSS_IPIPE_CLOCK: |
| 161 | shift = 5; |
| 162 | break; |
| 163 | case VPSS_CCDC_CLOCK: |
| 164 | shift = 6; |
| 165 | break; |
| 166 | default: |
| 167 | printk(KERN_ERR "dm355_enable_clock:" |
| 168 | " Invalid selector: %d\n", clock_sel); |
| 169 | return -1; |
| 170 | } |
| 171 | |
| 172 | spin_lock_irqsave(&oper_cfg.vpss_lock, flags); |
| 173 | utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL); |
| 174 | if (!en) |
| 175 | utemp &= ~(mask << shift); |
| 176 | else |
| 177 | utemp |= (mask << shift); |
| 178 | |
| 179 | vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL); |
| 180 | spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags); |
| 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en) |
| 185 | { |
| 186 | if (!oper_cfg.hw_ops.enable_clock) |
| 187 | return -1; |
| 188 | |
| 189 | return oper_cfg.hw_ops.enable_clock(clock_sel, en); |
| 190 | } |
| 191 | EXPORT_SYMBOL(vpss_enable_clock); |
| 192 | |
| 193 | static int __init vpss_probe(struct platform_device *pdev) |
| 194 | { |
| 195 | int status, dm355 = 0; |
| 196 | |
| 197 | if (!pdev->dev.platform_data) { |
| 198 | dev_err(&pdev->dev, "no platform data\n"); |
| 199 | return -ENOENT; |
| 200 | } |
| 201 | strcpy(oper_cfg.vpss_name, pdev->dev.platform_data); |
| 202 | |
| 203 | if (!strcmp(oper_cfg.vpss_name, "dm355_vpss")) |
| 204 | dm355 = 1; |
| 205 | else if (strcmp(oper_cfg.vpss_name, "dm644x_vpss")) { |
| 206 | dev_err(&pdev->dev, "vpss driver not supported on" |
| 207 | " this platform\n"); |
| 208 | return -ENODEV; |
| 209 | } |
| 210 | |
| 211 | dev_info(&pdev->dev, "%s vpss probed\n", oper_cfg.vpss_name); |
| 212 | oper_cfg.r1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 213 | if (!oper_cfg.r1) |
| 214 | return -ENOENT; |
| 215 | |
| 216 | oper_cfg.len1 = oper_cfg.r1->end - oper_cfg.r1->start + 1; |
| 217 | |
| 218 | oper_cfg.r1 = request_mem_region(oper_cfg.r1->start, oper_cfg.len1, |
| 219 | oper_cfg.r1->name); |
| 220 | if (!oper_cfg.r1) |
| 221 | return -EBUSY; |
| 222 | |
| 223 | oper_cfg.vpss_bl_regs_base = ioremap(oper_cfg.r1->start, oper_cfg.len1); |
| 224 | if (!oper_cfg.vpss_bl_regs_base) { |
| 225 | status = -EBUSY; |
| 226 | goto fail1; |
| 227 | } |
| 228 | |
| 229 | if (dm355) { |
| 230 | oper_cfg.r2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 231 | if (!oper_cfg.r2) { |
| 232 | status = -ENOENT; |
| 233 | goto fail2; |
| 234 | } |
| 235 | oper_cfg.len2 = oper_cfg.r2->end - oper_cfg.r2->start + 1; |
| 236 | oper_cfg.r2 = request_mem_region(oper_cfg.r2->start, |
| 237 | oper_cfg.len2, |
| 238 | oper_cfg.r2->name); |
| 239 | if (!oper_cfg.r2) { |
| 240 | status = -EBUSY; |
| 241 | goto fail2; |
| 242 | } |
| 243 | |
| 244 | oper_cfg.vpss_regs_base = ioremap(oper_cfg.r2->start, |
| 245 | oper_cfg.len2); |
| 246 | if (!oper_cfg.vpss_regs_base) { |
| 247 | status = -EBUSY; |
| 248 | goto fail3; |
| 249 | } |
| 250 | } |
| 251 | |
| 252 | if (dm355) { |
| 253 | oper_cfg.hw_ops.enable_clock = dm355_enable_clock; |
| 254 | oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source; |
| 255 | } else |
| 256 | oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow; |
| 257 | |
| 258 | spin_lock_init(&oper_cfg.vpss_lock); |
| 259 | dev_info(&pdev->dev, "%s vpss probe success\n", oper_cfg.vpss_name); |
| 260 | return 0; |
| 261 | |
| 262 | fail3: |
| 263 | release_mem_region(oper_cfg.r2->start, oper_cfg.len2); |
| 264 | fail2: |
| 265 | iounmap(oper_cfg.vpss_bl_regs_base); |
| 266 | fail1: |
| 267 | release_mem_region(oper_cfg.r1->start, oper_cfg.len1); |
| 268 | return status; |
| 269 | } |
| 270 | |
| 271 | static int vpss_remove(struct platform_device *pdev) |
| 272 | { |
| 273 | iounmap(oper_cfg.vpss_bl_regs_base); |
| 274 | release_mem_region(oper_cfg.r1->start, oper_cfg.len1); |
| 275 | if (!strcmp(oper_cfg.vpss_name, "dm355_vpss")) { |
| 276 | iounmap(oper_cfg.vpss_regs_base); |
| 277 | release_mem_region(oper_cfg.r2->start, oper_cfg.len2); |
| 278 | } |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static struct platform_driver vpss_driver = { |
| 283 | .driver = { |
| 284 | .name = "vpss", |
| 285 | .owner = THIS_MODULE, |
| 286 | }, |
| 287 | .remove = __devexit_p(vpss_remove), |
| 288 | .probe = vpss_probe, |
| 289 | }; |
| 290 | |
| 291 | static void vpss_exit(void) |
| 292 | { |
| 293 | platform_driver_unregister(&vpss_driver); |
| 294 | } |
| 295 | |
| 296 | static int __init vpss_init(void) |
| 297 | { |
| 298 | return platform_driver_register(&vpss_driver); |
| 299 | } |
| 300 | subsys_initcall(vpss_init); |
| 301 | module_exit(vpss_exit); |