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Kumar Gala10b35d92005-09-23 14:08:58 -05001#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#include <linux/config.h>
David Gibson3ddfbcf2005-11-10 12:56:55 +11005#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -05006
7#define PPC_FEATURE_32 0x80000000
8#define PPC_FEATURE_64 0x40000000
9#define PPC_FEATURE_601_INSTR 0x20000000
10#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
11#define PPC_FEATURE_HAS_FPU 0x08000000
12#define PPC_FEATURE_HAS_MMU 0x04000000
13#define PPC_FEATURE_HAS_4xxMAC 0x02000000
14#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
15#define PPC_FEATURE_HAS_SPE 0x00800000
16#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
17#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +100018#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +110019#define PPC_FEATURE_POWER4 0x00080000
20#define PPC_FEATURE_POWER5 0x00040000
21#define PPC_FEATURE_POWER5_PLUS 0x00020000
22#define PPC_FEATURE_CELL 0x00010000
Kumar Gala10b35d92005-09-23 14:08:58 -050023
24#ifdef __KERNEL__
25#ifndef __ASSEMBLY__
26
27/* This structure can grow, it's real size is used by head.S code
28 * via the mkdefs mechanism.
29 */
30struct cpu_spec;
31struct op_powerpc_model;
32
Kumar Gala10b35d92005-09-23 14:08:58 -050033typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Kumar Gala10b35d92005-09-23 14:08:58 -050034
35struct cpu_spec {
36 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
37 unsigned int pvr_mask;
38 unsigned int pvr_value;
39
40 char *cpu_name;
41 unsigned long cpu_features; /* Kernel features */
42 unsigned int cpu_user_features; /* Userland features */
43
44 /* cache line sizes */
45 unsigned int icache_bsize;
46 unsigned int dcache_bsize;
47
48 /* number of performance monitor counters */
49 unsigned int num_pmcs;
50
51 /* this is called to initialize various CPU bits like L1 cache,
52 * BHT, SPD, etc... from head.S before branching to identify_machine
53 */
54 cpu_setup_t cpu_setup;
Kumar Gala10b35d92005-09-23 14:08:58 -050055
56 /* Used by oprofile userspace to select the right counters */
57 char *oprofile_cpu_type;
58
59 /* Processor specific oprofile operations */
60 struct op_powerpc_model *oprofile_model;
Kumar Gala10b35d92005-09-23 14:08:58 -050061};
62
Kumar Gala10b35d92005-09-23 14:08:58 -050063extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -050064
Paul Mackerras9b6b5632005-10-06 12:06:20 +100065extern void identify_cpu(unsigned long offset, unsigned long cpu);
66extern void do_cpu_ftr_fixups(unsigned long offset);
67
Kumar Gala10b35d92005-09-23 14:08:58 -050068#endif /* __ASSEMBLY__ */
69
70/* CPU kernel features */
71
72/* Retain the 32b definitions all use bottom half of word */
73#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
74#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
75#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
76#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
77#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
78#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
79#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
80#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
81#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
82#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
83#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
84#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
85#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
86#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
87#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
88#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
89#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
90#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
91#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
92#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
93
94#ifdef __powerpc64__
95/* Add the 64b processor unique features in the top half of the word */
96#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
97#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
98#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
99#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
100#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
101#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
102#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
103#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
104#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
105#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
106#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
107#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100108#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500109#else
110/* ensure on 32b processors the flags are available for compiling but
111 * don't do anything */
112#define CPU_FTR_SLB ASM_CONST(0x0)
113#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
114#define CPU_FTR_TLBIEL ASM_CONST(0x0)
115#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
116#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0)
117#define CPU_FTR_IABR ASM_CONST(0x0)
118#define CPU_FTR_MMCRA ASM_CONST(0x0)
119#define CPU_FTR_CTRL ASM_CONST(0x0)
120#define CPU_FTR_SMT ASM_CONST(0x0)
121#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
122#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
123#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100124#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
Kumar Gala10b35d92005-09-23 14:08:58 -0500125#endif
126
127#ifndef __ASSEMBLY__
128
Kumar Gala10b35d92005-09-23 14:08:58 -0500129#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
130 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
131 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
132
133/* iSeries doesn't support large pages */
134#ifdef CONFIG_PPC_ISERIES
135#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
136#else
137#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
138#endif /* CONFIG_PPC_ISERIES */
139
140/* We only set the altivec features if the kernel was compiled with altivec
141 * support
142 */
143#ifdef CONFIG_ALTIVEC
144#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
145#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
146#else
147#define CPU_FTR_ALTIVEC_COMP 0
148#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
149#endif
150
151/* We need to mark all pages as being coherent if we're SMP or we
152 * have a 74[45]x and an MPC107 host bridge.
153 */
154#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
155#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
156#else
157#define CPU_FTR_COMMON 0
158#endif
159
160/* The powersave features NAP & DOZE seems to confuse BDI when
161 debugging. So if a BDI is used, disable theses
162 */
163#ifndef CONFIG_BDI_SWITCH
164#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
165#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
166#else
167#define CPU_FTR_MAYBE_CAN_DOZE 0
168#define CPU_FTR_MAYBE_CAN_NAP 0
169#endif
170
171#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
172 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
173 !defined(CONFIG_BOOKE))
174
175enum {
176 CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
177 CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
178 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
179 CPU_FTR_MAYBE_CAN_NAP,
180 CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
181 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
182 CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
183 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
184 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
185 CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
186 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
187 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
188 CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
189 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
190 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
191 CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
192 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
193 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
194 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
195 CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
196 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
197 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
198 CPU_FTR_NO_DPM,
199 CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
200 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
201 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
202 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
203 CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
204 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
205 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
206 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
207 CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
208 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
209 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
210 CPU_FTR_MAYBE_CAN_NAP,
211 CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
213 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
214 CPU_FTR_MAYBE_CAN_NAP,
215 CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
216 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
217 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
218 CPU_FTR_NEED_COHERENT,
219 CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
220 CPU_FTR_USE_TB |
221 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
222 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
223 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
224 CPU_FTR_NEED_COHERENT,
225 CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
226 CPU_FTR_USE_TB |
227 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
228 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
229 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
230 CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
231 CPU_FTR_USE_TB |
232 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
233 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
234 CPU_FTR_NEED_COHERENT,
235 CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
236 CPU_FTR_USE_TB |
237 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
238 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
239 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
240 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
241 CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
242 CPU_FTR_USE_TB |
243 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
244 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
245 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
246 CPU_FTR_NEED_COHERENT,
247 CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
248 CPU_FTR_USE_TB |
249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
250 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
251 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
252 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
253 CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
254 CPU_FTR_USE_TB |
255 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
256 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
257 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
258 CPU_FTR_NEED_COHERENT,
259 CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
260 CPU_FTR_USE_TB |
261 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
262 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
263 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
264 CPU_FTR_NEED_COHERENT,
265 CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
266 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
267 CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
268 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
269 CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
270 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
271 CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
272 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
273 CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
274 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
275 CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
276 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
277 CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
278 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
279 CPU_FTR_MAYBE_CAN_NAP,
280 CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
281 CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
282 CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
283 CPU_FTRS_E200 = CPU_FTR_USE_TB,
284 CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
285 CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
286 CPU_FTR_BIG_PHYS,
287 CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
288#ifdef __powerpc64__
289 CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
290 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
291 CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
292 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
293 CPU_FTR_MMCRA | CPU_FTR_CTRL,
294 CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
295 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
296 CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
297 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
298 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
299 CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
300 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
301 CPU_FTR_MMCRA | CPU_FTR_SMT |
302 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
303 CPU_FTR_MMCRA_SIHV,
304 CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
305 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
306 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
307 CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
308 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
309#endif
310
311 CPU_FTRS_POSSIBLE =
312#if CLASSIC_PPC
313 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
314 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
315 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
316 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
317 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
318 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
319 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
320 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
321#else
322 CPU_FTRS_GENERIC_32 |
323#endif
324#ifdef CONFIG_PPC64BRIDGE
325 CPU_FTRS_POWER3_32 |
326#endif
327#ifdef CONFIG_POWER4
328 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
329#endif
330#ifdef CONFIG_8xx
331 CPU_FTRS_8XX |
332#endif
333#ifdef CONFIG_40x
334 CPU_FTRS_40X |
335#endif
336#ifdef CONFIG_44x
337 CPU_FTRS_44X |
338#endif
339#ifdef CONFIG_E200
340 CPU_FTRS_E200 |
341#endif
342#ifdef CONFIG_E500
343 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
344#endif
345#ifdef __powerpc64__
346 CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
347 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100348 CPU_FTR_CI_LARGE_PAGE |
Kumar Gala10b35d92005-09-23 14:08:58 -0500349#endif
350 0,
351
352 CPU_FTRS_ALWAYS =
353#if CLASSIC_PPC
354 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
355 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
356 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
357 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
358 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
359 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
360 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
361 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
362#else
363 CPU_FTRS_GENERIC_32 &
364#endif
365#ifdef CONFIG_PPC64BRIDGE
366 CPU_FTRS_POWER3_32 &
367#endif
368#ifdef CONFIG_POWER4
369 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
370#endif
371#ifdef CONFIG_8xx
372 CPU_FTRS_8XX &
373#endif
374#ifdef CONFIG_40x
375 CPU_FTRS_40X &
376#endif
377#ifdef CONFIG_44x
378 CPU_FTRS_44X &
379#endif
380#ifdef CONFIG_E200
381 CPU_FTRS_E200 &
382#endif
383#ifdef CONFIG_E500
384 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
385#endif
386#ifdef __powerpc64__
387 CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
388 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
389#endif
390 CPU_FTRS_POSSIBLE,
391};
392
393static inline int cpu_has_feature(unsigned long feature)
394{
395 return (CPU_FTRS_ALWAYS & feature) ||
396 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500397 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500398 & feature);
399}
400
401#endif /* !__ASSEMBLY__ */
402
403#ifdef __ASSEMBLY__
404
405#define BEGIN_FTR_SECTION 98:
406
407#ifndef __powerpc64__
408#define END_FTR_SECTION(msk, val) \
40999: \
410 .section __ftr_fixup,"a"; \
411 .align 2; \
412 .long msk; \
413 .long val; \
414 .long 98b; \
415 .long 99b; \
416 .previous
417#else /* __powerpc64__ */
418#define END_FTR_SECTION(msk, val) \
41999: \
420 .section __ftr_fixup,"a"; \
421 .align 3; \
422 .llong msk; \
423 .llong val; \
424 .llong 98b; \
425 .llong 99b; \
426 .previous
427#endif /* __powerpc64__ */
428
429#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
430#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
431#endif /* __ASSEMBLY__ */
432
433#endif /* __KERNEL__ */
434#endif /* __ASM_POWERPC_CPUTABLE_H */