Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004 ATI Technologies Inc., Markham, Ontario |
| 3 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 4 | * Copyright 2008 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | */ |
| 27 | #include "drmP.h" |
| 28 | #include "radeon_drm.h" |
| 29 | #include "radeon.h" |
| 30 | #include "atom.h" |
| 31 | |
| 32 | #ifdef CONFIG_PPC_PMAC |
| 33 | /* not sure which of these are needed */ |
| 34 | #include <asm/machdep.h> |
| 35 | #include <asm/pmac_feature.h> |
| 36 | #include <asm/prom.h> |
| 37 | #include <asm/pci-bridge.h> |
| 38 | #endif /* CONFIG_PPC_PMAC */ |
| 39 | |
| 40 | /* from radeon_encoder.c */ |
| 41 | extern uint32_t |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 42 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
| 43 | uint8_t dac); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 44 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
| 45 | |
| 46 | /* from radeon_connector.c */ |
| 47 | extern void |
| 48 | radeon_add_legacy_connector(struct drm_device *dev, |
| 49 | uint32_t connector_id, |
| 50 | uint32_t supported_device, |
| 51 | int connector_type, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 52 | struct radeon_i2c_bus_rec *i2c_bus, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 53 | uint16_t connector_object_id, |
| 54 | struct radeon_hpd *hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 55 | |
| 56 | /* from radeon_legacy_encoder.c */ |
| 57 | extern void |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 58 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 59 | uint32_t supported_device); |
| 60 | |
| 61 | /* old legacy ATI BIOS routines */ |
| 62 | |
| 63 | /* COMBIOS table offsets */ |
| 64 | enum radeon_combios_table_offset { |
| 65 | /* absolute offset tables */ |
| 66 | COMBIOS_ASIC_INIT_1_TABLE, |
| 67 | COMBIOS_BIOS_SUPPORT_TABLE, |
| 68 | COMBIOS_DAC_PROGRAMMING_TABLE, |
| 69 | COMBIOS_MAX_COLOR_DEPTH_TABLE, |
| 70 | COMBIOS_CRTC_INFO_TABLE, |
| 71 | COMBIOS_PLL_INFO_TABLE, |
| 72 | COMBIOS_TV_INFO_TABLE, |
| 73 | COMBIOS_DFP_INFO_TABLE, |
| 74 | COMBIOS_HW_CONFIG_INFO_TABLE, |
| 75 | COMBIOS_MULTIMEDIA_INFO_TABLE, |
| 76 | COMBIOS_TV_STD_PATCH_TABLE, |
| 77 | COMBIOS_LCD_INFO_TABLE, |
| 78 | COMBIOS_MOBILE_INFO_TABLE, |
| 79 | COMBIOS_PLL_INIT_TABLE, |
| 80 | COMBIOS_MEM_CONFIG_TABLE, |
| 81 | COMBIOS_SAVE_MASK_TABLE, |
| 82 | COMBIOS_HARDCODED_EDID_TABLE, |
| 83 | COMBIOS_ASIC_INIT_2_TABLE, |
| 84 | COMBIOS_CONNECTOR_INFO_TABLE, |
| 85 | COMBIOS_DYN_CLK_1_TABLE, |
| 86 | COMBIOS_RESERVED_MEM_TABLE, |
| 87 | COMBIOS_EXT_TMDS_INFO_TABLE, |
| 88 | COMBIOS_MEM_CLK_INFO_TABLE, |
| 89 | COMBIOS_EXT_DAC_INFO_TABLE, |
| 90 | COMBIOS_MISC_INFO_TABLE, |
| 91 | COMBIOS_CRT_INFO_TABLE, |
| 92 | COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, |
| 93 | COMBIOS_COMPONENT_VIDEO_INFO_TABLE, |
| 94 | COMBIOS_FAN_SPEED_INFO_TABLE, |
| 95 | COMBIOS_OVERDRIVE_INFO_TABLE, |
| 96 | COMBIOS_OEM_INFO_TABLE, |
| 97 | COMBIOS_DYN_CLK_2_TABLE, |
| 98 | COMBIOS_POWER_CONNECTOR_INFO_TABLE, |
| 99 | COMBIOS_I2C_INFO_TABLE, |
| 100 | /* relative offset tables */ |
| 101 | COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ |
| 102 | COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ |
| 103 | COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ |
| 104 | COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ |
| 105 | COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ |
| 106 | COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ |
| 107 | COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ |
| 108 | COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ |
| 109 | COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ |
| 110 | COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ |
| 111 | COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ |
| 112 | }; |
| 113 | |
| 114 | enum radeon_combios_ddc { |
| 115 | DDC_NONE_DETECTED, |
| 116 | DDC_MONID, |
| 117 | DDC_DVI, |
| 118 | DDC_VGA, |
| 119 | DDC_CRT2, |
| 120 | DDC_LCD, |
| 121 | DDC_GPIO, |
| 122 | }; |
| 123 | |
| 124 | enum radeon_combios_connector { |
| 125 | CONNECTOR_NONE_LEGACY, |
| 126 | CONNECTOR_PROPRIETARY_LEGACY, |
| 127 | CONNECTOR_CRT_LEGACY, |
| 128 | CONNECTOR_DVI_I_LEGACY, |
| 129 | CONNECTOR_DVI_D_LEGACY, |
| 130 | CONNECTOR_CTV_LEGACY, |
| 131 | CONNECTOR_STV_LEGACY, |
| 132 | CONNECTOR_UNSUPPORTED_LEGACY |
| 133 | }; |
| 134 | |
| 135 | const int legacy_connector_convert[] = { |
| 136 | DRM_MODE_CONNECTOR_Unknown, |
| 137 | DRM_MODE_CONNECTOR_DVID, |
| 138 | DRM_MODE_CONNECTOR_VGA, |
| 139 | DRM_MODE_CONNECTOR_DVII, |
| 140 | DRM_MODE_CONNECTOR_DVID, |
| 141 | DRM_MODE_CONNECTOR_Composite, |
| 142 | DRM_MODE_CONNECTOR_SVIDEO, |
| 143 | DRM_MODE_CONNECTOR_Unknown, |
| 144 | }; |
| 145 | |
| 146 | static uint16_t combios_get_table_offset(struct drm_device *dev, |
| 147 | enum radeon_combios_table_offset table) |
| 148 | { |
| 149 | struct radeon_device *rdev = dev->dev_private; |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 150 | int rev, size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 151 | uint16_t offset = 0, check_offset; |
| 152 | |
Michel Dänzer | 03047cd | 2010-02-10 11:05:11 +0100 | [diff] [blame] | 153 | if (!rdev->bios) |
| 154 | return 0; |
| 155 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 156 | switch (table) { |
| 157 | /* absolute offset tables */ |
| 158 | case COMBIOS_ASIC_INIT_1_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 159 | check_offset = 0xc; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 160 | break; |
| 161 | case COMBIOS_BIOS_SUPPORT_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 162 | check_offset = 0x14; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 163 | break; |
| 164 | case COMBIOS_DAC_PROGRAMMING_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 165 | check_offset = 0x2a; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 166 | break; |
| 167 | case COMBIOS_MAX_COLOR_DEPTH_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 168 | check_offset = 0x2c; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | break; |
| 170 | case COMBIOS_CRTC_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 171 | check_offset = 0x2e; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 172 | break; |
| 173 | case COMBIOS_PLL_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 174 | check_offset = 0x30; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 175 | break; |
| 176 | case COMBIOS_TV_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 177 | check_offset = 0x32; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 178 | break; |
| 179 | case COMBIOS_DFP_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 180 | check_offset = 0x34; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | break; |
| 182 | case COMBIOS_HW_CONFIG_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 183 | check_offset = 0x36; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 184 | break; |
| 185 | case COMBIOS_MULTIMEDIA_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 186 | check_offset = 0x38; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 187 | break; |
| 188 | case COMBIOS_TV_STD_PATCH_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 189 | check_offset = 0x3e; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 190 | break; |
| 191 | case COMBIOS_LCD_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 192 | check_offset = 0x40; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 193 | break; |
| 194 | case COMBIOS_MOBILE_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 195 | check_offset = 0x42; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 196 | break; |
| 197 | case COMBIOS_PLL_INIT_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 198 | check_offset = 0x46; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 199 | break; |
| 200 | case COMBIOS_MEM_CONFIG_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 201 | check_offset = 0x48; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 202 | break; |
| 203 | case COMBIOS_SAVE_MASK_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 204 | check_offset = 0x4a; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 205 | break; |
| 206 | case COMBIOS_HARDCODED_EDID_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 207 | check_offset = 0x4c; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 208 | break; |
| 209 | case COMBIOS_ASIC_INIT_2_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 210 | check_offset = 0x4e; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 211 | break; |
| 212 | case COMBIOS_CONNECTOR_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 213 | check_offset = 0x50; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 214 | break; |
| 215 | case COMBIOS_DYN_CLK_1_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 216 | check_offset = 0x52; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 217 | break; |
| 218 | case COMBIOS_RESERVED_MEM_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 219 | check_offset = 0x54; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 220 | break; |
| 221 | case COMBIOS_EXT_TMDS_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 222 | check_offset = 0x58; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 223 | break; |
| 224 | case COMBIOS_MEM_CLK_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 225 | check_offset = 0x5a; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 226 | break; |
| 227 | case COMBIOS_EXT_DAC_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 228 | check_offset = 0x5c; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 229 | break; |
| 230 | case COMBIOS_MISC_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 231 | check_offset = 0x5e; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 232 | break; |
| 233 | case COMBIOS_CRT_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 234 | check_offset = 0x60; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 235 | break; |
| 236 | case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 237 | check_offset = 0x62; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 238 | break; |
| 239 | case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 240 | check_offset = 0x64; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 241 | break; |
| 242 | case COMBIOS_FAN_SPEED_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 243 | check_offset = 0x66; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 244 | break; |
| 245 | case COMBIOS_OVERDRIVE_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 246 | check_offset = 0x68; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 247 | break; |
| 248 | case COMBIOS_OEM_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 249 | check_offset = 0x6a; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | break; |
| 251 | case COMBIOS_DYN_CLK_2_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 252 | check_offset = 0x6c; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 253 | break; |
| 254 | case COMBIOS_POWER_CONNECTOR_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 255 | check_offset = 0x6e; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | break; |
| 257 | case COMBIOS_I2C_INFO_TABLE: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 258 | check_offset = 0x70; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 259 | break; |
| 260 | /* relative offset tables */ |
| 261 | case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ |
| 262 | check_offset = |
| 263 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
| 264 | if (check_offset) { |
| 265 | rev = RBIOS8(check_offset); |
| 266 | if (rev > 0) { |
| 267 | check_offset = RBIOS16(check_offset + 0x3); |
| 268 | if (check_offset) |
| 269 | offset = check_offset; |
| 270 | } |
| 271 | } |
| 272 | break; |
| 273 | case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ |
| 274 | check_offset = |
| 275 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
| 276 | if (check_offset) { |
| 277 | rev = RBIOS8(check_offset); |
| 278 | if (rev > 0) { |
| 279 | check_offset = RBIOS16(check_offset + 0x5); |
| 280 | if (check_offset) |
| 281 | offset = check_offset; |
| 282 | } |
| 283 | } |
| 284 | break; |
| 285 | case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ |
| 286 | check_offset = |
| 287 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
| 288 | if (check_offset) { |
| 289 | rev = RBIOS8(check_offset); |
| 290 | if (rev > 0) { |
| 291 | check_offset = RBIOS16(check_offset + 0x7); |
| 292 | if (check_offset) |
| 293 | offset = check_offset; |
| 294 | } |
| 295 | } |
| 296 | break; |
| 297 | case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ |
| 298 | check_offset = |
| 299 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
| 300 | if (check_offset) { |
| 301 | rev = RBIOS8(check_offset); |
| 302 | if (rev == 2) { |
| 303 | check_offset = RBIOS16(check_offset + 0x9); |
| 304 | if (check_offset) |
| 305 | offset = check_offset; |
| 306 | } |
| 307 | } |
| 308 | break; |
| 309 | case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ |
| 310 | check_offset = |
| 311 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
| 312 | if (check_offset) { |
| 313 | while (RBIOS8(check_offset++)); |
| 314 | check_offset += 2; |
| 315 | if (check_offset) |
| 316 | offset = check_offset; |
| 317 | } |
| 318 | break; |
| 319 | case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ |
| 320 | check_offset = |
| 321 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
| 322 | if (check_offset) { |
| 323 | check_offset = RBIOS16(check_offset + 0x11); |
| 324 | if (check_offset) |
| 325 | offset = check_offset; |
| 326 | } |
| 327 | break; |
| 328 | case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ |
| 329 | check_offset = |
| 330 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
| 331 | if (check_offset) { |
| 332 | check_offset = RBIOS16(check_offset + 0x13); |
| 333 | if (check_offset) |
| 334 | offset = check_offset; |
| 335 | } |
| 336 | break; |
| 337 | case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ |
| 338 | check_offset = |
| 339 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
| 340 | if (check_offset) { |
| 341 | check_offset = RBIOS16(check_offset + 0x15); |
| 342 | if (check_offset) |
| 343 | offset = check_offset; |
| 344 | } |
| 345 | break; |
| 346 | case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ |
| 347 | check_offset = |
| 348 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
| 349 | if (check_offset) { |
| 350 | check_offset = RBIOS16(check_offset + 0x17); |
| 351 | if (check_offset) |
| 352 | offset = check_offset; |
| 353 | } |
| 354 | break; |
| 355 | case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ |
| 356 | check_offset = |
| 357 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); |
| 358 | if (check_offset) { |
| 359 | check_offset = RBIOS16(check_offset + 0x2); |
| 360 | if (check_offset) |
| 361 | offset = check_offset; |
| 362 | } |
| 363 | break; |
| 364 | case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ |
| 365 | check_offset = |
| 366 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); |
| 367 | if (check_offset) { |
| 368 | check_offset = RBIOS16(check_offset + 0x4); |
| 369 | if (check_offset) |
| 370 | offset = check_offset; |
| 371 | } |
| 372 | break; |
| 373 | default: |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 374 | check_offset = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 375 | break; |
| 376 | } |
| 377 | |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 378 | size = RBIOS8(rdev->bios_header_start + 0x6); |
| 379 | /* check absolute offset tables */ |
| 380 | if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) |
| 381 | offset = RBIOS16(rdev->bios_header_start + check_offset); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 382 | |
Mark Kettenis | ec9c4c4 | 2013-07-21 16:44:09 -0400 | [diff] [blame] | 383 | return offset; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 384 | } |
| 385 | |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 386 | bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) |
| 387 | { |
Alex Deucher | fafcf94 | 2011-03-23 08:10:10 +0000 | [diff] [blame] | 388 | int edid_info, size; |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 389 | struct edid *edid; |
Adam Jackson | 7466f4c | 2010-03-29 21:43:23 +0000 | [diff] [blame] | 390 | unsigned char *raw; |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 391 | edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); |
| 392 | if (!edid_info) |
| 393 | return false; |
| 394 | |
Adam Jackson | 7466f4c | 2010-03-29 21:43:23 +0000 | [diff] [blame] | 395 | raw = rdev->bios + edid_info; |
Alex Deucher | fafcf94 | 2011-03-23 08:10:10 +0000 | [diff] [blame] | 396 | size = EDID_LENGTH * (raw[0x7e] + 1); |
| 397 | edid = kmalloc(size, GFP_KERNEL); |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 398 | if (edid == NULL) |
| 399 | return false; |
| 400 | |
Alex Deucher | fafcf94 | 2011-03-23 08:10:10 +0000 | [diff] [blame] | 401 | memcpy((unsigned char *)edid, raw, size); |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 402 | |
| 403 | if (!drm_edid_is_valid(edid)) { |
| 404 | kfree(edid); |
| 405 | return false; |
| 406 | } |
| 407 | |
| 408 | rdev->mode_info.bios_hardcoded_edid = edid; |
Alex Deucher | fafcf94 | 2011-03-23 08:10:10 +0000 | [diff] [blame] | 409 | rdev->mode_info.bios_hardcoded_edid_size = size; |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 410 | return true; |
| 411 | } |
| 412 | |
Alex Deucher | c324acd | 2010-12-08 22:13:06 -0500 | [diff] [blame] | 413 | /* this is used for atom LCDs as well */ |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 414 | struct edid * |
Alex Deucher | c324acd | 2010-12-08 22:13:06 -0500 | [diff] [blame] | 415 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 416 | { |
Alex Deucher | fafcf94 | 2011-03-23 08:10:10 +0000 | [diff] [blame] | 417 | struct edid *edid; |
| 418 | |
| 419 | if (rdev->mode_info.bios_hardcoded_edid) { |
| 420 | edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); |
| 421 | if (edid) { |
| 422 | memcpy((unsigned char *)edid, |
| 423 | (unsigned char *)rdev->mode_info.bios_hardcoded_edid, |
| 424 | rdev->mode_info.bios_hardcoded_edid_size); |
| 425 | return edid; |
| 426 | } |
| 427 | } |
Alex Deucher | 3c53788 | 2010-02-05 04:21:19 -0500 | [diff] [blame] | 428 | return NULL; |
| 429 | } |
| 430 | |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 431 | static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 432 | enum radeon_combios_ddc ddc, |
| 433 | u32 clk_mask, |
| 434 | u32 data_mask) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 435 | { |
| 436 | struct radeon_i2c_bus_rec i2c; |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 437 | int ddc_line = 0; |
| 438 | |
| 439 | /* ddc id = mask reg |
| 440 | * DDC_NONE_DETECTED = none |
| 441 | * DDC_DVI = RADEON_GPIO_DVI_DDC |
| 442 | * DDC_VGA = RADEON_GPIO_VGA_DDC |
| 443 | * DDC_LCD = RADEON_GPIOPAD_MASK |
| 444 | * DDC_GPIO = RADEON_MDGPIO_MASK |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 445 | * r1xx |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 446 | * DDC_MONID = RADEON_GPIO_MONID |
| 447 | * DDC_CRT2 = RADEON_GPIO_CRT2_DDC |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 448 | * r200 |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 449 | * DDC_MONID = RADEON_GPIO_MONID |
| 450 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 451 | * r300/r350 |
| 452 | * DDC_MONID = RADEON_GPIO_DVI_DDC |
| 453 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
| 454 | * rv2xx/rv3xx |
| 455 | * DDC_MONID = RADEON_GPIO_MONID |
| 456 | * DDC_CRT2 = RADEON_GPIO_MONID |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 457 | * rs3xx/rs4xx |
| 458 | * DDC_MONID = RADEON_GPIOPAD_MASK |
| 459 | * DDC_CRT2 = RADEON_GPIO_MONID |
| 460 | */ |
| 461 | switch (ddc) { |
| 462 | case DDC_NONE_DETECTED: |
| 463 | default: |
| 464 | ddc_line = 0; |
| 465 | break; |
| 466 | case DDC_DVI: |
| 467 | ddc_line = RADEON_GPIO_DVI_DDC; |
| 468 | break; |
| 469 | case DDC_VGA: |
| 470 | ddc_line = RADEON_GPIO_VGA_DDC; |
| 471 | break; |
| 472 | case DDC_LCD: |
| 473 | ddc_line = RADEON_GPIOPAD_MASK; |
| 474 | break; |
| 475 | case DDC_GPIO: |
| 476 | ddc_line = RADEON_MDGPIO_MASK; |
| 477 | break; |
| 478 | case DDC_MONID: |
| 479 | if (rdev->family == CHIP_RS300 || |
| 480 | rdev->family == CHIP_RS400 || |
| 481 | rdev->family == CHIP_RS480) |
| 482 | ddc_line = RADEON_GPIOPAD_MASK; |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 483 | else if (rdev->family == CHIP_R300 || |
Alex Deucher | 776f2b7 | 2011-05-04 15:14:44 +0000 | [diff] [blame] | 484 | rdev->family == CHIP_R350) { |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 485 | ddc_line = RADEON_GPIO_DVI_DDC; |
Alex Deucher | 776f2b7 | 2011-05-04 15:14:44 +0000 | [diff] [blame] | 486 | ddc = DDC_DVI; |
| 487 | } else |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 488 | ddc_line = RADEON_GPIO_MONID; |
| 489 | break; |
| 490 | case DDC_CRT2: |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 491 | if (rdev->family == CHIP_R200 || |
| 492 | rdev->family == CHIP_R300 || |
Alex Deucher | 776f2b7 | 2011-05-04 15:14:44 +0000 | [diff] [blame] | 493 | rdev->family == CHIP_R350) { |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 494 | ddc_line = RADEON_GPIO_DVI_DDC; |
Alex Deucher | 776f2b7 | 2011-05-04 15:14:44 +0000 | [diff] [blame] | 495 | ddc = DDC_DVI; |
| 496 | } else if (rdev->family == CHIP_RS300 || |
| 497 | rdev->family == CHIP_RS400 || |
| 498 | rdev->family == CHIP_RS480) |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 499 | ddc_line = RADEON_GPIO_MONID; |
Alex Deucher | 776f2b7 | 2011-05-04 15:14:44 +0000 | [diff] [blame] | 500 | else if (rdev->family >= CHIP_RV350) { |
| 501 | ddc_line = RADEON_GPIO_MONID; |
| 502 | ddc = DDC_MONID; |
| 503 | } else |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 504 | ddc_line = RADEON_GPIO_CRT2_DDC; |
| 505 | break; |
| 506 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 507 | |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 508 | if (ddc_line == RADEON_GPIOPAD_MASK) { |
| 509 | i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; |
| 510 | i2c.mask_data_reg = RADEON_GPIOPAD_MASK; |
| 511 | i2c.a_clk_reg = RADEON_GPIOPAD_A; |
| 512 | i2c.a_data_reg = RADEON_GPIOPAD_A; |
| 513 | i2c.en_clk_reg = RADEON_GPIOPAD_EN; |
| 514 | i2c.en_data_reg = RADEON_GPIOPAD_EN; |
| 515 | i2c.y_clk_reg = RADEON_GPIOPAD_Y; |
| 516 | i2c.y_data_reg = RADEON_GPIOPAD_Y; |
| 517 | } else if (ddc_line == RADEON_MDGPIO_MASK) { |
| 518 | i2c.mask_clk_reg = RADEON_MDGPIO_MASK; |
| 519 | i2c.mask_data_reg = RADEON_MDGPIO_MASK; |
| 520 | i2c.a_clk_reg = RADEON_MDGPIO_A; |
| 521 | i2c.a_data_reg = RADEON_MDGPIO_A; |
| 522 | i2c.en_clk_reg = RADEON_MDGPIO_EN; |
| 523 | i2c.en_data_reg = RADEON_MDGPIO_EN; |
| 524 | i2c.y_clk_reg = RADEON_MDGPIO_Y; |
| 525 | i2c.y_data_reg = RADEON_MDGPIO_Y; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 526 | } else { |
| 527 | i2c.mask_clk_reg = ddc_line; |
| 528 | i2c.mask_data_reg = ddc_line; |
| 529 | i2c.a_clk_reg = ddc_line; |
| 530 | i2c.a_data_reg = ddc_line; |
Alex Deucher | 9b9fe72 | 2009-11-10 15:59:44 -0500 | [diff] [blame] | 531 | i2c.en_clk_reg = ddc_line; |
| 532 | i2c.en_data_reg = ddc_line; |
| 533 | i2c.y_clk_reg = ddc_line; |
| 534 | i2c.y_data_reg = ddc_line; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 535 | } |
| 536 | |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 537 | if (clk_mask && data_mask) { |
Alex Deucher | be66305 | 2010-11-18 17:18:08 -0500 | [diff] [blame] | 538 | /* system specific masks */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 539 | i2c.mask_clk_mask = clk_mask; |
| 540 | i2c.mask_data_mask = data_mask; |
| 541 | i2c.a_clk_mask = clk_mask; |
| 542 | i2c.a_data_mask = data_mask; |
| 543 | i2c.en_clk_mask = clk_mask; |
| 544 | i2c.en_data_mask = data_mask; |
| 545 | i2c.y_clk_mask = clk_mask; |
| 546 | i2c.y_data_mask = data_mask; |
Alex Deucher | be66305 | 2010-11-18 17:18:08 -0500 | [diff] [blame] | 547 | } else if ((ddc_line == RADEON_GPIOPAD_MASK) || |
| 548 | (ddc_line == RADEON_MDGPIO_MASK)) { |
| 549 | /* default gpiopad masks */ |
| 550 | i2c.mask_clk_mask = (0x20 << 8); |
| 551 | i2c.mask_data_mask = 0x80; |
| 552 | i2c.a_clk_mask = (0x20 << 8); |
| 553 | i2c.a_data_mask = 0x80; |
| 554 | i2c.en_clk_mask = (0x20 << 8); |
| 555 | i2c.en_data_mask = 0x80; |
| 556 | i2c.y_clk_mask = (0x20 << 8); |
| 557 | i2c.y_data_mask = 0x80; |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 558 | } else { |
Alex Deucher | be66305 | 2010-11-18 17:18:08 -0500 | [diff] [blame] | 559 | /* default masks for ddc pads */ |
Jean Delvare | 286e0c9 | 2011-10-06 18:16:24 +0200 | [diff] [blame] | 560 | i2c.mask_clk_mask = RADEON_GPIO_MASK_1; |
| 561 | i2c.mask_data_mask = RADEON_GPIO_MASK_0; |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 562 | i2c.a_clk_mask = RADEON_GPIO_A_1; |
| 563 | i2c.a_data_mask = RADEON_GPIO_A_0; |
| 564 | i2c.en_clk_mask = RADEON_GPIO_EN_1; |
| 565 | i2c.en_data_mask = RADEON_GPIO_EN_0; |
| 566 | i2c.y_clk_mask = RADEON_GPIO_Y_1; |
| 567 | i2c.y_data_mask = RADEON_GPIO_Y_0; |
| 568 | } |
| 569 | |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 570 | switch (rdev->family) { |
| 571 | case CHIP_R100: |
| 572 | case CHIP_RV100: |
| 573 | case CHIP_RS100: |
| 574 | case CHIP_RV200: |
| 575 | case CHIP_RS200: |
| 576 | case CHIP_RS300: |
| 577 | switch (ddc_line) { |
| 578 | case RADEON_GPIO_DVI_DDC: |
Alex Deucher | b28ea41 | 2010-03-12 13:30:49 -0500 | [diff] [blame] | 579 | i2c.hw_capable = true; |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 580 | break; |
| 581 | default: |
| 582 | i2c.hw_capable = false; |
| 583 | break; |
| 584 | } |
| 585 | break; |
| 586 | case CHIP_R200: |
| 587 | switch (ddc_line) { |
| 588 | case RADEON_GPIO_DVI_DDC: |
| 589 | case RADEON_GPIO_MONID: |
| 590 | i2c.hw_capable = true; |
| 591 | break; |
| 592 | default: |
| 593 | i2c.hw_capable = false; |
| 594 | break; |
| 595 | } |
| 596 | break; |
| 597 | case CHIP_RV250: |
| 598 | case CHIP_RV280: |
| 599 | switch (ddc_line) { |
| 600 | case RADEON_GPIO_VGA_DDC: |
| 601 | case RADEON_GPIO_DVI_DDC: |
| 602 | case RADEON_GPIO_CRT2_DDC: |
| 603 | i2c.hw_capable = true; |
| 604 | break; |
| 605 | default: |
| 606 | i2c.hw_capable = false; |
| 607 | break; |
| 608 | } |
| 609 | break; |
| 610 | case CHIP_R300: |
| 611 | case CHIP_R350: |
| 612 | switch (ddc_line) { |
| 613 | case RADEON_GPIO_VGA_DDC: |
| 614 | case RADEON_GPIO_DVI_DDC: |
| 615 | i2c.hw_capable = true; |
| 616 | break; |
| 617 | default: |
| 618 | i2c.hw_capable = false; |
| 619 | break; |
| 620 | } |
| 621 | break; |
| 622 | case CHIP_RV350: |
| 623 | case CHIP_RV380: |
| 624 | case CHIP_RS400: |
| 625 | case CHIP_RS480: |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 626 | switch (ddc_line) { |
| 627 | case RADEON_GPIO_VGA_DDC: |
| 628 | case RADEON_GPIO_DVI_DDC: |
| 629 | i2c.hw_capable = true; |
| 630 | break; |
| 631 | case RADEON_GPIO_MONID: |
| 632 | /* hw i2c on RADEON_GPIO_MONID doesn't seem to work |
| 633 | * reliably on some pre-r4xx hardware; not sure why. |
| 634 | */ |
| 635 | i2c.hw_capable = false; |
| 636 | break; |
| 637 | default: |
| 638 | i2c.hw_capable = false; |
| 639 | break; |
| 640 | } |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 641 | break; |
| 642 | default: |
| 643 | i2c.hw_capable = false; |
| 644 | break; |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 645 | } |
| 646 | i2c.mm_i2c = false; |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 647 | |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 648 | i2c.i2c_id = ddc; |
Alex Deucher | 8e36ed0 | 2010-05-18 19:26:47 -0400 | [diff] [blame] | 649 | i2c.hpd = RADEON_HPD_NONE; |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 650 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 651 | if (ddc_line) |
| 652 | i2c.valid = true; |
| 653 | else |
| 654 | i2c.valid = false; |
| 655 | |
| 656 | return i2c; |
| 657 | } |
| 658 | |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 659 | void radeon_combios_i2c_init(struct radeon_device *rdev) |
| 660 | { |
| 661 | struct drm_device *dev = rdev->ddev; |
| 662 | struct radeon_i2c_bus_rec i2c; |
| 663 | |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 664 | /* actual hw pads |
| 665 | * r1xx/rs2xx/rs3xx |
| 666 | * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm |
| 667 | * r200 |
| 668 | * 0x60, 0x64, 0x68, mm |
| 669 | * r300/r350 |
| 670 | * 0x60, 0x64, mm |
| 671 | * rv2xx/rv3xx/rs4xx |
| 672 | * 0x60, 0x64, 0x68, gpiopads, mm |
| 673 | */ |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 674 | |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 675 | /* 0x60 */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 676 | i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
| 677 | rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 678 | /* 0x64 */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 679 | i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
| 680 | rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 681 | |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 682 | /* mm i2c */ |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 683 | i2c.valid = true; |
| 684 | i2c.hw_capable = true; |
| 685 | i2c.mm_i2c = true; |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 686 | i2c.i2c_id = 0xa0; |
| 687 | rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); |
| 688 | |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 689 | if (rdev->family == CHIP_R300 || |
| 690 | rdev->family == CHIP_R350) { |
| 691 | /* only 2 sw i2c pads */ |
| 692 | } else if (rdev->family == CHIP_RS300 || |
| 693 | rdev->family == CHIP_RS400 || |
| 694 | rdev->family == CHIP_RS480) { |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 695 | u16 offset; |
| 696 | u8 id, blocks, clk, data; |
| 697 | int i; |
| 698 | |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 699 | /* 0x68 */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 700 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
| 701 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
| 702 | |
| 703 | offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); |
| 704 | if (offset) { |
| 705 | blocks = RBIOS8(offset + 2); |
| 706 | for (i = 0; i < blocks; i++) { |
| 707 | id = RBIOS8(offset + 3 + (i * 5) + 0); |
| 708 | if (id == 136) { |
| 709 | clk = RBIOS8(offset + 3 + (i * 5) + 3); |
| 710 | data = RBIOS8(offset + 3 + (i * 5) + 4); |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 711 | /* gpiopad */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 712 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, |
Alex Deucher | 791cfe2 | 2010-11-21 10:58:05 -0500 | [diff] [blame] | 713 | (1 << clk), (1 << data)); |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 714 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); |
| 715 | break; |
| 716 | } |
| 717 | } |
| 718 | } |
Alex Deucher | 6dd6663 | 2011-07-23 18:02:04 +0000 | [diff] [blame] | 719 | } else if ((rdev->family == CHIP_R200) || |
| 720 | (rdev->family >= CHIP_R300)) { |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 721 | /* 0x68 */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 722 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
| 723 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
| 724 | } else { |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 725 | /* 0x68 */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 726 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
| 727 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
Alex Deucher | 508c8d6 | 2011-05-03 19:47:44 -0400 | [diff] [blame] | 728 | /* 0x6c */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 729 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
| 730 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); |
| 731 | } |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 732 | } |
| 733 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 734 | bool radeon_combios_get_clock_info(struct drm_device *dev) |
| 735 | { |
| 736 | struct radeon_device *rdev = dev->dev_private; |
| 737 | uint16_t pll_info; |
| 738 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
| 739 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
| 740 | struct radeon_pll *spll = &rdev->clock.spll; |
| 741 | struct radeon_pll *mpll = &rdev->clock.mpll; |
| 742 | int8_t rev; |
| 743 | uint16_t sclk, mclk; |
| 744 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 745 | pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); |
| 746 | if (pll_info) { |
| 747 | rev = RBIOS8(pll_info); |
| 748 | |
| 749 | /* pixel clocks */ |
| 750 | p1pll->reference_freq = RBIOS16(pll_info + 0xe); |
| 751 | p1pll->reference_div = RBIOS16(pll_info + 0x10); |
| 752 | p1pll->pll_out_min = RBIOS32(pll_info + 0x12); |
| 753 | p1pll->pll_out_max = RBIOS32(pll_info + 0x16); |
Alex Deucher | 86cb2bb | 2010-03-08 12:55:16 -0500 | [diff] [blame] | 754 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
| 755 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 756 | |
| 757 | if (rev > 9) { |
| 758 | p1pll->pll_in_min = RBIOS32(pll_info + 0x36); |
| 759 | p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); |
| 760 | } else { |
| 761 | p1pll->pll_in_min = 40; |
| 762 | p1pll->pll_in_max = 500; |
| 763 | } |
| 764 | *p2pll = *p1pll; |
| 765 | |
| 766 | /* system clock */ |
| 767 | spll->reference_freq = RBIOS16(pll_info + 0x1a); |
| 768 | spll->reference_div = RBIOS16(pll_info + 0x1c); |
| 769 | spll->pll_out_min = RBIOS32(pll_info + 0x1e); |
| 770 | spll->pll_out_max = RBIOS32(pll_info + 0x22); |
| 771 | |
| 772 | if (rev > 10) { |
| 773 | spll->pll_in_min = RBIOS32(pll_info + 0x48); |
| 774 | spll->pll_in_max = RBIOS32(pll_info + 0x4c); |
| 775 | } else { |
| 776 | /* ??? */ |
| 777 | spll->pll_in_min = 40; |
| 778 | spll->pll_in_max = 500; |
| 779 | } |
| 780 | |
| 781 | /* memory clock */ |
| 782 | mpll->reference_freq = RBIOS16(pll_info + 0x26); |
| 783 | mpll->reference_div = RBIOS16(pll_info + 0x28); |
| 784 | mpll->pll_out_min = RBIOS32(pll_info + 0x2a); |
| 785 | mpll->pll_out_max = RBIOS32(pll_info + 0x2e); |
| 786 | |
| 787 | if (rev > 10) { |
| 788 | mpll->pll_in_min = RBIOS32(pll_info + 0x5a); |
| 789 | mpll->pll_in_max = RBIOS32(pll_info + 0x5e); |
| 790 | } else { |
| 791 | /* ??? */ |
| 792 | mpll->pll_in_min = 40; |
| 793 | mpll->pll_in_max = 500; |
| 794 | } |
| 795 | |
| 796 | /* default sclk/mclk */ |
| 797 | sclk = RBIOS16(pll_info + 0xa); |
| 798 | mclk = RBIOS16(pll_info + 0x8); |
| 799 | if (sclk == 0) |
| 800 | sclk = 200 * 100; |
| 801 | if (mclk == 0) |
| 802 | mclk = 200 * 100; |
| 803 | |
| 804 | rdev->clock.default_sclk = sclk; |
| 805 | rdev->clock.default_mclk = mclk; |
| 806 | |
Alex Deucher | b20f9be | 2011-06-08 13:01:11 -0400 | [diff] [blame] | 807 | if (RBIOS32(pll_info + 0x16)) |
| 808 | rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); |
| 809 | else |
| 810 | rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ |
| 811 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 812 | return true; |
| 813 | } |
| 814 | return false; |
| 815 | } |
| 816 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 817 | bool radeon_combios_sideport_present(struct radeon_device *rdev) |
| 818 | { |
| 819 | struct drm_device *dev = rdev->ddev; |
| 820 | u16 igp_info; |
| 821 | |
Alex Deucher | 4c70b2e | 2010-08-02 19:39:15 -0400 | [diff] [blame] | 822 | /* sideport is AMD only */ |
| 823 | if (rdev->family == CHIP_RS400) |
| 824 | return false; |
| 825 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 826 | igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); |
| 827 | |
| 828 | if (igp_info) { |
| 829 | if (RBIOS16(igp_info + 0x4)) |
| 830 | return true; |
| 831 | } |
| 832 | return false; |
| 833 | } |
| 834 | |
Alex Deucher | 246263c | 2009-12-29 12:09:17 -0500 | [diff] [blame] | 835 | static const uint32_t default_primarydac_adj[CHIP_LAST] = { |
| 836 | 0x00000808, /* r100 */ |
| 837 | 0x00000808, /* rv100 */ |
| 838 | 0x00000808, /* rs100 */ |
| 839 | 0x00000808, /* rv200 */ |
| 840 | 0x00000808, /* rs200 */ |
| 841 | 0x00000808, /* r200 */ |
| 842 | 0x00000808, /* rv250 */ |
| 843 | 0x00000000, /* rs300 */ |
| 844 | 0x00000808, /* rv280 */ |
| 845 | 0x00000808, /* r300 */ |
| 846 | 0x00000808, /* r350 */ |
| 847 | 0x00000808, /* rv350 */ |
| 848 | 0x00000808, /* rv380 */ |
| 849 | 0x00000808, /* r420 */ |
| 850 | 0x00000808, /* r423 */ |
| 851 | 0x00000808, /* rv410 */ |
| 852 | 0x00000000, /* rs400 */ |
| 853 | 0x00000000, /* rs480 */ |
| 854 | }; |
| 855 | |
| 856 | static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, |
| 857 | struct radeon_encoder_primary_dac *p_dac) |
| 858 | { |
| 859 | p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; |
| 860 | return; |
| 861 | } |
| 862 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 863 | struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct |
| 864 | radeon_encoder |
| 865 | *encoder) |
| 866 | { |
| 867 | struct drm_device *dev = encoder->base.dev; |
| 868 | struct radeon_device *rdev = dev->dev_private; |
| 869 | uint16_t dac_info; |
| 870 | uint8_t rev, bg, dac; |
| 871 | struct radeon_encoder_primary_dac *p_dac = NULL; |
Alex Deucher | 246263c | 2009-12-29 12:09:17 -0500 | [diff] [blame] | 872 | int found = 0; |
| 873 | |
| 874 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), |
| 875 | GFP_KERNEL); |
| 876 | |
| 877 | if (!p_dac) |
| 878 | return NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 879 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 880 | /* check CRT table */ |
| 881 | dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
| 882 | if (dac_info) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 883 | rev = RBIOS8(dac_info) & 0x3; |
| 884 | if (rev < 2) { |
| 885 | bg = RBIOS8(dac_info + 0x2) & 0xf; |
| 886 | dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; |
| 887 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
| 888 | } else { |
| 889 | bg = RBIOS8(dac_info + 0x2) & 0xf; |
| 890 | dac = RBIOS8(dac_info + 0x3) & 0xf; |
| 891 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
| 892 | } |
Alex Deucher | f0870ae | 2013-07-19 17:44:43 -0400 | [diff] [blame] | 893 | /* if the values are zeros, use the table */ |
| 894 | if ((dac == 0) || (bg == 0)) |
| 895 | found = 0; |
| 896 | else |
Alex Deucher | 3a89b4a | 2010-04-06 12:35:26 -0400 | [diff] [blame] | 897 | found = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 898 | } |
| 899 | |
Alex Deucher | cc56065 | 2013-02-27 12:01:58 -0500 | [diff] [blame] | 900 | /* quirks */ |
| 901 | /* Radeon 9100 (R200) */ |
| 902 | if ((dev->pdev->device == 0x514D) && |
| 903 | (dev->pdev->subsystem_vendor == 0x174B) && |
| 904 | (dev->pdev->subsystem_device == 0x7149)) { |
| 905 | /* vbios value is bad, use the default */ |
| 906 | found = 0; |
| 907 | } |
| 908 | |
Alex Deucher | 246263c | 2009-12-29 12:09:17 -0500 | [diff] [blame] | 909 | if (!found) /* fallback to defaults */ |
| 910 | radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); |
| 911 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 912 | return p_dac; |
| 913 | } |
| 914 | |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 915 | enum radeon_tv_std |
| 916 | radeon_combios_get_tv_info(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 917 | { |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 918 | struct drm_device *dev = rdev->ddev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 919 | uint16_t tv_info; |
| 920 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
| 921 | |
| 922 | tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
| 923 | if (tv_info) { |
| 924 | if (RBIOS8(tv_info + 6) == 'T') { |
| 925 | switch (RBIOS8(tv_info + 7) & 0xf) { |
| 926 | case 1: |
| 927 | tv_std = TV_STD_NTSC; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 928 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 929 | break; |
| 930 | case 2: |
| 931 | tv_std = TV_STD_PAL; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 932 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 933 | break; |
| 934 | case 3: |
| 935 | tv_std = TV_STD_PAL_M; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 936 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 937 | break; |
| 938 | case 4: |
| 939 | tv_std = TV_STD_PAL_60; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 940 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 941 | break; |
| 942 | case 5: |
| 943 | tv_std = TV_STD_NTSC_J; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 944 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 945 | break; |
| 946 | case 6: |
| 947 | tv_std = TV_STD_SCART_PAL; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 948 | DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 949 | break; |
| 950 | default: |
| 951 | tv_std = TV_STD_NTSC; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 952 | DRM_DEBUG_KMS |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 953 | ("Unknown TV standard; defaulting to NTSC\n"); |
| 954 | break; |
| 955 | } |
| 956 | |
| 957 | switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { |
| 958 | case 0: |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 959 | DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 960 | break; |
| 961 | case 1: |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 962 | DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 963 | break; |
| 964 | case 2: |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 965 | DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 966 | break; |
| 967 | case 3: |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 968 | DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 969 | break; |
| 970 | default: |
| 971 | break; |
| 972 | } |
| 973 | } |
| 974 | } |
| 975 | return tv_std; |
| 976 | } |
| 977 | |
| 978 | static const uint32_t default_tvdac_adj[CHIP_LAST] = { |
| 979 | 0x00000000, /* r100 */ |
| 980 | 0x00280000, /* rv100 */ |
| 981 | 0x00000000, /* rs100 */ |
| 982 | 0x00880000, /* rv200 */ |
| 983 | 0x00000000, /* rs200 */ |
| 984 | 0x00000000, /* r200 */ |
| 985 | 0x00770000, /* rv250 */ |
| 986 | 0x00290000, /* rs300 */ |
| 987 | 0x00560000, /* rv280 */ |
| 988 | 0x00780000, /* r300 */ |
| 989 | 0x00770000, /* r350 */ |
| 990 | 0x00780000, /* rv350 */ |
| 991 | 0x00780000, /* rv380 */ |
| 992 | 0x01080000, /* r420 */ |
| 993 | 0x01080000, /* r423 */ |
| 994 | 0x01080000, /* rv410 */ |
| 995 | 0x00780000, /* rs400 */ |
| 996 | 0x00780000, /* rs480 */ |
| 997 | }; |
| 998 | |
Dave Airlie | 6a719e0 | 2009-08-17 10:19:51 +1000 | [diff] [blame] | 999 | static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, |
| 1000 | struct radeon_encoder_tv_dac *tv_dac) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1001 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1002 | tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; |
| 1003 | if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) |
| 1004 | tv_dac->ps2_tvdac_adj = 0x00880000; |
| 1005 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
| 1006 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
Dave Airlie | 6a719e0 | 2009-08-17 10:19:51 +1000 | [diff] [blame] | 1007 | return; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1008 | } |
| 1009 | |
| 1010 | struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct |
| 1011 | radeon_encoder |
| 1012 | *encoder) |
| 1013 | { |
| 1014 | struct drm_device *dev = encoder->base.dev; |
| 1015 | struct radeon_device *rdev = dev->dev_private; |
| 1016 | uint16_t dac_info; |
| 1017 | uint8_t rev, bg, dac; |
| 1018 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
Dave Airlie | 6a719e0 | 2009-08-17 10:19:51 +1000 | [diff] [blame] | 1019 | int found = 0; |
| 1020 | |
| 1021 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
| 1022 | if (!tv_dac) |
| 1023 | return NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1024 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1025 | /* first check TV table */ |
| 1026 | dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
| 1027 | if (dac_info) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1028 | rev = RBIOS8(dac_info + 0x3); |
| 1029 | if (rev > 4) { |
| 1030 | bg = RBIOS8(dac_info + 0xc) & 0xf; |
| 1031 | dac = RBIOS8(dac_info + 0xd) & 0xf; |
| 1032 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
| 1033 | |
| 1034 | bg = RBIOS8(dac_info + 0xe) & 0xf; |
| 1035 | dac = RBIOS8(dac_info + 0xf) & 0xf; |
| 1036 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
| 1037 | |
| 1038 | bg = RBIOS8(dac_info + 0x10) & 0xf; |
| 1039 | dac = RBIOS8(dac_info + 0x11) & 0xf; |
| 1040 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
Alex Deucher | 3a89b4a | 2010-04-06 12:35:26 -0400 | [diff] [blame] | 1041 | /* if the values are all zeros, use the table */ |
| 1042 | if (tv_dac->ps2_tvdac_adj) |
| 1043 | found = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1044 | } else if (rev > 1) { |
| 1045 | bg = RBIOS8(dac_info + 0xc) & 0xf; |
| 1046 | dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; |
| 1047 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
| 1048 | |
| 1049 | bg = RBIOS8(dac_info + 0xd) & 0xf; |
| 1050 | dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; |
| 1051 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
| 1052 | |
| 1053 | bg = RBIOS8(dac_info + 0xe) & 0xf; |
| 1054 | dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; |
| 1055 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
Alex Deucher | 3a89b4a | 2010-04-06 12:35:26 -0400 | [diff] [blame] | 1056 | /* if the values are all zeros, use the table */ |
| 1057 | if (tv_dac->ps2_tvdac_adj) |
| 1058 | found = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1059 | } |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 1060 | tv_dac->tv_std = radeon_combios_get_tv_info(rdev); |
Dave Airlie | 6a719e0 | 2009-08-17 10:19:51 +1000 | [diff] [blame] | 1061 | } |
| 1062 | if (!found) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1063 | /* then check CRT table */ |
| 1064 | dac_info = |
| 1065 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
| 1066 | if (dac_info) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1067 | rev = RBIOS8(dac_info) & 0x3; |
| 1068 | if (rev < 2) { |
| 1069 | bg = RBIOS8(dac_info + 0x3) & 0xf; |
| 1070 | dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; |
| 1071 | tv_dac->ps2_tvdac_adj = |
| 1072 | (bg << 16) | (dac << 20); |
| 1073 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
| 1074 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
Alex Deucher | 3a89b4a | 2010-04-06 12:35:26 -0400 | [diff] [blame] | 1075 | /* if the values are all zeros, use the table */ |
| 1076 | if (tv_dac->ps2_tvdac_adj) |
| 1077 | found = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1078 | } else { |
| 1079 | bg = RBIOS8(dac_info + 0x4) & 0xf; |
| 1080 | dac = RBIOS8(dac_info + 0x5) & 0xf; |
| 1081 | tv_dac->ps2_tvdac_adj = |
| 1082 | (bg << 16) | (dac << 20); |
| 1083 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
| 1084 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
Alex Deucher | 3a89b4a | 2010-04-06 12:35:26 -0400 | [diff] [blame] | 1085 | /* if the values are all zeros, use the table */ |
| 1086 | if (tv_dac->ps2_tvdac_adj) |
| 1087 | found = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1088 | } |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1089 | } else { |
| 1090 | DRM_INFO("No TV DAC info found in BIOS\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1091 | } |
| 1092 | } |
| 1093 | |
Dave Airlie | 6a719e0 | 2009-08-17 10:19:51 +1000 | [diff] [blame] | 1094 | if (!found) /* fallback to defaults */ |
| 1095 | radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); |
| 1096 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1097 | return tv_dac; |
| 1098 | } |
| 1099 | |
| 1100 | static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct |
| 1101 | radeon_device |
| 1102 | *rdev) |
| 1103 | { |
| 1104 | struct radeon_encoder_lvds *lvds = NULL; |
| 1105 | uint32_t fp_vert_stretch, fp_horz_stretch; |
| 1106 | uint32_t ppll_div_sel, ppll_val; |
Michel Dänzer | 8b5c744 | 2009-06-17 18:28:38 +0200 | [diff] [blame] | 1107 | uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1108 | |
| 1109 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); |
| 1110 | |
| 1111 | if (!lvds) |
| 1112 | return NULL; |
| 1113 | |
| 1114 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); |
| 1115 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); |
| 1116 | |
Michel Dänzer | 8b5c744 | 2009-06-17 18:28:38 +0200 | [diff] [blame] | 1117 | /* These should be fail-safe defaults, fingers crossed */ |
| 1118 | lvds->panel_pwr_delay = 200; |
| 1119 | lvds->panel_vcc_delay = 2000; |
| 1120 | |
| 1121 | lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
| 1122 | lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; |
| 1123 | lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; |
| 1124 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1125 | if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1126 | lvds->native_mode.vdisplay = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1127 | ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> |
| 1128 | RADEON_VERT_PANEL_SHIFT) + 1; |
| 1129 | else |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1130 | lvds->native_mode.vdisplay = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1131 | (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; |
| 1132 | |
| 1133 | if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1134 | lvds->native_mode.hdisplay = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1135 | (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> |
| 1136 | RADEON_HORZ_PANEL_SHIFT) + 1) * 8; |
| 1137 | else |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1138 | lvds->native_mode.hdisplay = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1139 | ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; |
| 1140 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1141 | if ((lvds->native_mode.hdisplay < 640) || |
| 1142 | (lvds->native_mode.vdisplay < 480)) { |
| 1143 | lvds->native_mode.hdisplay = 640; |
| 1144 | lvds->native_mode.vdisplay = 480; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1145 | } |
| 1146 | |
| 1147 | ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; |
| 1148 | ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); |
| 1149 | if ((ppll_val & 0x000707ff) == 0x1bb) |
| 1150 | lvds->use_bios_dividers = false; |
| 1151 | else { |
| 1152 | lvds->panel_ref_divider = |
| 1153 | RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
| 1154 | lvds->panel_post_divider = (ppll_val >> 16) & 0x7; |
| 1155 | lvds->panel_fb_divider = ppll_val & 0x7ff; |
| 1156 | |
| 1157 | if ((lvds->panel_ref_divider != 0) && |
| 1158 | (lvds->panel_fb_divider > 3)) |
| 1159 | lvds->use_bios_dividers = true; |
| 1160 | } |
| 1161 | lvds->panel_vcc_delay = 200; |
| 1162 | |
| 1163 | DRM_INFO("Panel info derived from registers\n"); |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1164 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, |
| 1165 | lvds->native_mode.vdisplay); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1166 | |
| 1167 | return lvds; |
| 1168 | } |
| 1169 | |
| 1170 | struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder |
| 1171 | *encoder) |
| 1172 | { |
| 1173 | struct drm_device *dev = encoder->base.dev; |
| 1174 | struct radeon_device *rdev = dev->dev_private; |
| 1175 | uint16_t lcd_info; |
| 1176 | uint32_t panel_setup; |
| 1177 | char stmp[30]; |
| 1178 | int tmp, i; |
| 1179 | struct radeon_encoder_lvds *lvds = NULL; |
| 1180 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1181 | lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
| 1182 | |
| 1183 | if (lcd_info) { |
| 1184 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); |
| 1185 | |
| 1186 | if (!lvds) |
| 1187 | return NULL; |
| 1188 | |
| 1189 | for (i = 0; i < 24; i++) |
| 1190 | stmp[i] = RBIOS8(lcd_info + i + 1); |
| 1191 | stmp[24] = 0; |
| 1192 | |
| 1193 | DRM_INFO("Panel ID String: %s\n", stmp); |
| 1194 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1195 | lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); |
| 1196 | lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1197 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1198 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, |
| 1199 | lvds->native_mode.vdisplay); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1200 | |
| 1201 | lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); |
Andrew Morton | 94cf643 | 2010-02-02 14:40:29 -0800 | [diff] [blame] | 1202 | lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1203 | |
| 1204 | lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); |
| 1205 | lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; |
| 1206 | lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; |
| 1207 | |
| 1208 | lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); |
| 1209 | lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); |
| 1210 | lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); |
| 1211 | if ((lvds->panel_ref_divider != 0) && |
| 1212 | (lvds->panel_fb_divider > 3)) |
| 1213 | lvds->use_bios_dividers = true; |
| 1214 | |
| 1215 | panel_setup = RBIOS32(lcd_info + 0x39); |
| 1216 | lvds->lvds_gen_cntl = 0xff00; |
| 1217 | if (panel_setup & 0x1) |
| 1218 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; |
| 1219 | |
| 1220 | if ((panel_setup >> 4) & 0x1) |
| 1221 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; |
| 1222 | |
| 1223 | switch ((panel_setup >> 8) & 0x7) { |
| 1224 | case 0: |
| 1225 | lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; |
| 1226 | break; |
| 1227 | case 1: |
| 1228 | lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; |
| 1229 | break; |
| 1230 | case 2: |
| 1231 | lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; |
| 1232 | break; |
| 1233 | default: |
| 1234 | break; |
| 1235 | } |
| 1236 | |
| 1237 | if ((panel_setup >> 16) & 0x1) |
| 1238 | lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; |
| 1239 | |
| 1240 | if ((panel_setup >> 17) & 0x1) |
| 1241 | lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; |
| 1242 | |
| 1243 | if ((panel_setup >> 18) & 0x1) |
| 1244 | lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; |
| 1245 | |
| 1246 | if ((panel_setup >> 23) & 0x1) |
| 1247 | lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; |
| 1248 | |
| 1249 | lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); |
| 1250 | |
| 1251 | for (i = 0; i < 32; i++) { |
| 1252 | tmp = RBIOS16(lcd_info + 64 + i * 2); |
| 1253 | if (tmp == 0) |
| 1254 | break; |
| 1255 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1256 | if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && |
Alex Deucher | 68b61a7 | 2010-05-18 00:30:05 -0400 | [diff] [blame] | 1257 | (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { |
| 1258 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
| 1259 | (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; |
| 1260 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
| 1261 | (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; |
| 1262 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
| 1263 | (RBIOS8(tmp + 23) * 8); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1264 | |
Alex Deucher | 68b61a7 | 2010-05-18 00:30:05 -0400 | [diff] [blame] | 1265 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
| 1266 | (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); |
| 1267 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
| 1268 | ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); |
| 1269 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
| 1270 | ((RBIOS16(tmp + 28) & 0xf800) >> 11); |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1271 | |
| 1272 | lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1273 | lvds->native_mode.flags = 0; |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1274 | /* set crtc values */ |
| 1275 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); |
| 1276 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1277 | } |
| 1278 | } |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1279 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1280 | DRM_INFO("No panel info found in BIOS\n"); |
Michel Dänzer | 8dfaa8a | 2009-09-15 17:09:27 +0200 | [diff] [blame] | 1281 | lvds = radeon_legacy_get_lvds_info_from_regs(rdev); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1282 | } |
Michel Dänzer | 03047cd | 2010-02-10 11:05:11 +0100 | [diff] [blame] | 1283 | |
Michel Dänzer | 8dfaa8a | 2009-09-15 17:09:27 +0200 | [diff] [blame] | 1284 | if (lvds) |
| 1285 | encoder->native_mode = lvds->native_mode; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1286 | return lvds; |
| 1287 | } |
| 1288 | |
| 1289 | static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { |
| 1290 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ |
| 1291 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ |
| 1292 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ |
| 1293 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ |
| 1294 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ |
| 1295 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ |
| 1296 | {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ |
| 1297 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ |
| 1298 | {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ |
| 1299 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ |
| 1300 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ |
| 1301 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ |
| 1302 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ |
| 1303 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ |
| 1304 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ |
| 1305 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1306 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ |
| 1307 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1308 | }; |
| 1309 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1310 | bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
| 1311 | struct radeon_encoder_int_tmds *tmds) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1312 | { |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1313 | struct drm_device *dev = encoder->base.dev; |
| 1314 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1315 | int i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1316 | |
| 1317 | for (i = 0; i < 4; i++) { |
| 1318 | tmds->tmds_pll[i].value = |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1319 | default_tmds_pll[rdev->family][i].value; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1320 | tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; |
| 1321 | } |
| 1322 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1323 | return true; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1324 | } |
| 1325 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1326 | bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
| 1327 | struct radeon_encoder_int_tmds *tmds) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1328 | { |
| 1329 | struct drm_device *dev = encoder->base.dev; |
| 1330 | struct radeon_device *rdev = dev->dev_private; |
| 1331 | uint16_t tmds_info; |
| 1332 | int i, n; |
| 1333 | uint8_t ver; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1334 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1335 | tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
| 1336 | |
| 1337 | if (tmds_info) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1338 | ver = RBIOS8(tmds_info); |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1339 | DRM_DEBUG_KMS("DFP table revision: %d\n", ver); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1340 | if (ver == 3) { |
| 1341 | n = RBIOS8(tmds_info + 5) + 1; |
| 1342 | if (n > 4) |
| 1343 | n = 4; |
| 1344 | for (i = 0; i < n; i++) { |
| 1345 | tmds->tmds_pll[i].value = |
| 1346 | RBIOS32(tmds_info + i * 10 + 0x08); |
| 1347 | tmds->tmds_pll[i].freq = |
| 1348 | RBIOS16(tmds_info + i * 10 + 0x10); |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1349 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1350 | tmds->tmds_pll[i].freq, |
| 1351 | tmds->tmds_pll[i].value); |
| 1352 | } |
| 1353 | } else if (ver == 4) { |
| 1354 | int stride = 0; |
| 1355 | n = RBIOS8(tmds_info + 5) + 1; |
| 1356 | if (n > 4) |
| 1357 | n = 4; |
| 1358 | for (i = 0; i < n; i++) { |
| 1359 | tmds->tmds_pll[i].value = |
| 1360 | RBIOS32(tmds_info + stride + 0x08); |
| 1361 | tmds->tmds_pll[i].freq = |
| 1362 | RBIOS16(tmds_info + stride + 0x10); |
| 1363 | if (i == 0) |
| 1364 | stride += 10; |
| 1365 | else |
| 1366 | stride += 6; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1367 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1368 | tmds->tmds_pll[i].freq, |
| 1369 | tmds->tmds_pll[i].value); |
| 1370 | } |
| 1371 | } |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1372 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1373 | DRM_INFO("No TMDS info found in BIOS\n"); |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1374 | return false; |
| 1375 | } |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1376 | return true; |
| 1377 | } |
| 1378 | |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1379 | bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
| 1380 | struct radeon_encoder_ext_tmds *tmds) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1381 | { |
| 1382 | struct drm_device *dev = encoder->base.dev; |
| 1383 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1384 | struct radeon_i2c_bus_rec i2c_bus; |
| 1385 | |
| 1386 | /* default for macs */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1387 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 1388 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1389 | |
| 1390 | /* XXX some macs have duallink chips */ |
| 1391 | switch (rdev->mode_info.connector_table) { |
| 1392 | case CT_POWERBOOK_EXTERNAL: |
| 1393 | case CT_MINI_EXTERNAL: |
| 1394 | default: |
| 1395 | tmds->dvo_chip = DVO_SIL164; |
| 1396 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
| 1397 | break; |
| 1398 | } |
| 1399 | |
| 1400 | return true; |
| 1401 | } |
| 1402 | |
| 1403 | bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
| 1404 | struct radeon_encoder_ext_tmds *tmds) |
| 1405 | { |
| 1406 | struct drm_device *dev = encoder->base.dev; |
| 1407 | struct radeon_device *rdev = dev->dev_private; |
| 1408 | uint16_t offset; |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1409 | uint8_t ver; |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1410 | enum radeon_combios_ddc gpio; |
| 1411 | struct radeon_i2c_bus_rec i2c_bus; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1412 | |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1413 | tmds->i2c_bus = NULL; |
| 1414 | if (rdev->flags & RADEON_IS_IGP) { |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1415 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
| 1416 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
| 1417 | tmds->dvo_chip = DVO_SIL164; |
| 1418 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1419 | } else { |
| 1420 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
| 1421 | if (offset) { |
| 1422 | ver = RBIOS8(offset); |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1423 | DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1424 | tmds->slave_addr = RBIOS8(offset + 4 + 2); |
| 1425 | tmds->slave_addr >>= 1; /* 7 bit addressing */ |
| 1426 | gpio = RBIOS8(offset + 4 + 3); |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1427 | if (gpio == DDC_LCD) { |
| 1428 | /* MM i2c */ |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 1429 | i2c_bus.valid = true; |
| 1430 | i2c_bus.hw_capable = true; |
| 1431 | i2c_bus.mm_i2c = true; |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1432 | i2c_bus.i2c_id = 0xa0; |
| 1433 | } else |
| 1434 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
| 1435 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1436 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1437 | } |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1438 | |
| 1439 | if (!tmds->i2c_bus) { |
| 1440 | DRM_INFO("No valid Ext TMDS info found in BIOS\n"); |
| 1441 | return false; |
| 1442 | } |
| 1443 | |
| 1444 | return true; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1445 | } |
| 1446 | |
| 1447 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) |
| 1448 | { |
| 1449 | struct radeon_device *rdev = dev->dev_private; |
| 1450 | struct radeon_i2c_bus_rec ddc_i2c; |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1451 | struct radeon_hpd hpd; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1452 | |
| 1453 | rdev->mode_info.connector_table = radeon_connector_table; |
| 1454 | if (rdev->mode_info.connector_table == CT_NONE) { |
| 1455 | #ifdef CONFIG_PPC_PMAC |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1456 | if (of_machine_is_compatible("PowerBook3,3")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1457 | /* powerbook with VGA */ |
| 1458 | rdev->mode_info.connector_table = CT_POWERBOOK_VGA; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1459 | } else if (of_machine_is_compatible("PowerBook3,4") || |
| 1460 | of_machine_is_compatible("PowerBook3,5")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1461 | /* powerbook with internal tmds */ |
| 1462 | rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1463 | } else if (of_machine_is_compatible("PowerBook5,1") || |
| 1464 | of_machine_is_compatible("PowerBook5,2") || |
| 1465 | of_machine_is_compatible("PowerBook5,3") || |
| 1466 | of_machine_is_compatible("PowerBook5,4") || |
| 1467 | of_machine_is_compatible("PowerBook5,5")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1468 | /* powerbook with external single link tmds (sil164) */ |
| 1469 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1470 | } else if (of_machine_is_compatible("PowerBook5,6")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1471 | /* powerbook with external dual or single link tmds */ |
| 1472 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1473 | } else if (of_machine_is_compatible("PowerBook5,7") || |
| 1474 | of_machine_is_compatible("PowerBook5,8") || |
| 1475 | of_machine_is_compatible("PowerBook5,9")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1476 | /* PowerBook6,2 ? */ |
| 1477 | /* powerbook with external dual link tmds (sil1178?) */ |
| 1478 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1479 | } else if (of_machine_is_compatible("PowerBook4,1") || |
| 1480 | of_machine_is_compatible("PowerBook4,2") || |
| 1481 | of_machine_is_compatible("PowerBook4,3") || |
| 1482 | of_machine_is_compatible("PowerBook6,3") || |
| 1483 | of_machine_is_compatible("PowerBook6,5") || |
| 1484 | of_machine_is_compatible("PowerBook6,7")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1485 | /* ibook */ |
| 1486 | rdev->mode_info.connector_table = CT_IBOOK; |
Alex Deucher | ac2f952 | 2012-12-20 16:35:47 -0500 | [diff] [blame^] | 1487 | } else if (of_machine_is_compatible("PowerMac3,5")) { |
| 1488 | /* PowerMac G4 Silver radeon 7500 */ |
| 1489 | rdev->mode_info.connector_table = CT_MAC_G4_SILVER; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1490 | } else if (of_machine_is_compatible("PowerMac4,4")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1491 | /* emac */ |
| 1492 | rdev->mode_info.connector_table = CT_EMAC; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1493 | } else if (of_machine_is_compatible("PowerMac10,1")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1494 | /* mini with internal tmds */ |
| 1495 | rdev->mode_info.connector_table = CT_MINI_INTERNAL; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1496 | } else if (of_machine_is_compatible("PowerMac10,2")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1497 | /* mini with external tmds */ |
| 1498 | rdev->mode_info.connector_table = CT_MINI_EXTERNAL; |
Grant Likely | 71a157e | 2010-02-01 21:34:14 -0700 | [diff] [blame] | 1499 | } else if (of_machine_is_compatible("PowerMac12,1")) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1500 | /* PowerMac8,1 ? */ |
| 1501 | /* imac g5 isight */ |
| 1502 | rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; |
Alex Deucher | aa74fbb | 2010-09-07 14:41:30 -0400 | [diff] [blame] | 1503 | } else if ((rdev->pdev->device == 0x4a48) && |
| 1504 | (rdev->pdev->subsystem_vendor == 0x1002) && |
| 1505 | (rdev->pdev->subsystem_device == 0x4a48)) { |
| 1506 | /* Mac X800 */ |
| 1507 | rdev->mode_info.connector_table = CT_MAC_X800; |
Alex Deucher | 7c88d2b | 2011-06-14 15:27:38 +0000 | [diff] [blame] | 1508 | } else if ((of_machine_is_compatible("PowerMac7,2") || |
| 1509 | of_machine_is_compatible("PowerMac7,3")) && |
| 1510 | (rdev->pdev->device == 0x4150) && |
| 1511 | (rdev->pdev->subsystem_vendor == 0x1002) && |
| 1512 | (rdev->pdev->subsystem_device == 0x4150)) { |
| 1513 | /* Mac G5 tower 9600 */ |
Alex Deucher | 9fad321 | 2011-02-07 13:15:28 -0500 | [diff] [blame] | 1514 | rdev->mode_info.connector_table = CT_MAC_G5_9600; |
Alex Deucher | adaa423 | 2012-05-02 12:10:21 -0400 | [diff] [blame] | 1515 | } else if ((rdev->pdev->device == 0x4c66) && |
| 1516 | (rdev->pdev->subsystem_vendor == 0x1002) && |
| 1517 | (rdev->pdev->subsystem_device == 0x4c66)) { |
| 1518 | /* SAM440ep RV250 embedded board */ |
| 1519 | rdev->mode_info.connector_table = CT_SAM440EP; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1520 | } else |
| 1521 | #endif /* CONFIG_PPC_PMAC */ |
Dave Airlie | 76a7142 | 2010-06-11 01:09:05 -0400 | [diff] [blame] | 1522 | #ifdef CONFIG_PPC64 |
| 1523 | if (ASIC_IS_RN50(rdev)) |
| 1524 | rdev->mode_info.connector_table = CT_RN50_POWER; |
| 1525 | else |
| 1526 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1527 | rdev->mode_info.connector_table = CT_GENERIC; |
| 1528 | } |
| 1529 | |
| 1530 | switch (rdev->mode_info.connector_table) { |
| 1531 | case CT_GENERIC: |
| 1532 | DRM_INFO("Connector Table: %d (generic)\n", |
| 1533 | rdev->mode_info.connector_table); |
| 1534 | /* these are the most common settings */ |
| 1535 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
| 1536 | /* VGA - primary dac */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1537 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1538 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1539 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1540 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1541 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1542 | 1), |
| 1543 | ATOM_DEVICE_CRT1_SUPPORT); |
| 1544 | radeon_add_legacy_connector(dev, 0, |
| 1545 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1546 | DRM_MODE_CONNECTOR_VGA, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1547 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1548 | CONNECTOR_OBJECT_ID_VGA, |
| 1549 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1550 | } else if (rdev->flags & RADEON_IS_MOBILITY) { |
| 1551 | /* LVDS */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1552 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1553 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1554 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1555 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1556 | ATOM_DEVICE_LCD1_SUPPORT, |
| 1557 | 0), |
| 1558 | ATOM_DEVICE_LCD1_SUPPORT); |
| 1559 | radeon_add_legacy_connector(dev, 0, |
| 1560 | ATOM_DEVICE_LCD1_SUPPORT, |
| 1561 | DRM_MODE_CONNECTOR_LVDS, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1562 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1563 | CONNECTOR_OBJECT_ID_LVDS, |
| 1564 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1565 | |
| 1566 | /* VGA - primary dac */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1567 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1568 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1569 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1570 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1571 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1572 | 1), |
| 1573 | ATOM_DEVICE_CRT1_SUPPORT); |
| 1574 | radeon_add_legacy_connector(dev, 1, |
| 1575 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1576 | DRM_MODE_CONNECTOR_VGA, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1577 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1578 | CONNECTOR_OBJECT_ID_VGA, |
| 1579 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1580 | } else { |
| 1581 | /* DVI-I - tv dac, int tmds */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1582 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1583 | hpd.hpd = RADEON_HPD_1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1584 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1585 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1586 | ATOM_DEVICE_DFP1_SUPPORT, |
| 1587 | 0), |
| 1588 | ATOM_DEVICE_DFP1_SUPPORT); |
| 1589 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1590 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1591 | ATOM_DEVICE_CRT2_SUPPORT, |
| 1592 | 2), |
| 1593 | ATOM_DEVICE_CRT2_SUPPORT); |
| 1594 | radeon_add_legacy_connector(dev, 0, |
| 1595 | ATOM_DEVICE_DFP1_SUPPORT | |
| 1596 | ATOM_DEVICE_CRT2_SUPPORT, |
| 1597 | DRM_MODE_CONNECTOR_DVII, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1598 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1599 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 1600 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1601 | |
| 1602 | /* VGA - primary dac */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1603 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1604 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1605 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1606 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1607 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1608 | 1), |
| 1609 | ATOM_DEVICE_CRT1_SUPPORT); |
| 1610 | radeon_add_legacy_connector(dev, 1, |
| 1611 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1612 | DRM_MODE_CONNECTOR_VGA, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1613 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1614 | CONNECTOR_OBJECT_ID_VGA, |
| 1615 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1616 | } |
| 1617 | |
| 1618 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
| 1619 | /* TV - tv dac */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1620 | ddc_i2c.valid = false; |
| 1621 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1622 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1623 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1624 | ATOM_DEVICE_TV1_SUPPORT, |
| 1625 | 2), |
| 1626 | ATOM_DEVICE_TV1_SUPPORT); |
| 1627 | radeon_add_legacy_connector(dev, 2, |
| 1628 | ATOM_DEVICE_TV1_SUPPORT, |
| 1629 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1630 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1631 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1632 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1633 | } |
| 1634 | break; |
| 1635 | case CT_IBOOK: |
| 1636 | DRM_INFO("Connector Table: %d (ibook)\n", |
| 1637 | rdev->mode_info.connector_table); |
| 1638 | /* LVDS */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1639 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1640 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1641 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1642 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1643 | ATOM_DEVICE_LCD1_SUPPORT, |
| 1644 | 0), |
| 1645 | ATOM_DEVICE_LCD1_SUPPORT); |
| 1646 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1647 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1648 | CONNECTOR_OBJECT_ID_LVDS, |
| 1649 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1650 | /* VGA - TV DAC */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1651 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1652 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1653 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1654 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1655 | ATOM_DEVICE_CRT2_SUPPORT, |
| 1656 | 2), |
| 1657 | ATOM_DEVICE_CRT2_SUPPORT); |
| 1658 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1659 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1660 | CONNECTOR_OBJECT_ID_VGA, |
| 1661 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1662 | /* TV - TV DAC */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1663 | ddc_i2c.valid = false; |
| 1664 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1665 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1666 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1667 | ATOM_DEVICE_TV1_SUPPORT, |
| 1668 | 2), |
| 1669 | ATOM_DEVICE_TV1_SUPPORT); |
| 1670 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
| 1671 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1672 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1673 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1674 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1675 | break; |
| 1676 | case CT_POWERBOOK_EXTERNAL: |
| 1677 | DRM_INFO("Connector Table: %d (powerbook external tmds)\n", |
| 1678 | rdev->mode_info.connector_table); |
| 1679 | /* LVDS */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1680 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1681 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1682 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1683 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1684 | ATOM_DEVICE_LCD1_SUPPORT, |
| 1685 | 0), |
| 1686 | ATOM_DEVICE_LCD1_SUPPORT); |
| 1687 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1688 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1689 | CONNECTOR_OBJECT_ID_LVDS, |
| 1690 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1691 | /* DVI-I - primary dac, ext tmds */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1692 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1693 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1694 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1695 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1696 | ATOM_DEVICE_DFP2_SUPPORT, |
| 1697 | 0), |
| 1698 | ATOM_DEVICE_DFP2_SUPPORT); |
| 1699 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1700 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1701 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1702 | 1), |
| 1703 | ATOM_DEVICE_CRT1_SUPPORT); |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1704 | /* XXX some are SL */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1705 | radeon_add_legacy_connector(dev, 1, |
| 1706 | ATOM_DEVICE_DFP2_SUPPORT | |
| 1707 | ATOM_DEVICE_CRT1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1708 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1709 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
| 1710 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1711 | /* TV - TV DAC */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1712 | ddc_i2c.valid = false; |
| 1713 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1714 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1715 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1716 | ATOM_DEVICE_TV1_SUPPORT, |
| 1717 | 2), |
| 1718 | ATOM_DEVICE_TV1_SUPPORT); |
| 1719 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
| 1720 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1721 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1722 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1723 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1724 | break; |
| 1725 | case CT_POWERBOOK_INTERNAL: |
| 1726 | DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", |
| 1727 | rdev->mode_info.connector_table); |
| 1728 | /* LVDS */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1729 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1730 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1731 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1732 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1733 | ATOM_DEVICE_LCD1_SUPPORT, |
| 1734 | 0), |
| 1735 | ATOM_DEVICE_LCD1_SUPPORT); |
| 1736 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1737 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1738 | CONNECTOR_OBJECT_ID_LVDS, |
| 1739 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1740 | /* DVI-I - primary dac, int tmds */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1741 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1742 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1743 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1744 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1745 | ATOM_DEVICE_DFP1_SUPPORT, |
| 1746 | 0), |
| 1747 | ATOM_DEVICE_DFP1_SUPPORT); |
| 1748 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1749 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1750 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1751 | 1), |
| 1752 | ATOM_DEVICE_CRT1_SUPPORT); |
| 1753 | radeon_add_legacy_connector(dev, 1, |
| 1754 | ATOM_DEVICE_DFP1_SUPPORT | |
| 1755 | ATOM_DEVICE_CRT1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1756 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1757 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 1758 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1759 | /* TV - TV DAC */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1760 | ddc_i2c.valid = false; |
| 1761 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1762 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1763 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1764 | ATOM_DEVICE_TV1_SUPPORT, |
| 1765 | 2), |
| 1766 | ATOM_DEVICE_TV1_SUPPORT); |
| 1767 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
| 1768 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1769 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1770 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1771 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1772 | break; |
| 1773 | case CT_POWERBOOK_VGA: |
| 1774 | DRM_INFO("Connector Table: %d (powerbook vga)\n", |
| 1775 | rdev->mode_info.connector_table); |
| 1776 | /* LVDS */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1777 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1778 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1779 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1780 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1781 | ATOM_DEVICE_LCD1_SUPPORT, |
| 1782 | 0), |
| 1783 | ATOM_DEVICE_LCD1_SUPPORT); |
| 1784 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1785 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1786 | CONNECTOR_OBJECT_ID_LVDS, |
| 1787 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1788 | /* VGA - primary dac */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1789 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1790 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1791 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1792 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1793 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1794 | 1), |
| 1795 | ATOM_DEVICE_CRT1_SUPPORT); |
| 1796 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1797 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1798 | CONNECTOR_OBJECT_ID_VGA, |
| 1799 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1800 | /* TV - TV DAC */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1801 | ddc_i2c.valid = false; |
| 1802 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1803 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1804 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1805 | ATOM_DEVICE_TV1_SUPPORT, |
| 1806 | 2), |
| 1807 | ATOM_DEVICE_TV1_SUPPORT); |
| 1808 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
| 1809 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1810 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1811 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1812 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1813 | break; |
| 1814 | case CT_MINI_EXTERNAL: |
| 1815 | DRM_INFO("Connector Table: %d (mini external tmds)\n", |
| 1816 | rdev->mode_info.connector_table); |
| 1817 | /* DVI-I - tv dac, ext tmds */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1818 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1819 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1820 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1821 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1822 | ATOM_DEVICE_DFP2_SUPPORT, |
| 1823 | 0), |
| 1824 | ATOM_DEVICE_DFP2_SUPPORT); |
| 1825 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1826 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1827 | ATOM_DEVICE_CRT2_SUPPORT, |
| 1828 | 2), |
| 1829 | ATOM_DEVICE_CRT2_SUPPORT); |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1830 | /* XXX are any DL? */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1831 | radeon_add_legacy_connector(dev, 0, |
| 1832 | ATOM_DEVICE_DFP2_SUPPORT | |
| 1833 | ATOM_DEVICE_CRT2_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1834 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1835 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 1836 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1837 | /* TV - TV DAC */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1838 | ddc_i2c.valid = false; |
| 1839 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1840 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1841 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1842 | ATOM_DEVICE_TV1_SUPPORT, |
| 1843 | 2), |
| 1844 | ATOM_DEVICE_TV1_SUPPORT); |
| 1845 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
| 1846 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1847 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1848 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1849 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1850 | break; |
| 1851 | case CT_MINI_INTERNAL: |
| 1852 | DRM_INFO("Connector Table: %d (mini internal tmds)\n", |
| 1853 | rdev->mode_info.connector_table); |
| 1854 | /* DVI-I - tv dac, int tmds */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1855 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1856 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1857 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1858 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1859 | ATOM_DEVICE_DFP1_SUPPORT, |
| 1860 | 0), |
| 1861 | ATOM_DEVICE_DFP1_SUPPORT); |
| 1862 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1863 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1864 | ATOM_DEVICE_CRT2_SUPPORT, |
| 1865 | 2), |
| 1866 | ATOM_DEVICE_CRT2_SUPPORT); |
| 1867 | radeon_add_legacy_connector(dev, 0, |
| 1868 | ATOM_DEVICE_DFP1_SUPPORT | |
| 1869 | ATOM_DEVICE_CRT2_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1870 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1871 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 1872 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1873 | /* TV - TV DAC */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1874 | ddc_i2c.valid = false; |
| 1875 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1876 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1877 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1878 | ATOM_DEVICE_TV1_SUPPORT, |
| 1879 | 2), |
| 1880 | ATOM_DEVICE_TV1_SUPPORT); |
| 1881 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
| 1882 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1883 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1884 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1885 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1886 | break; |
| 1887 | case CT_IMAC_G5_ISIGHT: |
| 1888 | DRM_INFO("Connector Table: %d (imac g5 isight)\n", |
| 1889 | rdev->mode_info.connector_table); |
| 1890 | /* DVI-D - int tmds */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1891 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1892 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1893 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1894 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1895 | ATOM_DEVICE_DFP1_SUPPORT, |
| 1896 | 0), |
| 1897 | ATOM_DEVICE_DFP1_SUPPORT); |
| 1898 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1899 | DRM_MODE_CONNECTOR_DVID, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1900 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
| 1901 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1902 | /* VGA - tv dac */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1903 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1904 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1905 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1906 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1907 | ATOM_DEVICE_CRT2_SUPPORT, |
| 1908 | 2), |
| 1909 | ATOM_DEVICE_CRT2_SUPPORT); |
| 1910 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1911 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1912 | CONNECTOR_OBJECT_ID_VGA, |
| 1913 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1914 | /* TV - TV DAC */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1915 | ddc_i2c.valid = false; |
| 1916 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1917 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1918 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1919 | ATOM_DEVICE_TV1_SUPPORT, |
| 1920 | 2), |
| 1921 | ATOM_DEVICE_TV1_SUPPORT); |
| 1922 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
| 1923 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1924 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1925 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1926 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1927 | break; |
| 1928 | case CT_EMAC: |
| 1929 | DRM_INFO("Connector Table: %d (emac)\n", |
| 1930 | rdev->mode_info.connector_table); |
| 1931 | /* VGA - primary dac */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1932 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1933 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1934 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1935 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1936 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1937 | 1), |
| 1938 | ATOM_DEVICE_CRT1_SUPPORT); |
| 1939 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1940 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1941 | CONNECTOR_OBJECT_ID_VGA, |
| 1942 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1943 | /* VGA - tv dac */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1944 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1945 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1946 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1947 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1948 | ATOM_DEVICE_CRT2_SUPPORT, |
| 1949 | 2), |
| 1950 | ATOM_DEVICE_CRT2_SUPPORT); |
| 1951 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1952 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1953 | CONNECTOR_OBJECT_ID_VGA, |
| 1954 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1955 | /* TV - TV DAC */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1956 | ddc_i2c.valid = false; |
| 1957 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1958 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1959 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1960 | ATOM_DEVICE_TV1_SUPPORT, |
| 1961 | 2), |
| 1962 | ATOM_DEVICE_TV1_SUPPORT); |
| 1963 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
| 1964 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1965 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1966 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 1967 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1968 | break; |
Dave Airlie | 76a7142 | 2010-06-11 01:09:05 -0400 | [diff] [blame] | 1969 | case CT_RN50_POWER: |
| 1970 | DRM_INFO("Connector Table: %d (rn50-power)\n", |
| 1971 | rdev->mode_info.connector_table); |
| 1972 | /* VGA - primary dac */ |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1973 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Dave Airlie | 76a7142 | 2010-06-11 01:09:05 -0400 | [diff] [blame] | 1974 | hpd.hpd = RADEON_HPD_NONE; |
| 1975 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1976 | radeon_get_encoder_enum(dev, |
Dave Airlie | 76a7142 | 2010-06-11 01:09:05 -0400 | [diff] [blame] | 1977 | ATOM_DEVICE_CRT1_SUPPORT, |
| 1978 | 1), |
| 1979 | ATOM_DEVICE_CRT1_SUPPORT); |
| 1980 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
| 1981 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
| 1982 | CONNECTOR_OBJECT_ID_VGA, |
| 1983 | &hpd); |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 1984 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
Dave Airlie | 76a7142 | 2010-06-11 01:09:05 -0400 | [diff] [blame] | 1985 | hpd.hpd = RADEON_HPD_NONE; |
| 1986 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1987 | radeon_get_encoder_enum(dev, |
Dave Airlie | 76a7142 | 2010-06-11 01:09:05 -0400 | [diff] [blame] | 1988 | ATOM_DEVICE_CRT2_SUPPORT, |
| 1989 | 2), |
| 1990 | ATOM_DEVICE_CRT2_SUPPORT); |
| 1991 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
| 1992 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
| 1993 | CONNECTOR_OBJECT_ID_VGA, |
| 1994 | &hpd); |
| 1995 | break; |
Alex Deucher | aa74fbb | 2010-09-07 14:41:30 -0400 | [diff] [blame] | 1996 | case CT_MAC_X800: |
| 1997 | DRM_INFO("Connector Table: %d (mac x800)\n", |
| 1998 | rdev->mode_info.connector_table); |
| 1999 | /* DVI - primary dac, internal tmds */ |
| 2000 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
| 2001 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
| 2002 | radeon_add_legacy_encoder(dev, |
| 2003 | radeon_get_encoder_enum(dev, |
| 2004 | ATOM_DEVICE_DFP1_SUPPORT, |
| 2005 | 0), |
| 2006 | ATOM_DEVICE_DFP1_SUPPORT); |
| 2007 | radeon_add_legacy_encoder(dev, |
| 2008 | radeon_get_encoder_enum(dev, |
| 2009 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2010 | 1), |
| 2011 | ATOM_DEVICE_CRT1_SUPPORT); |
| 2012 | radeon_add_legacy_connector(dev, 0, |
| 2013 | ATOM_DEVICE_DFP1_SUPPORT | |
| 2014 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2015 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
| 2016 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 2017 | &hpd); |
| 2018 | /* DVI - tv dac, dvo */ |
| 2019 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
| 2020 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
| 2021 | radeon_add_legacy_encoder(dev, |
| 2022 | radeon_get_encoder_enum(dev, |
| 2023 | ATOM_DEVICE_DFP2_SUPPORT, |
| 2024 | 0), |
| 2025 | ATOM_DEVICE_DFP2_SUPPORT); |
| 2026 | radeon_add_legacy_encoder(dev, |
| 2027 | radeon_get_encoder_enum(dev, |
| 2028 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2029 | 2), |
| 2030 | ATOM_DEVICE_CRT2_SUPPORT); |
| 2031 | radeon_add_legacy_connector(dev, 1, |
| 2032 | ATOM_DEVICE_DFP2_SUPPORT | |
| 2033 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2034 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
| 2035 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
| 2036 | &hpd); |
| 2037 | break; |
Alex Deucher | 9fad321 | 2011-02-07 13:15:28 -0500 | [diff] [blame] | 2038 | case CT_MAC_G5_9600: |
| 2039 | DRM_INFO("Connector Table: %d (mac g5 9600)\n", |
| 2040 | rdev->mode_info.connector_table); |
| 2041 | /* DVI - tv dac, dvo */ |
| 2042 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
| 2043 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
| 2044 | radeon_add_legacy_encoder(dev, |
| 2045 | radeon_get_encoder_enum(dev, |
| 2046 | ATOM_DEVICE_DFP2_SUPPORT, |
| 2047 | 0), |
| 2048 | ATOM_DEVICE_DFP2_SUPPORT); |
| 2049 | radeon_add_legacy_encoder(dev, |
| 2050 | radeon_get_encoder_enum(dev, |
| 2051 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2052 | 2), |
| 2053 | ATOM_DEVICE_CRT2_SUPPORT); |
| 2054 | radeon_add_legacy_connector(dev, 0, |
| 2055 | ATOM_DEVICE_DFP2_SUPPORT | |
| 2056 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2057 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
| 2058 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 2059 | &hpd); |
| 2060 | /* ADC - primary dac, internal tmds */ |
| 2061 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
| 2062 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
| 2063 | radeon_add_legacy_encoder(dev, |
| 2064 | radeon_get_encoder_enum(dev, |
| 2065 | ATOM_DEVICE_DFP1_SUPPORT, |
| 2066 | 0), |
| 2067 | ATOM_DEVICE_DFP1_SUPPORT); |
| 2068 | radeon_add_legacy_encoder(dev, |
| 2069 | radeon_get_encoder_enum(dev, |
| 2070 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2071 | 1), |
| 2072 | ATOM_DEVICE_CRT1_SUPPORT); |
| 2073 | radeon_add_legacy_connector(dev, 1, |
| 2074 | ATOM_DEVICE_DFP1_SUPPORT | |
| 2075 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2076 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
| 2077 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 2078 | &hpd); |
Alex Deucher | beb4727 | 2011-04-02 09:09:08 -0400 | [diff] [blame] | 2079 | /* TV - TV DAC */ |
| 2080 | ddc_i2c.valid = false; |
| 2081 | hpd.hpd = RADEON_HPD_NONE; |
| 2082 | radeon_add_legacy_encoder(dev, |
| 2083 | radeon_get_encoder_enum(dev, |
| 2084 | ATOM_DEVICE_TV1_SUPPORT, |
| 2085 | 2), |
| 2086 | ATOM_DEVICE_TV1_SUPPORT); |
| 2087 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
| 2088 | DRM_MODE_CONNECTOR_SVIDEO, |
| 2089 | &ddc_i2c, |
| 2090 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 2091 | &hpd); |
Alex Deucher | 9fad321 | 2011-02-07 13:15:28 -0500 | [diff] [blame] | 2092 | break; |
Alex Deucher | adaa423 | 2012-05-02 12:10:21 -0400 | [diff] [blame] | 2093 | case CT_SAM440EP: |
| 2094 | DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", |
| 2095 | rdev->mode_info.connector_table); |
| 2096 | /* LVDS */ |
| 2097 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
| 2098 | hpd.hpd = RADEON_HPD_NONE; |
| 2099 | radeon_add_legacy_encoder(dev, |
| 2100 | radeon_get_encoder_enum(dev, |
| 2101 | ATOM_DEVICE_LCD1_SUPPORT, |
| 2102 | 0), |
| 2103 | ATOM_DEVICE_LCD1_SUPPORT); |
| 2104 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
| 2105 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
| 2106 | CONNECTOR_OBJECT_ID_LVDS, |
| 2107 | &hpd); |
| 2108 | /* DVI-I - secondary dac, int tmds */ |
| 2109 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
| 2110 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
| 2111 | radeon_add_legacy_encoder(dev, |
| 2112 | radeon_get_encoder_enum(dev, |
| 2113 | ATOM_DEVICE_DFP1_SUPPORT, |
| 2114 | 0), |
| 2115 | ATOM_DEVICE_DFP1_SUPPORT); |
| 2116 | radeon_add_legacy_encoder(dev, |
| 2117 | radeon_get_encoder_enum(dev, |
| 2118 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2119 | 2), |
| 2120 | ATOM_DEVICE_CRT2_SUPPORT); |
| 2121 | radeon_add_legacy_connector(dev, 1, |
| 2122 | ATOM_DEVICE_DFP1_SUPPORT | |
| 2123 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2124 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
| 2125 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 2126 | &hpd); |
| 2127 | /* VGA - primary dac */ |
| 2128 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
| 2129 | hpd.hpd = RADEON_HPD_NONE; |
| 2130 | radeon_add_legacy_encoder(dev, |
| 2131 | radeon_get_encoder_enum(dev, |
| 2132 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2133 | 1), |
| 2134 | ATOM_DEVICE_CRT1_SUPPORT); |
| 2135 | radeon_add_legacy_connector(dev, 2, |
| 2136 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2137 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
| 2138 | CONNECTOR_OBJECT_ID_VGA, |
| 2139 | &hpd); |
| 2140 | /* TV - TV DAC */ |
| 2141 | ddc_i2c.valid = false; |
| 2142 | hpd.hpd = RADEON_HPD_NONE; |
| 2143 | radeon_add_legacy_encoder(dev, |
| 2144 | radeon_get_encoder_enum(dev, |
| 2145 | ATOM_DEVICE_TV1_SUPPORT, |
| 2146 | 2), |
| 2147 | ATOM_DEVICE_TV1_SUPPORT); |
| 2148 | radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, |
| 2149 | DRM_MODE_CONNECTOR_SVIDEO, |
| 2150 | &ddc_i2c, |
| 2151 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 2152 | &hpd); |
| 2153 | break; |
Alex Deucher | ac2f952 | 2012-12-20 16:35:47 -0500 | [diff] [blame^] | 2154 | case CT_MAC_G4_SILVER: |
| 2155 | DRM_INFO("Connector Table: %d (mac g4 silver)\n", |
| 2156 | rdev->mode_info.connector_table); |
| 2157 | /* DVI-I - tv dac, int tmds */ |
| 2158 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
| 2159 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
| 2160 | radeon_add_legacy_encoder(dev, |
| 2161 | radeon_get_encoder_enum(dev, |
| 2162 | ATOM_DEVICE_DFP1_SUPPORT, |
| 2163 | 0), |
| 2164 | ATOM_DEVICE_DFP1_SUPPORT); |
| 2165 | radeon_add_legacy_encoder(dev, |
| 2166 | radeon_get_encoder_enum(dev, |
| 2167 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2168 | 2), |
| 2169 | ATOM_DEVICE_CRT2_SUPPORT); |
| 2170 | radeon_add_legacy_connector(dev, 0, |
| 2171 | ATOM_DEVICE_DFP1_SUPPORT | |
| 2172 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2173 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
| 2174 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 2175 | &hpd); |
| 2176 | /* VGA - primary dac */ |
| 2177 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
| 2178 | hpd.hpd = RADEON_HPD_NONE; |
| 2179 | radeon_add_legacy_encoder(dev, |
| 2180 | radeon_get_encoder_enum(dev, |
| 2181 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2182 | 1), |
| 2183 | ATOM_DEVICE_CRT1_SUPPORT); |
| 2184 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, |
| 2185 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
| 2186 | CONNECTOR_OBJECT_ID_VGA, |
| 2187 | &hpd); |
| 2188 | /* TV - TV DAC */ |
| 2189 | ddc_i2c.valid = false; |
| 2190 | hpd.hpd = RADEON_HPD_NONE; |
| 2191 | radeon_add_legacy_encoder(dev, |
| 2192 | radeon_get_encoder_enum(dev, |
| 2193 | ATOM_DEVICE_TV1_SUPPORT, |
| 2194 | 2), |
| 2195 | ATOM_DEVICE_TV1_SUPPORT); |
| 2196 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
| 2197 | DRM_MODE_CONNECTOR_SVIDEO, |
| 2198 | &ddc_i2c, |
| 2199 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 2200 | &hpd); |
| 2201 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2202 | default: |
| 2203 | DRM_INFO("Connector table: %d (invalid)\n", |
| 2204 | rdev->mode_info.connector_table); |
| 2205 | return false; |
| 2206 | } |
| 2207 | |
| 2208 | radeon_link_encoder_connector(dev); |
| 2209 | |
| 2210 | return true; |
| 2211 | } |
| 2212 | |
| 2213 | static bool radeon_apply_legacy_quirks(struct drm_device *dev, |
| 2214 | int bios_index, |
| 2215 | enum radeon_combios_connector |
| 2216 | *legacy_connector, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2217 | struct radeon_i2c_bus_rec *ddc_i2c, |
| 2218 | struct radeon_hpd *hpd) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2219 | { |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2220 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2221 | /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, |
| 2222 | one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ |
| 2223 | if (dev->pdev->device == 0x515e && |
| 2224 | dev->pdev->subsystem_vendor == 0x1014) { |
| 2225 | if (*legacy_connector == CONNECTOR_CRT_LEGACY && |
| 2226 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
| 2227 | return false; |
| 2228 | } |
| 2229 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2230 | /* X300 card with extra non-existent DVI port */ |
| 2231 | if (dev->pdev->device == 0x5B60 && |
| 2232 | dev->pdev->subsystem_vendor == 0x17af && |
| 2233 | dev->pdev->subsystem_device == 0x201e && bios_index == 2) { |
| 2234 | if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) |
| 2235 | return false; |
| 2236 | } |
| 2237 | |
| 2238 | return true; |
| 2239 | } |
| 2240 | |
Alex Deucher | 790cfb3 | 2009-10-15 23:26:09 -0400 | [diff] [blame] | 2241 | static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) |
| 2242 | { |
| 2243 | /* Acer 5102 has non-existent TV port */ |
| 2244 | if (dev->pdev->device == 0x5975 && |
| 2245 | dev->pdev->subsystem_vendor == 0x1025 && |
| 2246 | dev->pdev->subsystem_device == 0x009f) |
| 2247 | return false; |
| 2248 | |
Alex Deucher | fc7f711 | 2009-10-28 01:46:54 -0400 | [diff] [blame] | 2249 | /* HP dc5750 has non-existent TV port */ |
| 2250 | if (dev->pdev->device == 0x5974 && |
| 2251 | dev->pdev->subsystem_vendor == 0x103c && |
| 2252 | dev->pdev->subsystem_device == 0x280a) |
| 2253 | return false; |
| 2254 | |
Alex Deucher | fd874ad | 2009-11-16 18:33:51 -0500 | [diff] [blame] | 2255 | /* MSI S270 has non-existent TV port */ |
| 2256 | if (dev->pdev->device == 0x5955 && |
| 2257 | dev->pdev->subsystem_vendor == 0x1462 && |
| 2258 | dev->pdev->subsystem_device == 0x0131) |
| 2259 | return false; |
| 2260 | |
Alex Deucher | 790cfb3 | 2009-10-15 23:26:09 -0400 | [diff] [blame] | 2261 | return true; |
| 2262 | } |
| 2263 | |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2264 | static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) |
| 2265 | { |
| 2266 | struct radeon_device *rdev = dev->dev_private; |
| 2267 | uint32_t ext_tmds_info; |
| 2268 | |
| 2269 | if (rdev->flags & RADEON_IS_IGP) { |
| 2270 | if (is_dvi_d) |
| 2271 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
| 2272 | else |
| 2273 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
| 2274 | } |
| 2275 | ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
| 2276 | if (ext_tmds_info) { |
| 2277 | uint8_t rev = RBIOS8(ext_tmds_info); |
| 2278 | uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); |
| 2279 | if (rev >= 3) { |
| 2280 | if (is_dvi_d) |
| 2281 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
| 2282 | else |
| 2283 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
| 2284 | } else { |
| 2285 | if (flags & 1) { |
| 2286 | if (is_dvi_d) |
| 2287 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
| 2288 | else |
| 2289 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
| 2290 | } |
| 2291 | } |
| 2292 | } |
| 2293 | if (is_dvi_d) |
| 2294 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
| 2295 | else |
| 2296 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
| 2297 | } |
| 2298 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2299 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) |
| 2300 | { |
| 2301 | struct radeon_device *rdev = dev->dev_private; |
| 2302 | uint32_t conn_info, entry, devices; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2303 | uint16_t tmp, connector_object_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2304 | enum radeon_combios_ddc ddc_type; |
| 2305 | enum radeon_combios_connector connector; |
| 2306 | int i = 0; |
| 2307 | struct radeon_i2c_bus_rec ddc_i2c; |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2308 | struct radeon_hpd hpd; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2309 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2310 | conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); |
| 2311 | if (conn_info) { |
| 2312 | for (i = 0; i < 4; i++) { |
| 2313 | entry = conn_info + 2 + i * 2; |
| 2314 | |
| 2315 | if (!RBIOS16(entry)) |
| 2316 | break; |
| 2317 | |
| 2318 | tmp = RBIOS16(entry); |
| 2319 | |
| 2320 | connector = (tmp >> 12) & 0xf; |
| 2321 | |
| 2322 | ddc_type = (tmp >> 8) & 0xf; |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 2323 | ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2324 | |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2325 | switch (connector) { |
| 2326 | case CONNECTOR_PROPRIETARY_LEGACY: |
| 2327 | case CONNECTOR_DVI_I_LEGACY: |
| 2328 | case CONNECTOR_DVI_D_LEGACY: |
| 2329 | if ((tmp >> 4) & 0x1) |
| 2330 | hpd.hpd = RADEON_HPD_2; |
| 2331 | else |
| 2332 | hpd.hpd = RADEON_HPD_1; |
| 2333 | break; |
| 2334 | default: |
| 2335 | hpd.hpd = RADEON_HPD_NONE; |
| 2336 | break; |
| 2337 | } |
| 2338 | |
Alex Deucher | 2d152c6 | 2009-10-15 23:08:05 -0400 | [diff] [blame] | 2339 | if (!radeon_apply_legacy_quirks(dev, i, &connector, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2340 | &ddc_i2c, &hpd)) |
Alex Deucher | 2d152c6 | 2009-10-15 23:08:05 -0400 | [diff] [blame] | 2341 | continue; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2342 | |
| 2343 | switch (connector) { |
| 2344 | case CONNECTOR_PROPRIETARY_LEGACY: |
| 2345 | if ((tmp >> 4) & 0x1) |
| 2346 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
| 2347 | else |
| 2348 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
| 2349 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2350 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2351 | (dev, devices, 0), |
| 2352 | devices); |
| 2353 | radeon_add_legacy_connector(dev, i, devices, |
| 2354 | legacy_connector_convert |
| 2355 | [connector], |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2356 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2357 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
| 2358 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2359 | break; |
| 2360 | case CONNECTOR_CRT_LEGACY: |
| 2361 | if (tmp & 0x1) { |
| 2362 | devices = ATOM_DEVICE_CRT2_SUPPORT; |
| 2363 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2364 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2365 | (dev, |
| 2366 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2367 | 2), |
| 2368 | ATOM_DEVICE_CRT2_SUPPORT); |
| 2369 | } else { |
| 2370 | devices = ATOM_DEVICE_CRT1_SUPPORT; |
| 2371 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2372 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2373 | (dev, |
| 2374 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2375 | 1), |
| 2376 | ATOM_DEVICE_CRT1_SUPPORT); |
| 2377 | } |
| 2378 | radeon_add_legacy_connector(dev, |
| 2379 | i, |
| 2380 | devices, |
| 2381 | legacy_connector_convert |
| 2382 | [connector], |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2383 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2384 | CONNECTOR_OBJECT_ID_VGA, |
| 2385 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2386 | break; |
| 2387 | case CONNECTOR_DVI_I_LEGACY: |
| 2388 | devices = 0; |
| 2389 | if (tmp & 0x1) { |
| 2390 | devices |= ATOM_DEVICE_CRT2_SUPPORT; |
| 2391 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2392 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2393 | (dev, |
| 2394 | ATOM_DEVICE_CRT2_SUPPORT, |
| 2395 | 2), |
| 2396 | ATOM_DEVICE_CRT2_SUPPORT); |
| 2397 | } else { |
| 2398 | devices |= ATOM_DEVICE_CRT1_SUPPORT; |
| 2399 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2400 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2401 | (dev, |
| 2402 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2403 | 1), |
| 2404 | ATOM_DEVICE_CRT1_SUPPORT); |
| 2405 | } |
Alex Deucher | d96c908 | 2013-01-29 16:36:47 -0500 | [diff] [blame] | 2406 | /* RV100 board with external TDMS bit mis-set. |
| 2407 | * Actually uses internal TMDS, clear the bit. |
| 2408 | */ |
| 2409 | if (dev->pdev->device == 0x5159 && |
| 2410 | dev->pdev->subsystem_vendor == 0x1014 && |
| 2411 | dev->pdev->subsystem_device == 0x029A) { |
| 2412 | tmp &= ~(1 << 4); |
| 2413 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2414 | if ((tmp >> 4) & 0x1) { |
| 2415 | devices |= ATOM_DEVICE_DFP2_SUPPORT; |
| 2416 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2417 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2418 | (dev, |
| 2419 | ATOM_DEVICE_DFP2_SUPPORT, |
| 2420 | 0), |
| 2421 | ATOM_DEVICE_DFP2_SUPPORT); |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2422 | connector_object_id = combios_check_dl_dvi(dev, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2423 | } else { |
| 2424 | devices |= ATOM_DEVICE_DFP1_SUPPORT; |
| 2425 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2426 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2427 | (dev, |
| 2428 | ATOM_DEVICE_DFP1_SUPPORT, |
| 2429 | 0), |
| 2430 | ATOM_DEVICE_DFP1_SUPPORT); |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2431 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2432 | } |
| 2433 | radeon_add_legacy_connector(dev, |
| 2434 | i, |
| 2435 | devices, |
| 2436 | legacy_connector_convert |
| 2437 | [connector], |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2438 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2439 | connector_object_id, |
| 2440 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2441 | break; |
| 2442 | case CONNECTOR_DVI_D_LEGACY: |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2443 | if ((tmp >> 4) & 0x1) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2444 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2445 | connector_object_id = combios_check_dl_dvi(dev, 1); |
| 2446 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2447 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2448 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
| 2449 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2450 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2451 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2452 | (dev, devices, 0), |
| 2453 | devices); |
| 2454 | radeon_add_legacy_connector(dev, i, devices, |
| 2455 | legacy_connector_convert |
| 2456 | [connector], |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2457 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2458 | connector_object_id, |
| 2459 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2460 | break; |
| 2461 | case CONNECTOR_CTV_LEGACY: |
| 2462 | case CONNECTOR_STV_LEGACY: |
| 2463 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2464 | radeon_get_encoder_enum |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2465 | (dev, |
| 2466 | ATOM_DEVICE_TV1_SUPPORT, |
| 2467 | 2), |
| 2468 | ATOM_DEVICE_TV1_SUPPORT); |
| 2469 | radeon_add_legacy_connector(dev, i, |
| 2470 | ATOM_DEVICE_TV1_SUPPORT, |
| 2471 | legacy_connector_convert |
| 2472 | [connector], |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2473 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2474 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 2475 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2476 | break; |
| 2477 | default: |
| 2478 | DRM_ERROR("Unknown connector type: %d\n", |
| 2479 | connector); |
| 2480 | continue; |
| 2481 | } |
| 2482 | |
| 2483 | } |
| 2484 | } else { |
| 2485 | uint16_t tmds_info = |
| 2486 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
| 2487 | if (tmds_info) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2488 | DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2489 | |
| 2490 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2491 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2492 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2493 | 1), |
| 2494 | ATOM_DEVICE_CRT1_SUPPORT); |
| 2495 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2496 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2497 | ATOM_DEVICE_DFP1_SUPPORT, |
| 2498 | 0), |
| 2499 | ATOM_DEVICE_DFP1_SUPPORT); |
| 2500 | |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 2501 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
Alex Deucher | 8e36ed0 | 2010-05-18 19:26:47 -0400 | [diff] [blame] | 2502 | hpd.hpd = RADEON_HPD_1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2503 | radeon_add_legacy_connector(dev, |
| 2504 | 0, |
| 2505 | ATOM_DEVICE_CRT1_SUPPORT | |
| 2506 | ATOM_DEVICE_DFP1_SUPPORT, |
| 2507 | DRM_MODE_CONNECTOR_DVII, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2508 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2509 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
| 2510 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2511 | } else { |
Alex Deucher | d0c403e | 2009-10-15 23:38:32 -0400 | [diff] [blame] | 2512 | uint16_t crt_info = |
| 2513 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2514 | DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); |
Alex Deucher | d0c403e | 2009-10-15 23:38:32 -0400 | [diff] [blame] | 2515 | if (crt_info) { |
| 2516 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2517 | radeon_get_encoder_enum(dev, |
Alex Deucher | d0c403e | 2009-10-15 23:38:32 -0400 | [diff] [blame] | 2518 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2519 | 1), |
| 2520 | ATOM_DEVICE_CRT1_SUPPORT); |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 2521 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2522 | hpd.hpd = RADEON_HPD_NONE; |
Alex Deucher | d0c403e | 2009-10-15 23:38:32 -0400 | [diff] [blame] | 2523 | radeon_add_legacy_connector(dev, |
| 2524 | 0, |
| 2525 | ATOM_DEVICE_CRT1_SUPPORT, |
| 2526 | DRM_MODE_CONNECTOR_VGA, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2527 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2528 | CONNECTOR_OBJECT_ID_VGA, |
| 2529 | &hpd); |
Alex Deucher | d0c403e | 2009-10-15 23:38:32 -0400 | [diff] [blame] | 2530 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2531 | DRM_DEBUG_KMS("No connector info found\n"); |
Alex Deucher | d0c403e | 2009-10-15 23:38:32 -0400 | [diff] [blame] | 2532 | return false; |
| 2533 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2534 | } |
| 2535 | } |
| 2536 | |
| 2537 | if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { |
| 2538 | uint16_t lcd_info = |
| 2539 | combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
| 2540 | if (lcd_info) { |
| 2541 | uint16_t lcd_ddc_info = |
| 2542 | combios_get_table_offset(dev, |
| 2543 | COMBIOS_LCD_DDC_INFO_TABLE); |
| 2544 | |
| 2545 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2546 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2547 | ATOM_DEVICE_LCD1_SUPPORT, |
| 2548 | 0), |
| 2549 | ATOM_DEVICE_LCD1_SUPPORT); |
| 2550 | |
| 2551 | if (lcd_ddc_info) { |
| 2552 | ddc_type = RBIOS8(lcd_ddc_info + 2); |
| 2553 | switch (ddc_type) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2554 | case DDC_LCD: |
| 2555 | ddc_i2c = |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 2556 | combios_setup_i2c_bus(rdev, |
| 2557 | DDC_LCD, |
| 2558 | RBIOS32(lcd_ddc_info + 3), |
| 2559 | RBIOS32(lcd_ddc_info + 7)); |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 2560 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2561 | break; |
| 2562 | case DDC_GPIO: |
| 2563 | ddc_i2c = |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 2564 | combios_setup_i2c_bus(rdev, |
| 2565 | DDC_GPIO, |
| 2566 | RBIOS32(lcd_ddc_info + 3), |
| 2567 | RBIOS32(lcd_ddc_info + 7)); |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 2568 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2569 | break; |
| 2570 | default: |
Alex Deucher | 179e807 | 2010-08-05 21:21:17 -0400 | [diff] [blame] | 2571 | ddc_i2c = |
| 2572 | combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2573 | break; |
| 2574 | } |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2575 | DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2576 | } else |
| 2577 | ddc_i2c.valid = false; |
| 2578 | |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2579 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2580 | radeon_add_legacy_connector(dev, |
| 2581 | 5, |
| 2582 | ATOM_DEVICE_LCD1_SUPPORT, |
| 2583 | DRM_MODE_CONNECTOR_LVDS, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2584 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2585 | CONNECTOR_OBJECT_ID_LVDS, |
| 2586 | &hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2587 | } |
| 2588 | } |
| 2589 | |
| 2590 | /* check TV table */ |
| 2591 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
| 2592 | uint32_t tv_info = |
| 2593 | combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
| 2594 | if (tv_info) { |
| 2595 | if (RBIOS8(tv_info + 6) == 'T') { |
Alex Deucher | 790cfb3 | 2009-10-15 23:26:09 -0400 | [diff] [blame] | 2596 | if (radeon_apply_legacy_tv_quirks(dev)) { |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2597 | hpd.hpd = RADEON_HPD_NONE; |
Dave Airlie | d294ed6 | 2010-06-08 13:04:50 +1000 | [diff] [blame] | 2598 | ddc_i2c.valid = false; |
Alex Deucher | 790cfb3 | 2009-10-15 23:26:09 -0400 | [diff] [blame] | 2599 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 2600 | radeon_get_encoder_enum |
Alex Deucher | 790cfb3 | 2009-10-15 23:26:09 -0400 | [diff] [blame] | 2601 | (dev, |
| 2602 | ATOM_DEVICE_TV1_SUPPORT, |
| 2603 | 2), |
| 2604 | ATOM_DEVICE_TV1_SUPPORT); |
| 2605 | radeon_add_legacy_connector(dev, 6, |
| 2606 | ATOM_DEVICE_TV1_SUPPORT, |
| 2607 | DRM_MODE_CONNECTOR_SVIDEO, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 2608 | &ddc_i2c, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 2609 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 2610 | &hpd); |
Alex Deucher | 790cfb3 | 2009-10-15 23:26:09 -0400 | [diff] [blame] | 2611 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2612 | } |
| 2613 | } |
| 2614 | } |
| 2615 | |
| 2616 | radeon_link_encoder_connector(dev); |
| 2617 | |
| 2618 | return true; |
| 2619 | } |
| 2620 | |
Alex Deucher | 63f7d98 | 2011-05-03 12:44:54 -0400 | [diff] [blame] | 2621 | static const char *thermal_controller_names[] = { |
| 2622 | "NONE", |
| 2623 | "lm63", |
| 2624 | "adm1032", |
| 2625 | }; |
| 2626 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2627 | void radeon_combios_get_power_modes(struct radeon_device *rdev) |
| 2628 | { |
| 2629 | struct drm_device *dev = rdev->ddev; |
| 2630 | u16 offset, misc, misc2 = 0; |
| 2631 | u8 rev, blocks, tmp; |
| 2632 | int state_index = 0; |
Alex Deucher | c41b9ee | 2011-07-30 18:12:24 +0000 | [diff] [blame] | 2633 | struct radeon_i2c_bus_rec i2c_bus; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2634 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 2635 | rdev->pm.default_power_state_index = -1; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2636 | |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 2637 | /* allocate 2 power states */ |
| 2638 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); |
Alex Deucher | a7c36fd | 2011-11-12 11:57:29 -0500 | [diff] [blame] | 2639 | if (rdev->pm.power_state) { |
| 2640 | /* allocate 1 clock mode per state */ |
| 2641 | rdev->pm.power_state[0].clock_info = |
| 2642 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
| 2643 | rdev->pm.power_state[1].clock_info = |
| 2644 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
| 2645 | if (!rdev->pm.power_state[0].clock_info || |
| 2646 | !rdev->pm.power_state[1].clock_info) |
| 2647 | goto pm_failed; |
| 2648 | } else |
| 2649 | goto pm_failed; |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 2650 | |
Alex Deucher | 63f7d98 | 2011-05-03 12:44:54 -0400 | [diff] [blame] | 2651 | /* check for a thermal chip */ |
| 2652 | offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); |
| 2653 | if (offset) { |
| 2654 | u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; |
Alex Deucher | 63f7d98 | 2011-05-03 12:44:54 -0400 | [diff] [blame] | 2655 | |
| 2656 | rev = RBIOS8(offset); |
| 2657 | |
| 2658 | if (rev == 0) { |
| 2659 | thermal_controller = RBIOS8(offset + 3); |
| 2660 | gpio = RBIOS8(offset + 4) & 0x3f; |
| 2661 | i2c_addr = RBIOS8(offset + 5); |
| 2662 | } else if (rev == 1) { |
| 2663 | thermal_controller = RBIOS8(offset + 4); |
| 2664 | gpio = RBIOS8(offset + 5) & 0x3f; |
| 2665 | i2c_addr = RBIOS8(offset + 6); |
| 2666 | } else if (rev == 2) { |
| 2667 | thermal_controller = RBIOS8(offset + 4); |
| 2668 | gpio = RBIOS8(offset + 5) & 0x3f; |
| 2669 | i2c_addr = RBIOS8(offset + 6); |
| 2670 | clk_bit = RBIOS8(offset + 0xa); |
| 2671 | data_bit = RBIOS8(offset + 0xb); |
| 2672 | } |
| 2673 | if ((thermal_controller > 0) && (thermal_controller < 3)) { |
| 2674 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
| 2675 | thermal_controller_names[thermal_controller], |
| 2676 | i2c_addr >> 1); |
| 2677 | if (gpio == DDC_LCD) { |
| 2678 | /* MM i2c */ |
| 2679 | i2c_bus.valid = true; |
| 2680 | i2c_bus.hw_capable = true; |
| 2681 | i2c_bus.mm_i2c = true; |
| 2682 | i2c_bus.i2c_id = 0xa0; |
| 2683 | } else if (gpio == DDC_GPIO) |
| 2684 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); |
| 2685 | else |
| 2686 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
| 2687 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
| 2688 | if (rdev->pm.i2c_bus) { |
| 2689 | struct i2c_board_info info = { }; |
| 2690 | const char *name = thermal_controller_names[thermal_controller]; |
| 2691 | info.addr = i2c_addr >> 1; |
| 2692 | strlcpy(info.type, name, sizeof(info.type)); |
| 2693 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
| 2694 | } |
| 2695 | } |
Alex Deucher | c41b9ee | 2011-07-30 18:12:24 +0000 | [diff] [blame] | 2696 | } else { |
| 2697 | /* boards with a thermal chip, but no overdrive table */ |
| 2698 | |
| 2699 | /* Asus 9600xt has an f75375 on the monid bus */ |
| 2700 | if ((dev->pdev->device == 0x4152) && |
| 2701 | (dev->pdev->subsystem_vendor == 0x1043) && |
| 2702 | (dev->pdev->subsystem_device == 0xc002)) { |
| 2703 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
| 2704 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
| 2705 | if (rdev->pm.i2c_bus) { |
| 2706 | struct i2c_board_info info = { }; |
| 2707 | const char *name = "f75375"; |
| 2708 | info.addr = 0x28; |
| 2709 | strlcpy(info.type, name, sizeof(info.type)); |
| 2710 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
| 2711 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
| 2712 | name, info.addr); |
| 2713 | } |
| 2714 | } |
Alex Deucher | 63f7d98 | 2011-05-03 12:44:54 -0400 | [diff] [blame] | 2715 | } |
| 2716 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2717 | if (rdev->flags & RADEON_IS_MOBILITY) { |
| 2718 | offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); |
| 2719 | if (offset) { |
| 2720 | rev = RBIOS8(offset); |
| 2721 | blocks = RBIOS8(offset + 0x2); |
| 2722 | /* power mode 0 tends to be the only valid one */ |
| 2723 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
| 2724 | rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); |
| 2725 | rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); |
| 2726 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
| 2727 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
| 2728 | goto default_mode; |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 2729 | rdev->pm.power_state[state_index].type = |
| 2730 | POWER_STATE_TYPE_BATTERY; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2731 | misc = RBIOS16(offset + 0x5 + 0x0); |
| 2732 | if (rev > 4) |
| 2733 | misc2 = RBIOS16(offset + 0x5 + 0xe); |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 2734 | rdev->pm.power_state[state_index].misc = misc; |
| 2735 | rdev->pm.power_state[state_index].misc2 = misc2; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2736 | if (misc & 0x4) { |
| 2737 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; |
| 2738 | if (misc & 0x8) |
| 2739 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
| 2740 | true; |
| 2741 | else |
| 2742 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
| 2743 | false; |
| 2744 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; |
| 2745 | if (rev < 6) { |
| 2746 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = |
| 2747 | RBIOS16(offset + 0x5 + 0xb) * 4; |
| 2748 | tmp = RBIOS8(offset + 0x5 + 0xd); |
| 2749 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); |
| 2750 | } else { |
| 2751 | u8 entries = RBIOS8(offset + 0x5 + 0xb); |
| 2752 | u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); |
| 2753 | if (entries && voltage_table_offset) { |
| 2754 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = |
| 2755 | RBIOS16(voltage_table_offset) * 4; |
| 2756 | tmp = RBIOS8(voltage_table_offset + 0x2); |
| 2757 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); |
| 2758 | } else |
| 2759 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; |
| 2760 | } |
| 2761 | switch ((misc2 & 0x700) >> 8) { |
| 2762 | case 0: |
| 2763 | default: |
| 2764 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; |
| 2765 | break; |
| 2766 | case 1: |
| 2767 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; |
| 2768 | break; |
| 2769 | case 2: |
| 2770 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; |
| 2771 | break; |
| 2772 | case 3: |
| 2773 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; |
| 2774 | break; |
| 2775 | case 4: |
| 2776 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; |
| 2777 | break; |
| 2778 | } |
| 2779 | } else |
| 2780 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
| 2781 | if (rev > 6) |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 2782 | rdev->pm.power_state[state_index].pcie_lanes = |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2783 | RBIOS8(offset + 0x5 + 0x10); |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 2784 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2785 | state_index++; |
| 2786 | } else { |
| 2787 | /* XXX figure out some good default low power mode for mobility cards w/out power tables */ |
| 2788 | } |
| 2789 | } else { |
| 2790 | /* XXX figure out some good default low power mode for desktop cards */ |
| 2791 | } |
| 2792 | |
| 2793 | default_mode: |
| 2794 | /* add the default mode */ |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 2795 | rdev->pm.power_state[state_index].type = |
| 2796 | POWER_STATE_TYPE_DEFAULT; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2797 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
| 2798 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
| 2799 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
| 2800 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; |
Alex Deucher | 84d88f4 | 2010-05-27 17:01:42 -0400 | [diff] [blame] | 2801 | if ((state_index > 0) && |
Alex Deucher | 8de016e | 2010-06-03 21:28:23 -0400 | [diff] [blame] | 2802 | (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) |
Alex Deucher | 84d88f4 | 2010-05-27 17:01:42 -0400 | [diff] [blame] | 2803 | rdev->pm.power_state[state_index].clock_info[0].voltage = |
| 2804 | rdev->pm.power_state[0].clock_info[0].voltage; |
| 2805 | else |
| 2806 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 2807 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 2808 | rdev->pm.power_state[state_index].flags = 0; |
| 2809 | rdev->pm.default_power_state_index = state_index; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2810 | rdev->pm.num_power_states = state_index + 1; |
Rafał Miłecki | 9038dfd | 2010-02-20 23:15:04 +0000 | [diff] [blame] | 2811 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 2812 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
| 2813 | rdev->pm.current_clock_mode_index = 0; |
Alex Deucher | a7c36fd | 2011-11-12 11:57:29 -0500 | [diff] [blame] | 2814 | return; |
| 2815 | |
| 2816 | pm_failed: |
| 2817 | rdev->pm.default_power_state_index = state_index; |
| 2818 | rdev->pm.num_power_states = 0; |
| 2819 | |
| 2820 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
| 2821 | rdev->pm.current_clock_mode_index = 0; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2822 | } |
| 2823 | |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2824 | void radeon_external_tmds_setup(struct drm_encoder *encoder) |
| 2825 | { |
| 2826 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2827 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
| 2828 | |
| 2829 | if (!tmds) |
| 2830 | return; |
| 2831 | |
| 2832 | switch (tmds->dvo_chip) { |
| 2833 | case DVO_SIL164: |
| 2834 | /* sil 164 */ |
Alex Deucher | 5a6f98f | 2009-12-22 15:04:48 -0500 | [diff] [blame] | 2835 | radeon_i2c_put_byte(tmds->i2c_bus, |
| 2836 | tmds->slave_addr, |
| 2837 | 0x08, 0x30); |
| 2838 | radeon_i2c_put_byte(tmds->i2c_bus, |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2839 | tmds->slave_addr, |
| 2840 | 0x09, 0x00); |
Alex Deucher | 5a6f98f | 2009-12-22 15:04:48 -0500 | [diff] [blame] | 2841 | radeon_i2c_put_byte(tmds->i2c_bus, |
| 2842 | tmds->slave_addr, |
| 2843 | 0x0a, 0x90); |
| 2844 | radeon_i2c_put_byte(tmds->i2c_bus, |
| 2845 | tmds->slave_addr, |
| 2846 | 0x0c, 0x89); |
| 2847 | radeon_i2c_put_byte(tmds->i2c_bus, |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2848 | tmds->slave_addr, |
| 2849 | 0x08, 0x3b); |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2850 | break; |
| 2851 | case DVO_SIL1178: |
| 2852 | /* sil 1178 - untested */ |
| 2853 | /* |
| 2854 | * 0x0f, 0x44 |
| 2855 | * 0x0f, 0x4c |
| 2856 | * 0x0e, 0x01 |
| 2857 | * 0x0a, 0x80 |
| 2858 | * 0x09, 0x30 |
| 2859 | * 0x0c, 0xc9 |
| 2860 | * 0x0d, 0x70 |
| 2861 | * 0x08, 0x32 |
| 2862 | * 0x08, 0x33 |
| 2863 | */ |
| 2864 | break; |
| 2865 | default: |
| 2866 | break; |
| 2867 | } |
| 2868 | |
| 2869 | } |
| 2870 | |
| 2871 | bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) |
| 2872 | { |
| 2873 | struct drm_device *dev = encoder->dev; |
| 2874 | struct radeon_device *rdev = dev->dev_private; |
| 2875 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2876 | uint16_t offset; |
| 2877 | uint8_t blocks, slave_addr, rev; |
| 2878 | uint32_t index, id; |
| 2879 | uint32_t reg, val, and_mask, or_mask; |
| 2880 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
| 2881 | |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2882 | if (!tmds) |
| 2883 | return false; |
| 2884 | |
| 2885 | if (rdev->flags & RADEON_IS_IGP) { |
| 2886 | offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); |
| 2887 | rev = RBIOS8(offset); |
| 2888 | if (offset) { |
| 2889 | rev = RBIOS8(offset); |
| 2890 | if (rev > 1) { |
| 2891 | blocks = RBIOS8(offset + 3); |
| 2892 | index = offset + 4; |
| 2893 | while (blocks > 0) { |
| 2894 | id = RBIOS16(index); |
| 2895 | index += 2; |
| 2896 | switch (id >> 13) { |
| 2897 | case 0: |
| 2898 | reg = (id & 0x1fff) * 4; |
| 2899 | val = RBIOS32(index); |
| 2900 | index += 4; |
| 2901 | WREG32(reg, val); |
| 2902 | break; |
| 2903 | case 2: |
| 2904 | reg = (id & 0x1fff) * 4; |
| 2905 | and_mask = RBIOS32(index); |
| 2906 | index += 4; |
| 2907 | or_mask = RBIOS32(index); |
| 2908 | index += 4; |
| 2909 | val = RREG32(reg); |
| 2910 | val = (val & and_mask) | or_mask; |
| 2911 | WREG32(reg, val); |
| 2912 | break; |
| 2913 | case 3: |
| 2914 | val = RBIOS16(index); |
| 2915 | index += 2; |
| 2916 | udelay(val); |
| 2917 | break; |
| 2918 | case 4: |
| 2919 | val = RBIOS16(index); |
| 2920 | index += 2; |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 2921 | mdelay(val); |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2922 | break; |
| 2923 | case 6: |
| 2924 | slave_addr = id & 0xff; |
| 2925 | slave_addr >>= 1; /* 7 bit addressing */ |
| 2926 | index++; |
| 2927 | reg = RBIOS8(index); |
| 2928 | index++; |
| 2929 | val = RBIOS8(index); |
| 2930 | index++; |
Alex Deucher | 5a6f98f | 2009-12-22 15:04:48 -0500 | [diff] [blame] | 2931 | radeon_i2c_put_byte(tmds->i2c_bus, |
| 2932 | slave_addr, |
| 2933 | reg, val); |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2934 | break; |
| 2935 | default: |
| 2936 | DRM_ERROR("Unknown id %d\n", id >> 13); |
| 2937 | break; |
| 2938 | } |
| 2939 | blocks--; |
| 2940 | } |
| 2941 | return true; |
| 2942 | } |
| 2943 | } |
| 2944 | } else { |
| 2945 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
| 2946 | if (offset) { |
| 2947 | index = offset + 10; |
| 2948 | id = RBIOS16(index); |
| 2949 | while (id != 0xffff) { |
| 2950 | index += 2; |
| 2951 | switch (id >> 13) { |
| 2952 | case 0: |
| 2953 | reg = (id & 0x1fff) * 4; |
| 2954 | val = RBIOS32(index); |
| 2955 | WREG32(reg, val); |
| 2956 | break; |
| 2957 | case 2: |
| 2958 | reg = (id & 0x1fff) * 4; |
| 2959 | and_mask = RBIOS32(index); |
| 2960 | index += 4; |
| 2961 | or_mask = RBIOS32(index); |
| 2962 | index += 4; |
| 2963 | val = RREG32(reg); |
| 2964 | val = (val & and_mask) | or_mask; |
| 2965 | WREG32(reg, val); |
| 2966 | break; |
| 2967 | case 4: |
| 2968 | val = RBIOS16(index); |
| 2969 | index += 2; |
| 2970 | udelay(val); |
| 2971 | break; |
| 2972 | case 5: |
| 2973 | reg = id & 0x1fff; |
| 2974 | and_mask = RBIOS32(index); |
| 2975 | index += 4; |
| 2976 | or_mask = RBIOS32(index); |
| 2977 | index += 4; |
| 2978 | val = RREG32_PLL(reg); |
| 2979 | val = (val & and_mask) | or_mask; |
| 2980 | WREG32_PLL(reg, val); |
| 2981 | break; |
| 2982 | case 6: |
| 2983 | reg = id & 0x1fff; |
| 2984 | val = RBIOS8(index); |
| 2985 | index += 1; |
Alex Deucher | 5a6f98f | 2009-12-22 15:04:48 -0500 | [diff] [blame] | 2986 | radeon_i2c_put_byte(tmds->i2c_bus, |
| 2987 | tmds->slave_addr, |
| 2988 | reg, val); |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 2989 | break; |
| 2990 | default: |
| 2991 | DRM_ERROR("Unknown id %d\n", id >> 13); |
| 2992 | break; |
| 2993 | } |
| 2994 | id = RBIOS16(index); |
| 2995 | } |
| 2996 | return true; |
| 2997 | } |
| 2998 | } |
| 2999 | return false; |
| 3000 | } |
| 3001 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3002 | static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) |
| 3003 | { |
| 3004 | struct radeon_device *rdev = dev->dev_private; |
| 3005 | |
| 3006 | if (offset) { |
| 3007 | while (RBIOS16(offset)) { |
| 3008 | uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); |
| 3009 | uint32_t addr = (RBIOS16(offset) & 0x1fff); |
| 3010 | uint32_t val, and_mask, or_mask; |
| 3011 | uint32_t tmp; |
| 3012 | |
| 3013 | offset += 2; |
| 3014 | switch (cmd) { |
| 3015 | case 0: |
| 3016 | val = RBIOS32(offset); |
| 3017 | offset += 4; |
| 3018 | WREG32(addr, val); |
| 3019 | break; |
| 3020 | case 1: |
| 3021 | val = RBIOS32(offset); |
| 3022 | offset += 4; |
| 3023 | WREG32(addr, val); |
| 3024 | break; |
| 3025 | case 2: |
| 3026 | and_mask = RBIOS32(offset); |
| 3027 | offset += 4; |
| 3028 | or_mask = RBIOS32(offset); |
| 3029 | offset += 4; |
| 3030 | tmp = RREG32(addr); |
| 3031 | tmp &= and_mask; |
| 3032 | tmp |= or_mask; |
| 3033 | WREG32(addr, tmp); |
| 3034 | break; |
| 3035 | case 3: |
| 3036 | and_mask = RBIOS32(offset); |
| 3037 | offset += 4; |
| 3038 | or_mask = RBIOS32(offset); |
| 3039 | offset += 4; |
| 3040 | tmp = RREG32(addr); |
| 3041 | tmp &= and_mask; |
| 3042 | tmp |= or_mask; |
| 3043 | WREG32(addr, tmp); |
| 3044 | break; |
| 3045 | case 4: |
| 3046 | val = RBIOS16(offset); |
| 3047 | offset += 2; |
| 3048 | udelay(val); |
| 3049 | break; |
| 3050 | case 5: |
| 3051 | val = RBIOS16(offset); |
| 3052 | offset += 2; |
| 3053 | switch (addr) { |
| 3054 | case 8: |
| 3055 | while (val--) { |
| 3056 | if (! |
| 3057 | (RREG32_PLL |
| 3058 | (RADEON_CLK_PWRMGT_CNTL) & |
| 3059 | RADEON_MC_BUSY)) |
| 3060 | break; |
| 3061 | } |
| 3062 | break; |
| 3063 | case 9: |
| 3064 | while (val--) { |
| 3065 | if ((RREG32(RADEON_MC_STATUS) & |
| 3066 | RADEON_MC_IDLE)) |
| 3067 | break; |
| 3068 | } |
| 3069 | break; |
| 3070 | default: |
| 3071 | break; |
| 3072 | } |
| 3073 | break; |
| 3074 | default: |
| 3075 | break; |
| 3076 | } |
| 3077 | } |
| 3078 | } |
| 3079 | } |
| 3080 | |
| 3081 | static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) |
| 3082 | { |
| 3083 | struct radeon_device *rdev = dev->dev_private; |
| 3084 | |
| 3085 | if (offset) { |
| 3086 | while (RBIOS8(offset)) { |
| 3087 | uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); |
| 3088 | uint8_t addr = (RBIOS8(offset) & 0x3f); |
| 3089 | uint32_t val, shift, tmp; |
| 3090 | uint32_t and_mask, or_mask; |
| 3091 | |
| 3092 | offset++; |
| 3093 | switch (cmd) { |
| 3094 | case 0: |
| 3095 | val = RBIOS32(offset); |
| 3096 | offset += 4; |
| 3097 | WREG32_PLL(addr, val); |
| 3098 | break; |
| 3099 | case 1: |
| 3100 | shift = RBIOS8(offset) * 8; |
| 3101 | offset++; |
| 3102 | and_mask = RBIOS8(offset) << shift; |
| 3103 | and_mask |= ~(0xff << shift); |
| 3104 | offset++; |
| 3105 | or_mask = RBIOS8(offset) << shift; |
| 3106 | offset++; |
| 3107 | tmp = RREG32_PLL(addr); |
| 3108 | tmp &= and_mask; |
| 3109 | tmp |= or_mask; |
| 3110 | WREG32_PLL(addr, tmp); |
| 3111 | break; |
| 3112 | case 2: |
| 3113 | case 3: |
| 3114 | tmp = 1000; |
| 3115 | switch (addr) { |
| 3116 | case 1: |
| 3117 | udelay(150); |
| 3118 | break; |
| 3119 | case 2: |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 3120 | mdelay(1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3121 | break; |
| 3122 | case 3: |
| 3123 | while (tmp--) { |
| 3124 | if (! |
| 3125 | (RREG32_PLL |
| 3126 | (RADEON_CLK_PWRMGT_CNTL) & |
| 3127 | RADEON_MC_BUSY)) |
| 3128 | break; |
| 3129 | } |
| 3130 | break; |
| 3131 | case 4: |
| 3132 | while (tmp--) { |
| 3133 | if (RREG32_PLL |
| 3134 | (RADEON_CLK_PWRMGT_CNTL) & |
| 3135 | RADEON_DLL_READY) |
| 3136 | break; |
| 3137 | } |
| 3138 | break; |
| 3139 | case 5: |
| 3140 | tmp = |
| 3141 | RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); |
| 3142 | if (tmp & RADEON_CG_NO1_DEBUG_0) { |
| 3143 | #if 0 |
| 3144 | uint32_t mclk_cntl = |
| 3145 | RREG32_PLL |
| 3146 | (RADEON_MCLK_CNTL); |
| 3147 | mclk_cntl &= 0xffff0000; |
| 3148 | /*mclk_cntl |= 0x00001111;*//* ??? */ |
| 3149 | WREG32_PLL(RADEON_MCLK_CNTL, |
| 3150 | mclk_cntl); |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 3151 | mdelay(10); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3152 | #endif |
| 3153 | WREG32_PLL |
| 3154 | (RADEON_CLK_PWRMGT_CNTL, |
| 3155 | tmp & |
| 3156 | ~RADEON_CG_NO1_DEBUG_0); |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 3157 | mdelay(10); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3158 | } |
| 3159 | break; |
| 3160 | default: |
| 3161 | break; |
| 3162 | } |
| 3163 | break; |
| 3164 | default: |
| 3165 | break; |
| 3166 | } |
| 3167 | } |
| 3168 | } |
| 3169 | } |
| 3170 | |
| 3171 | static void combios_parse_ram_reset_table(struct drm_device *dev, |
| 3172 | uint16_t offset) |
| 3173 | { |
| 3174 | struct radeon_device *rdev = dev->dev_private; |
| 3175 | uint32_t tmp; |
| 3176 | |
| 3177 | if (offset) { |
| 3178 | uint8_t val = RBIOS8(offset); |
| 3179 | while (val != 0xff) { |
| 3180 | offset++; |
| 3181 | |
| 3182 | if (val == 0x0f) { |
| 3183 | uint32_t channel_complete_mask; |
| 3184 | |
| 3185 | if (ASIC_IS_R300(rdev)) |
| 3186 | channel_complete_mask = |
| 3187 | R300_MEM_PWRUP_COMPLETE; |
| 3188 | else |
| 3189 | channel_complete_mask = |
| 3190 | RADEON_MEM_PWRUP_COMPLETE; |
| 3191 | tmp = 20000; |
| 3192 | while (tmp--) { |
| 3193 | if ((RREG32(RADEON_MEM_STR_CNTL) & |
| 3194 | channel_complete_mask) == |
| 3195 | channel_complete_mask) |
| 3196 | break; |
| 3197 | } |
| 3198 | } else { |
| 3199 | uint32_t or_mask = RBIOS16(offset); |
| 3200 | offset += 2; |
| 3201 | |
| 3202 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
| 3203 | tmp &= RADEON_SDRAM_MODE_MASK; |
| 3204 | tmp |= or_mask; |
| 3205 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); |
| 3206 | |
| 3207 | or_mask = val << 24; |
| 3208 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
| 3209 | tmp &= RADEON_B3MEM_RESET_MASK; |
| 3210 | tmp |= or_mask; |
| 3211 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); |
| 3212 | } |
| 3213 | val = RBIOS8(offset); |
| 3214 | } |
| 3215 | } |
| 3216 | } |
| 3217 | |
| 3218 | static uint32_t combios_detect_ram(struct drm_device *dev, int ram, |
| 3219 | int mem_addr_mapping) |
| 3220 | { |
| 3221 | struct radeon_device *rdev = dev->dev_private; |
| 3222 | uint32_t mem_cntl; |
| 3223 | uint32_t mem_size; |
| 3224 | uint32_t addr = 0; |
| 3225 | |
| 3226 | mem_cntl = RREG32(RADEON_MEM_CNTL); |
| 3227 | if (mem_cntl & RV100_HALF_MODE) |
| 3228 | ram /= 2; |
| 3229 | mem_size = ram; |
| 3230 | mem_cntl &= ~(0xff << 8); |
| 3231 | mem_cntl |= (mem_addr_mapping & 0xff) << 8; |
| 3232 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
| 3233 | RREG32(RADEON_MEM_CNTL); |
| 3234 | |
| 3235 | /* sdram reset ? */ |
| 3236 | |
| 3237 | /* something like this???? */ |
| 3238 | while (ram--) { |
| 3239 | addr = ram * 1024 * 1024; |
| 3240 | /* write to each page */ |
| 3241 | WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); |
| 3242 | WREG32(RADEON_MM_DATA, 0xdeadbeef); |
| 3243 | /* read back and verify */ |
| 3244 | WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); |
| 3245 | if (RREG32(RADEON_MM_DATA) != 0xdeadbeef) |
| 3246 | return 0; |
| 3247 | } |
| 3248 | |
| 3249 | return mem_size; |
| 3250 | } |
| 3251 | |
| 3252 | static void combios_write_ram_size(struct drm_device *dev) |
| 3253 | { |
| 3254 | struct radeon_device *rdev = dev->dev_private; |
| 3255 | uint8_t rev; |
| 3256 | uint16_t offset; |
| 3257 | uint32_t mem_size = 0; |
| 3258 | uint32_t mem_cntl = 0; |
| 3259 | |
| 3260 | /* should do something smarter here I guess... */ |
| 3261 | if (rdev->flags & RADEON_IS_IGP) |
| 3262 | return; |
| 3263 | |
| 3264 | /* first check detected mem table */ |
| 3265 | offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); |
| 3266 | if (offset) { |
| 3267 | rev = RBIOS8(offset); |
| 3268 | if (rev < 3) { |
| 3269 | mem_cntl = RBIOS32(offset + 1); |
| 3270 | mem_size = RBIOS16(offset + 5); |
Alex Deucher | 4ce9198 | 2010-06-30 12:13:55 -0400 | [diff] [blame] | 3271 | if ((rdev->family < CHIP_R200) && |
| 3272 | !ASIC_IS_RN50(rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3273 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
| 3274 | } |
| 3275 | } |
| 3276 | |
| 3277 | if (!mem_size) { |
| 3278 | offset = |
| 3279 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
| 3280 | if (offset) { |
| 3281 | rev = RBIOS8(offset - 1); |
| 3282 | if (rev < 1) { |
Alex Deucher | 4ce9198 | 2010-06-30 12:13:55 -0400 | [diff] [blame] | 3283 | if ((rdev->family < CHIP_R200) |
| 3284 | && !ASIC_IS_RN50(rdev)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3285 | int ram = 0; |
| 3286 | int mem_addr_mapping = 0; |
| 3287 | |
| 3288 | while (RBIOS8(offset)) { |
| 3289 | ram = RBIOS8(offset); |
| 3290 | mem_addr_mapping = |
| 3291 | RBIOS8(offset + 1); |
| 3292 | if (mem_addr_mapping != 0x25) |
| 3293 | ram *= 2; |
| 3294 | mem_size = |
| 3295 | combios_detect_ram(dev, ram, |
| 3296 | mem_addr_mapping); |
| 3297 | if (mem_size) |
| 3298 | break; |
| 3299 | offset += 2; |
| 3300 | } |
| 3301 | } else |
| 3302 | mem_size = RBIOS8(offset); |
| 3303 | } else { |
| 3304 | mem_size = RBIOS8(offset); |
| 3305 | mem_size *= 2; /* convert to MB */ |
| 3306 | } |
| 3307 | } |
| 3308 | } |
| 3309 | |
| 3310 | mem_size *= (1024 * 1024); /* convert to bytes */ |
| 3311 | WREG32(RADEON_CONFIG_MEMSIZE, mem_size); |
| 3312 | } |
| 3313 | |
| 3314 | void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable) |
| 3315 | { |
| 3316 | uint16_t dyn_clk_info = |
| 3317 | combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); |
| 3318 | |
| 3319 | if (dyn_clk_info) |
| 3320 | combios_parse_pll_table(dev, dyn_clk_info); |
| 3321 | } |
| 3322 | |
| 3323 | void radeon_combios_asic_init(struct drm_device *dev) |
| 3324 | { |
| 3325 | struct radeon_device *rdev = dev->dev_private; |
| 3326 | uint16_t table; |
| 3327 | |
| 3328 | /* port hardcoded mac stuff from radeonfb */ |
| 3329 | if (rdev->bios == NULL) |
| 3330 | return; |
| 3331 | |
| 3332 | /* ASIC INIT 1 */ |
| 3333 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); |
| 3334 | if (table) |
| 3335 | combios_parse_mmio_table(dev, table); |
| 3336 | |
| 3337 | /* PLL INIT */ |
| 3338 | table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); |
| 3339 | if (table) |
| 3340 | combios_parse_pll_table(dev, table); |
| 3341 | |
| 3342 | /* ASIC INIT 2 */ |
| 3343 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); |
| 3344 | if (table) |
| 3345 | combios_parse_mmio_table(dev, table); |
| 3346 | |
| 3347 | if (!(rdev->flags & RADEON_IS_IGP)) { |
| 3348 | /* ASIC INIT 4 */ |
| 3349 | table = |
| 3350 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); |
| 3351 | if (table) |
| 3352 | combios_parse_mmio_table(dev, table); |
| 3353 | |
| 3354 | /* RAM RESET */ |
| 3355 | table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); |
| 3356 | if (table) |
| 3357 | combios_parse_ram_reset_table(dev, table); |
| 3358 | |
| 3359 | /* ASIC INIT 3 */ |
| 3360 | table = |
| 3361 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); |
| 3362 | if (table) |
| 3363 | combios_parse_mmio_table(dev, table); |
| 3364 | |
| 3365 | /* write CONFIG_MEMSIZE */ |
| 3366 | combios_write_ram_size(dev); |
| 3367 | } |
| 3368 | |
Dave Airlie | 580b4ff | 2010-06-30 13:26:11 +1000 | [diff] [blame] | 3369 | /* quirk for rs4xx HP nx6125 laptop to make it resume |
| 3370 | * - it hangs on resume inside the dynclk 1 table. |
| 3371 | */ |
| 3372 | if (rdev->family == CHIP_RS480 && |
| 3373 | rdev->pdev->subsystem_vendor == 0x103c && |
| 3374 | rdev->pdev->subsystem_device == 0x308b) |
| 3375 | return; |
| 3376 | |
Alex Deucher | 52fa2bb | 2010-07-21 23:54:35 -0400 | [diff] [blame] | 3377 | /* quirk for rs4xx HP dv5000 laptop to make it resume |
| 3378 | * - it hangs on resume inside the dynclk 1 table. |
| 3379 | */ |
| 3380 | if (rdev->family == CHIP_RS480 && |
| 3381 | rdev->pdev->subsystem_vendor == 0x103c && |
| 3382 | rdev->pdev->subsystem_device == 0x30a4) |
| 3383 | return; |
| 3384 | |
Alex Deucher | 302a8e8 | 2011-08-29 14:55:25 +0000 | [diff] [blame] | 3385 | /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume |
| 3386 | * - it hangs on resume inside the dynclk 1 table. |
| 3387 | */ |
| 3388 | if (rdev->family == CHIP_RS480 && |
| 3389 | rdev->pdev->subsystem_vendor == 0x103c && |
| 3390 | rdev->pdev->subsystem_device == 0x30ae) |
| 3391 | return; |
| 3392 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3393 | /* DYN CLK 1 */ |
| 3394 | table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); |
| 3395 | if (table) |
| 3396 | combios_parse_pll_table(dev, table); |
| 3397 | |
| 3398 | } |
| 3399 | |
| 3400 | void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) |
| 3401 | { |
| 3402 | struct radeon_device *rdev = dev->dev_private; |
| 3403 | uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; |
| 3404 | |
| 3405 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
| 3406 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 3407 | bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); |
| 3408 | |
| 3409 | /* let the bios control the backlight */ |
| 3410 | bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; |
| 3411 | |
| 3412 | /* tell the bios not to handle mode switching */ |
| 3413 | bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | |
| 3414 | RADEON_ACC_MODE_CHANGE); |
| 3415 | |
| 3416 | /* tell the bios a driver is loaded */ |
| 3417 | bios_7_scratch |= RADEON_DRV_LOADED; |
| 3418 | |
| 3419 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); |
| 3420 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 3421 | WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); |
| 3422 | } |
| 3423 | |
| 3424 | void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) |
| 3425 | { |
| 3426 | struct drm_device *dev = encoder->dev; |
| 3427 | struct radeon_device *rdev = dev->dev_private; |
| 3428 | uint32_t bios_6_scratch; |
| 3429 | |
| 3430 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 3431 | |
| 3432 | if (lock) |
| 3433 | bios_6_scratch |= RADEON_DRIVER_CRITICAL; |
| 3434 | else |
| 3435 | bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; |
| 3436 | |
| 3437 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 3438 | } |
| 3439 | |
| 3440 | void |
| 3441 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
| 3442 | struct drm_encoder *encoder, |
| 3443 | bool connected) |
| 3444 | { |
| 3445 | struct drm_device *dev = connector->dev; |
| 3446 | struct radeon_device *rdev = dev->dev_private; |
| 3447 | struct radeon_connector *radeon_connector = |
| 3448 | to_radeon_connector(connector); |
| 3449 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 3450 | uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); |
| 3451 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); |
| 3452 | |
| 3453 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
| 3454 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
| 3455 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3456 | DRM_DEBUG_KMS("TV1 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3457 | /* fix me */ |
| 3458 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; |
| 3459 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ |
| 3460 | bios_5_scratch |= RADEON_TV1_ON; |
| 3461 | bios_5_scratch |= RADEON_ACC_REQ_TV1; |
| 3462 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3463 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3464 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; |
| 3465 | bios_5_scratch &= ~RADEON_TV1_ON; |
| 3466 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1; |
| 3467 | } |
| 3468 | } |
| 3469 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
| 3470 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
| 3471 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3472 | DRM_DEBUG_KMS("LCD1 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3473 | bios_4_scratch |= RADEON_LCD1_ATTACHED; |
| 3474 | bios_5_scratch |= RADEON_LCD1_ON; |
| 3475 | bios_5_scratch |= RADEON_ACC_REQ_LCD1; |
| 3476 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3477 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3478 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED; |
| 3479 | bios_5_scratch &= ~RADEON_LCD1_ON; |
| 3480 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; |
| 3481 | } |
| 3482 | } |
| 3483 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
| 3484 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
| 3485 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3486 | DRM_DEBUG_KMS("CRT1 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3487 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; |
| 3488 | bios_5_scratch |= RADEON_CRT1_ON; |
| 3489 | bios_5_scratch |= RADEON_ACC_REQ_CRT1; |
| 3490 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3491 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3492 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; |
| 3493 | bios_5_scratch &= ~RADEON_CRT1_ON; |
| 3494 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; |
| 3495 | } |
| 3496 | } |
| 3497 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
| 3498 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
| 3499 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3500 | DRM_DEBUG_KMS("CRT2 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3501 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; |
| 3502 | bios_5_scratch |= RADEON_CRT2_ON; |
| 3503 | bios_5_scratch |= RADEON_ACC_REQ_CRT2; |
| 3504 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3505 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3506 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; |
| 3507 | bios_5_scratch &= ~RADEON_CRT2_ON; |
| 3508 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; |
| 3509 | } |
| 3510 | } |
| 3511 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
| 3512 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
| 3513 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3514 | DRM_DEBUG_KMS("DFP1 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3515 | bios_4_scratch |= RADEON_DFP1_ATTACHED; |
| 3516 | bios_5_scratch |= RADEON_DFP1_ON; |
| 3517 | bios_5_scratch |= RADEON_ACC_REQ_DFP1; |
| 3518 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3519 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3520 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED; |
| 3521 | bios_5_scratch &= ~RADEON_DFP1_ON; |
| 3522 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; |
| 3523 | } |
| 3524 | } |
| 3525 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
| 3526 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
| 3527 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3528 | DRM_DEBUG_KMS("DFP2 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3529 | bios_4_scratch |= RADEON_DFP2_ATTACHED; |
| 3530 | bios_5_scratch |= RADEON_DFP2_ON; |
| 3531 | bios_5_scratch |= RADEON_ACC_REQ_DFP2; |
| 3532 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 3533 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3534 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED; |
| 3535 | bios_5_scratch &= ~RADEON_DFP2_ON; |
| 3536 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; |
| 3537 | } |
| 3538 | } |
| 3539 | WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); |
| 3540 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); |
| 3541 | } |
| 3542 | |
| 3543 | void |
| 3544 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
| 3545 | { |
| 3546 | struct drm_device *dev = encoder->dev; |
| 3547 | struct radeon_device *rdev = dev->dev_private; |
| 3548 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 3549 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); |
| 3550 | |
| 3551 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 3552 | bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; |
| 3553 | bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); |
| 3554 | } |
| 3555 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| 3556 | bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; |
| 3557 | bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); |
| 3558 | } |
| 3559 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| 3560 | bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; |
| 3561 | bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); |
| 3562 | } |
| 3563 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| 3564 | bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; |
| 3565 | bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); |
| 3566 | } |
| 3567 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
| 3568 | bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; |
| 3569 | bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); |
| 3570 | } |
| 3571 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
| 3572 | bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; |
| 3573 | bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); |
| 3574 | } |
| 3575 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); |
| 3576 | } |
| 3577 | |
| 3578 | void |
| 3579 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) |
| 3580 | { |
| 3581 | struct drm_device *dev = encoder->dev; |
| 3582 | struct radeon_device *rdev = dev->dev_private; |
| 3583 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 3584 | uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 3585 | |
| 3586 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { |
| 3587 | if (on) |
| 3588 | bios_6_scratch |= RADEON_TV_DPMS_ON; |
| 3589 | else |
| 3590 | bios_6_scratch &= ~RADEON_TV_DPMS_ON; |
| 3591 | } |
| 3592 | if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
| 3593 | if (on) |
| 3594 | bios_6_scratch |= RADEON_CRT_DPMS_ON; |
| 3595 | else |
| 3596 | bios_6_scratch &= ~RADEON_CRT_DPMS_ON; |
| 3597 | } |
| 3598 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 3599 | if (on) |
| 3600 | bios_6_scratch |= RADEON_LCD_DPMS_ON; |
| 3601 | else |
| 3602 | bios_6_scratch &= ~RADEON_LCD_DPMS_ON; |
| 3603 | } |
| 3604 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 3605 | if (on) |
| 3606 | bios_6_scratch |= RADEON_DFP_DPMS_ON; |
| 3607 | else |
| 3608 | bios_6_scratch &= ~RADEON_DFP_DPMS_ON; |
| 3609 | } |
| 3610 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 3611 | } |