| Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1 | #ifndef __ASM_SPARC_PERF_EVENT_H |
| 2 | #define __ASM_SPARC_PERF_EVENT_H |
| 3 | |
| 4 | extern void set_perf_event_pending(void); |
| 5 | |
| 6 | #define PERF_EVENT_INDEX_OFFSET 0 |
| 7 | |
| 8 | #ifdef CONFIG_PERF_EVENTS |
| Frederic Weisbecker | b0f82b8 | 2010-05-20 07:47:21 +0200 | [diff] [blame] | 9 | #include <asm/ptrace.h> |
| 10 | |
| Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 11 | extern void init_hw_perf_events(void); |
| Frederic Weisbecker | b0f82b8 | 2010-05-20 07:47:21 +0200 | [diff] [blame] | 12 | |
| David S. Miller | b11287e | 2010-08-08 22:03:59 -0700 | [diff] [blame^] | 13 | #define perf_arch_fetch_caller_regs(regs, ip) \ |
| 14 | do { \ |
| 15 | unsigned long _pstate, _asi, _pil, _i7, _fp; \ |
| 16 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" \ |
| 17 | "rd %%asi, %1\n\t" \ |
| 18 | "rdpr %%pil, %2\n\t" \ |
| 19 | "mov %%i7, %3\n\t" \ |
| 20 | "mov %%i6, %4\n\t" \ |
| 21 | : "=r" (_pstate), \ |
| 22 | "=r" (_asi), \ |
| 23 | "=r" (_pil), \ |
| 24 | "=r" (_i7), \ |
| 25 | "=r" (_fp)); \ |
| 26 | (regs)->tstate = (_pstate << 8) | \ |
| 27 | (_asi << 24) | (_pil << 20); \ |
| 28 | (regs)->tpc = (ip); \ |
| 29 | (regs)->tnpc = (regs)->tpc + 4; \ |
| 30 | (regs)->u_regs[UREG_I6] = _fp; \ |
| 31 | (regs)->u_regs[UREG_I7] = _i7; \ |
| 32 | } while (0) |
| Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 33 | #else |
| 34 | static inline void init_hw_perf_events(void) { } |
| 35 | #endif |
| 36 | |
| 37 | #endif |