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gerrit-public.fairphone.software / kernel / msm / b3950e6a52b1d0279787ef44ba1efac2f3414260 / . / drivers / net / wireless / ath / ath9k / ar9003_hw.c
blob: 6111bdb7779bb230d23bdc5564703973315eb942 [file] [log] [blame]
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400[diff] [blame^]1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_initvals.h"
19
20/* General hardware code for the AR9003 hadware family */
21
22static bool ar9003_hw_macversion_supported(u32 macversion)
23{
24 switch (macversion) {
25 case AR_SREV_VERSION_9300:
26 return true;
27 default:
28 break;
29 }
30 return false;
31}
32
33/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
34static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
35{
36 /* mac */
37 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
38 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
39 ar9300_2p0_mac_core,
40 ARRAY_SIZE(ar9300_2p0_mac_core), 2);
41 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
42 ar9300_2p0_mac_postamble,
43 ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
44
45 /* bb */
46 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
47 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
48 ar9300_2p0_baseband_core,
49 ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
50 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
51 ar9300_2p0_baseband_postamble,
52 ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
53
54 /* radio */
55 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
56 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
57 ar9300_2p0_radio_core,
58 ARRAY_SIZE(ar9300_2p0_radio_core), 2);
59 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
60 ar9300_2p0_radio_postamble,
61 ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
62
63 /* soc */
64 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
65 ar9300_2p0_soc_preamble,
66 ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
67 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
68 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
69 ar9300_2p0_soc_postamble,
70 ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
71
72 /* rx/tx gain */
73 INIT_INI_ARRAY(&ah->iniModesRxGain,
74 ar9300Common_rx_gain_table_2p0,
75 ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
76 INIT_INI_ARRAY(&ah->iniModesTxGain,
77 ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
78 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
79 5);
80
81 /* Load PCIE SERDES settings from INI */
82
83 /* Awake Setting */
84
85 INIT_INI_ARRAY(&ah->iniPcieSerdes,
86 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
87 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
88 2);
89
90 /* Sleep Setting */
91
92 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
93 ar9300PciePhy_clkreq_enable_L1_2p0,
94 ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
95 2);
96
97 /* Fast clock modal settings */
98 INIT_INI_ARRAY(&ah->iniModesAdditional,
99 ar9300Modes_fast_clock_2p0,
100 ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
101 3);
102}
103
104/*
105 * Helper for ASPM support.
106 *
107 * Disable PLL when in L0s as well as receiver clock when in L1.
108 * This power saving option must be enabled through the SerDes.
109 *
110 * Programming the SerDes must go through the same 288 bit serial shift
111 * register as the other analog registers. Hence the 9 writes.
112 */
113static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
114 int restore,
115 int power_off)
116{
117 if (ah->is_pciexpress != true)
118 return;
119
120 /* Do not touch SerDes registers */
121 if (ah->config.pcie_powersave_enable == 2)
122 return;
123
124 /* Nothing to do on restore for 11N */
125 if (!restore) {
126 /* set bit 19 to allow forcing of pcie core into L1 state */
127 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
128
129 /* Several PCIe massages to ensure proper behaviour */
130 if (ah->config.pcie_waen)
131 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
132 }
133}
134
135/* Sets up the AR9003 hardware familiy callbacks */
136void ar9003_hw_attach_ops(struct ath_hw *ah)
137{
138 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
139 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
140
141 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
142 priv_ops->macversion_supported = ar9003_hw_macversion_supported;
143
144 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
145
146 ar9003_hw_attach_phy_ops(ah);
147 ar9003_hw_attach_calib_ops(ah);
148 ar9003_hw_attach_mac_ops(ah);
149}