blob: 6f7e3fde9e7cdcbe9fa12c23eb88cad8a3dbee0e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
Ayaz Abdulla87046e52006-12-19 23:33:32 -05006 * and Andrew de Quincey.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
Manfred Spraul18360982005-12-24 14:19:24 +010012 * Copyright (C) 2003,4,5 Manfred Spraul
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
Ayaz Abdullaf648d122008-01-13 16:02:57 -050016 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Changelog:
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41 * irq mask updated
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56 * open.
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60 * the tx length.
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * on close.
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -050082 * capabilities.
Manfred Spraul22c6d142005-04-19 21:17:09 +020083 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
Manfred Spraul8f767fc2005-06-18 16:27:19 +020084 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
Manfred Spraulf49d16e2005-06-26 11:36:52 +020086 * 0.35: 26 Jun 2005: Support for MCP55 added.
Manfred Sprauldc8216c2005-07-31 18:26:05 +020087 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
Manfred Spraulc2dba062005-07-31 18:29:47 +020089 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90 * per-packet flags.
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -050091 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
Manfred Spraulb3df9f82005-07-31 18:38:58 +020094 * of nv_remove
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -050095 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
Manfred Spraul1b1b3c92005-08-06 23:47:55 +020096 * in the second (and later) nv_open call
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -050097 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500100 * 0.46: 20 Oct 2005: Add irq optimization modes.
Ayaz Abdulla7a33e452005-11-11 08:31:11 -0500101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
Manfred Spraul18360982005-12-24 14:19:24 +0100102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
Ayaz Abdullafa454592006-01-05 22:45:45 -0800103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
Ayaz Abdulla84b39322006-05-20 14:59:48 -0700108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
Ayaz Abdullaebe611a2006-06-10 22:48:24 -0400110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500113 * 0.59: 30 Oct 2006: Added support for recoverable error.
Ayaz Abdulla21828162007-01-23 12:27:21 -0500114 * 0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 *
116 * Known bugs:
117 * We suspect that on some hardware no TX done interrupts are generated.
118 * This means recovery from netif_stop_queue only happens if the hw timer
119 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
120 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
121 * If your hardware reliably generates tx done interrupts, then you can remove
122 * DEV_NEED_TIMERIRQ from the driver_data flags.
123 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
124 * superfluous timer interrupts from the nic.
125 */
Stephen Hemmingere27cdba2006-07-31 20:37:19 -0700126#ifdef CONFIG_FORCEDETH_NAPI
127#define DRIVERNAPI "-NAPI"
128#else
129#define DRIVERNAPI
130#endif
Jeff Garzik8148ff42007-10-16 20:56:09 -0400131#define FORCEDETH_VERSION "0.61"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132#define DRV_NAME "forcedeth"
133
134#include <linux/module.h>
135#include <linux/types.h>
136#include <linux/pci.h>
137#include <linux/interrupt.h>
138#include <linux/netdevice.h>
139#include <linux/etherdevice.h>
140#include <linux/delay.h>
141#include <linux/spinlock.h>
142#include <linux/ethtool.h>
143#include <linux/timer.h>
144#include <linux/skbuff.h>
145#include <linux/mii.h>
146#include <linux/random.h>
147#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +0200148#include <linux/if_vlan.h>
Matthias Gehre910638a2006-03-28 01:56:48 -0800149#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150
151#include <asm/irq.h>
152#include <asm/io.h>
153#include <asm/uaccess.h>
154#include <asm/system.h>
155
156#if 0
157#define dprintk printk
158#else
159#define dprintk(x...) do { } while (0)
160#endif
161
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700162#define TX_WORK_PER_LOOP 64
163#define RX_WORK_PER_LOOP 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164
165/*
166 * Hardware access:
167 */
168
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500169#define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */
170#define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */
171#define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */
172#define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */
173#define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */
174#define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */
175#define DEV_HAS_MSI 0x00040 /* device supports MSI */
176#define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */
177#define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */
178#define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */
179#define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */
180#define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */
181#define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */
182#define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */
183#define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */
184#define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
185#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
186#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500187#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188
189enum {
190 NvRegIrqStatus = 0x000,
191#define NVREG_IRQSTAT_MIIEVENT 0x040
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500192#define NVREG_IRQSTAT_MASK 0x81ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 NvRegIrqMask = 0x004,
194#define NVREG_IRQ_RX_ERROR 0x0001
195#define NVREG_IRQ_RX 0x0002
196#define NVREG_IRQ_RX_NOBUF 0x0004
197#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200198#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199#define NVREG_IRQ_TIMER 0x0020
200#define NVREG_IRQ_LINK 0x0040
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500201#define NVREG_IRQ_RX_FORCED 0x0080
202#define NVREG_IRQ_TX_FORCED 0x0100
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500203#define NVREG_IRQ_RECOVER_ERROR 0x8000
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500204#define NVREG_IRQMASK_THROUGHPUT 0x00df
Ayaz Abdulla096a4582007-05-21 20:23:11 -0400205#define NVREG_IRQMASK_CPU 0x0060
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500206#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
207#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500208#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200209
210#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500211 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500212 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213
214 NvRegUnknownSetupReg6 = 0x008,
215#define NVREG_UNKSETUP6_VAL 3
216
217/*
218 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
219 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
220 */
221 NvRegPollingInterval = 0x00c,
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -0500222#define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500223#define NVREG_POLL_DEFAULT_CPU 13
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500224 NvRegMSIMap0 = 0x020,
225 NvRegMSIMap1 = 0x024,
226 NvRegMSIIrqMask = 0x030,
227#define NVREG_MSI_VECTOR_0_ENABLED 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 NvRegMisc1 = 0x080,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400229#define NVREG_MISC1_PAUSE_TX 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230#define NVREG_MISC1_HD 0x02
231#define NVREG_MISC1_FORCE 0x3b0f3c
232
Ayaz Abdulla0a626772008-01-13 16:02:42 -0500233 NvRegMacReset = 0x34,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400234#define NVREG_MAC_RESET_ASSERT 0x0F3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 NvRegTransmitterControl = 0x084,
236#define NVREG_XMITCTL_START 0x01
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500237#define NVREG_XMITCTL_MGMT_ST 0x40000000
238#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
239#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
240#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
241#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
242#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
243#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
244#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
245#define NVREG_XMITCTL_HOST_LOADED 0x00004000
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500246#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 NvRegTransmitterStatus = 0x088,
248#define NVREG_XMITSTAT_BUSY 0x01
249
250 NvRegPacketFilterFlags = 0x8c,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400251#define NVREG_PFF_PAUSE_RX 0x08
252#define NVREG_PFF_ALWAYS 0x7F0000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253#define NVREG_PFF_PROMISC 0x80
254#define NVREG_PFF_MYADDR 0x20
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400255#define NVREG_PFF_LOOPBACK 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256
257 NvRegOffloadConfig = 0x90,
258#define NVREG_OFFLOAD_HOMEPHY 0x601
259#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
260 NvRegReceiverControl = 0x094,
261#define NVREG_RCVCTL_START 0x01
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500262#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263 NvRegReceiverStatus = 0x98,
264#define NVREG_RCVSTAT_BUSY 0x01
265
266 NvRegRandomSeed = 0x9c,
267#define NVREG_RNDSEED_MASK 0x00ff
268#define NVREG_RNDSEED_FORCE 0x7f00
269#define NVREG_RNDSEED_FORCE2 0x2d00
270#define NVREG_RNDSEED_FORCE3 0x7400
271
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400272 NvRegTxDeferral = 0xA0,
Ayaz Abdullafd9b5582008-02-05 12:29:49 -0500273#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
274#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
275#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
276#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
277#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
278#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400279 NvRegRxDeferral = 0xA4,
280#define NVREG_RX_DEFERRAL_DEFAULT 0x16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281 NvRegMacAddrA = 0xA8,
282 NvRegMacAddrB = 0xAC,
283 NvRegMulticastAddrA = 0xB0,
284#define NVREG_MCASTADDRA_FORCE 0x01
285 NvRegMulticastAddrB = 0xB4,
286 NvRegMulticastMaskA = 0xB8,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500287#define NVREG_MCASTMASKA_NONE 0xffffffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 NvRegMulticastMaskB = 0xBC,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500289#define NVREG_MCASTMASKB_NONE 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290
291 NvRegPhyInterface = 0xC0,
292#define PHY_RGMII 0x10000000
293
294 NvRegTxRingPhysAddr = 0x100,
295 NvRegRxRingPhysAddr = 0x104,
296 NvRegRingSizes = 0x108,
297#define NVREG_RINGSZ_TXSHIFT 0
298#define NVREG_RINGSZ_RXSHIFT 16
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400299 NvRegTransmitPoll = 0x10c,
300#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 NvRegLinkSpeed = 0x110,
302#define NVREG_LINKSPEED_FORCE 0x10000
303#define NVREG_LINKSPEED_10 1000
304#define NVREG_LINKSPEED_100 100
305#define NVREG_LINKSPEED_1000 50
306#define NVREG_LINKSPEED_MASK (0xFFF)
307 NvRegUnknownSetupReg5 = 0x130,
308#define NVREG_UNKSETUP5_BIT31 (1<<31)
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400309 NvRegTxWatermark = 0x13c,
310#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
311#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
312#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 NvRegTxRxControl = 0x144,
314#define NVREG_TXRXCTL_KICK 0x0001
315#define NVREG_TXRXCTL_BIT1 0x0002
316#define NVREG_TXRXCTL_BIT2 0x0004
317#define NVREG_TXRXCTL_IDLE 0x0008
318#define NVREG_TXRXCTL_RESET 0x0010
319#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400320#define NVREG_TXRXCTL_DESC_1 0
Ayaz Abdullad2f78412007-01-09 13:30:02 -0500321#define NVREG_TXRXCTL_DESC_2 0x002100
322#define NVREG_TXRXCTL_DESC_3 0xc02200
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500323#define NVREG_TXRXCTL_VLANSTRIP 0x00040
324#define NVREG_TXRXCTL_VLANINS 0x00080
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500325 NvRegTxRingPhysAddrHigh = 0x148,
326 NvRegRxRingPhysAddrHigh = 0x14C,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400327 NvRegTxPauseFrame = 0x170,
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500328#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
329#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
330#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
331#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 NvRegMIIStatus = 0x180,
333#define NVREG_MIISTAT_ERROR 0x0001
334#define NVREG_MIISTAT_LINKCHANGE 0x0008
Ayaz Abdullaeb798422008-02-04 15:14:04 -0500335#define NVREG_MIISTAT_MASK_RW 0x0007
336#define NVREG_MIISTAT_MASK_ALL 0x000f
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500337 NvRegMIIMask = 0x184,
338#define NVREG_MII_LINKCHANGE 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339
340 NvRegAdapterControl = 0x188,
341#define NVREG_ADAPTCTL_START 0x02
342#define NVREG_ADAPTCTL_LINKUP 0x04
343#define NVREG_ADAPTCTL_PHYVALID 0x40000
344#define NVREG_ADAPTCTL_RUNNING 0x100000
345#define NVREG_ADAPTCTL_PHYSHIFT 24
346 NvRegMIISpeed = 0x18c,
347#define NVREG_MIISPEED_BIT8 (1<<8)
348#define NVREG_MIIDELAY 5
349 NvRegMIIControl = 0x190,
350#define NVREG_MIICTL_INUSE 0x08000
351#define NVREG_MIICTL_WRITE 0x00400
352#define NVREG_MIICTL_ADDRSHIFT 5
353 NvRegMIIData = 0x194,
354 NvRegWakeUpFlags = 0x200,
355#define NVREG_WAKEUPFLAGS_VAL 0x7770
356#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
357#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
358#define NVREG_WAKEUPFLAGS_D3SHIFT 12
359#define NVREG_WAKEUPFLAGS_D2SHIFT 8
360#define NVREG_WAKEUPFLAGS_D1SHIFT 4
361#define NVREG_WAKEUPFLAGS_D0SHIFT 0
362#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
363#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
364#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
365#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
366
367 NvRegPatternCRC = 0x204,
368 NvRegPatternMask = 0x208,
369 NvRegPowerCap = 0x268,
370#define NVREG_POWERCAP_D3SUPP (1<<30)
371#define NVREG_POWERCAP_D2SUPP (1<<26)
372#define NVREG_POWERCAP_D1SUPP (1<<25)
373 NvRegPowerState = 0x26c,
374#define NVREG_POWERSTATE_POWEREDUP 0x8000
375#define NVREG_POWERSTATE_VALID 0x0100
376#define NVREG_POWERSTATE_MASK 0x0003
377#define NVREG_POWERSTATE_D0 0x0000
378#define NVREG_POWERSTATE_D1 0x0001
379#define NVREG_POWERSTATE_D2 0x0002
380#define NVREG_POWERSTATE_D3 0x0003
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400381 NvRegTxCnt = 0x280,
382 NvRegTxZeroReXmt = 0x284,
383 NvRegTxOneReXmt = 0x288,
384 NvRegTxManyReXmt = 0x28c,
385 NvRegTxLateCol = 0x290,
386 NvRegTxUnderflow = 0x294,
387 NvRegTxLossCarrier = 0x298,
388 NvRegTxExcessDef = 0x29c,
389 NvRegTxRetryErr = 0x2a0,
390 NvRegRxFrameErr = 0x2a4,
391 NvRegRxExtraByte = 0x2a8,
392 NvRegRxLateCol = 0x2ac,
393 NvRegRxRunt = 0x2b0,
394 NvRegRxFrameTooLong = 0x2b4,
395 NvRegRxOverflow = 0x2b8,
396 NvRegRxFCSErr = 0x2bc,
397 NvRegRxFrameAlignErr = 0x2c0,
398 NvRegRxLenErr = 0x2c4,
399 NvRegRxUnicast = 0x2c8,
400 NvRegRxMulticast = 0x2cc,
401 NvRegRxBroadcast = 0x2d0,
402 NvRegTxDef = 0x2d4,
403 NvRegTxFrame = 0x2d8,
404 NvRegRxCnt = 0x2dc,
405 NvRegTxPause = 0x2e0,
406 NvRegRxPause = 0x2e4,
407 NvRegRxDropFrame = 0x2e8,
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500408 NvRegVlanControl = 0x300,
409#define NVREG_VLANCONTROL_ENABLE 0x2000
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500410 NvRegMSIXMap0 = 0x3e0,
411 NvRegMSIXMap1 = 0x3e4,
412 NvRegMSIXIrqStatus = 0x3f0,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400413
414 NvRegPowerState2 = 0x600,
415#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
416#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417};
418
419/* Big endian: should work, but is untested */
420struct ring_desc {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700421 __le32 buf;
422 __le32 flaglen;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423};
424
Manfred Spraulee733622005-07-31 18:32:26 +0200425struct ring_desc_ex {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700426 __le32 bufhigh;
427 __le32 buflow;
428 __le32 txvlan;
429 __le32 flaglen;
Manfred Spraulee733622005-07-31 18:32:26 +0200430};
431
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700432union ring_type {
Manfred Spraulee733622005-07-31 18:32:26 +0200433 struct ring_desc* orig;
434 struct ring_desc_ex* ex;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700435};
Manfred Spraulee733622005-07-31 18:32:26 +0200436
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437#define FLAG_MASK_V1 0xffff0000
438#define FLAG_MASK_V2 0xffffc000
439#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
440#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
441
442#define NV_TX_LASTPACKET (1<<16)
443#define NV_TX_RETRYERROR (1<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200444#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445#define NV_TX_DEFERRED (1<<26)
446#define NV_TX_CARRIERLOST (1<<27)
447#define NV_TX_LATECOLLISION (1<<28)
448#define NV_TX_UNDERFLOW (1<<29)
449#define NV_TX_ERROR (1<<30)
450#define NV_TX_VALID (1<<31)
451
452#define NV_TX2_LASTPACKET (1<<29)
453#define NV_TX2_RETRYERROR (1<<18)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200454#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455#define NV_TX2_DEFERRED (1<<25)
456#define NV_TX2_CARRIERLOST (1<<26)
457#define NV_TX2_LATECOLLISION (1<<27)
458#define NV_TX2_UNDERFLOW (1<<28)
459/* error and valid are the same for both */
460#define NV_TX2_ERROR (1<<30)
461#define NV_TX2_VALID (1<<31)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400462#define NV_TX2_TSO (1<<28)
463#define NV_TX2_TSO_SHIFT 14
Ayaz Abdullafa454592006-01-05 22:45:45 -0800464#define NV_TX2_TSO_MAX_SHIFT 14
465#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400466#define NV_TX2_CHECKSUM_L3 (1<<27)
467#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500469#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
470
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471#define NV_RX_DESCRIPTORVALID (1<<16)
472#define NV_RX_MISSEDFRAME (1<<17)
473#define NV_RX_SUBSTRACT1 (1<<18)
474#define NV_RX_ERROR1 (1<<23)
475#define NV_RX_ERROR2 (1<<24)
476#define NV_RX_ERROR3 (1<<25)
477#define NV_RX_ERROR4 (1<<26)
478#define NV_RX_CRCERR (1<<27)
479#define NV_RX_OVERFLOW (1<<28)
480#define NV_RX_FRAMINGERR (1<<29)
481#define NV_RX_ERROR (1<<30)
482#define NV_RX_AVAIL (1<<31)
483
484#define NV_RX2_CHECKSUMMASK (0x1C000000)
Ayaz Abdullabfaffe82008-01-13 16:02:55 -0500485#define NV_RX2_CHECKSUM_IP (0x10000000)
486#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
487#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488#define NV_RX2_DESCRIPTORVALID (1<<29)
489#define NV_RX2_SUBSTRACT1 (1<<25)
490#define NV_RX2_ERROR1 (1<<18)
491#define NV_RX2_ERROR2 (1<<19)
492#define NV_RX2_ERROR3 (1<<20)
493#define NV_RX2_ERROR4 (1<<21)
494#define NV_RX2_CRCERR (1<<22)
495#define NV_RX2_OVERFLOW (1<<23)
496#define NV_RX2_FRAMINGERR (1<<24)
497/* error and avail are the same for both */
498#define NV_RX2_ERROR (1<<30)
499#define NV_RX2_AVAIL (1<<31)
500
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500501#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
502#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
503
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504/* Miscelaneous hardware related defines: */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400505#define NV_PCI_REGSZ_VER1 0x270
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500506#define NV_PCI_REGSZ_VER2 0x2d4
507#define NV_PCI_REGSZ_VER3 0x604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508
509/* various timeout delays: all in usec */
510#define NV_TXRX_RESET_DELAY 4
511#define NV_TXSTOP_DELAY1 10
512#define NV_TXSTOP_DELAY1MAX 500000
513#define NV_TXSTOP_DELAY2 100
514#define NV_RXSTOP_DELAY1 10
515#define NV_RXSTOP_DELAY1MAX 500000
516#define NV_RXSTOP_DELAY2 100
517#define NV_SETUP5_DELAY 5
518#define NV_SETUP5_DELAYMAX 50000
519#define NV_POWERUP_DELAY 5
520#define NV_POWERUP_DELAYMAX 5000
521#define NV_MIIBUSY_DELAY 50
522#define NV_MIIPHY_DELAY 10
523#define NV_MIIPHY_DELAYMAX 10000
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400524#define NV_MAC_RESET_DELAY 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525
526#define NV_WAKEUPPATTERNS 5
527#define NV_WAKEUPMASKENTRIES 4
528
529/* General driver defaults */
530#define NV_WATCHDOG_TIMEO (5*HZ)
531
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400532#define RX_RING_DEFAULT 128
533#define TX_RING_DEFAULT 256
534#define RX_RING_MIN 128
535#define TX_RING_MIN 64
536#define RING_MAX_DESC_VER_1 1024
537#define RING_MAX_DESC_VER_2_3 16384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
539/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200540#define NV_RX_HEADERS (64)
541/* even more slack. */
542#define NV_RX_ALLOC_PAD (64)
543
544/* maximum mtu size */
545#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
546#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547
548#define OOM_REFILL (1+HZ/20)
549#define POLL_WAIT (1+HZ/100)
550#define LINK_TIMEOUT (3*HZ)
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400551#define STATS_INTERVAL (10*HZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400553/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400555 * The nic supports three different descriptor types:
556 * - DESC_VER_1: Original
557 * - DESC_VER_2: support for jumbo frames.
558 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400560#define DESC_VER_1 1
561#define DESC_VER_2 2
562#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563
564/* PHY defines */
565#define PHY_OUI_MARVELL 0x5043
566#define PHY_OUI_CICADA 0x03f1
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400567#define PHY_OUI_VITESSE 0x01c1
Willy Tarreauba685fb2007-08-23 21:35:41 +0200568#define PHY_OUI_REALTEK 0x0732
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569#define PHYID1_OUI_MASK 0x03ff
570#define PHYID1_OUI_SHFT 6
571#define PHYID2_OUI_MASK 0xfc00
572#define PHYID2_OUI_SHFT 10
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400573#define PHYID2_MODEL_MASK 0x03f0
574#define PHY_MODEL_MARVELL_E3016 0x220
575#define PHY_MARVELL_E3016_INITMASK 0x0300
Ayaz Abdulla14a67f32007-07-15 06:50:28 -0400576#define PHY_CICADA_INIT1 0x0f000
577#define PHY_CICADA_INIT2 0x0e00
578#define PHY_CICADA_INIT3 0x01000
579#define PHY_CICADA_INIT4 0x0200
580#define PHY_CICADA_INIT5 0x0004
581#define PHY_CICADA_INIT6 0x02000
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400582#define PHY_VITESSE_INIT_REG1 0x1f
583#define PHY_VITESSE_INIT_REG2 0x10
584#define PHY_VITESSE_INIT_REG3 0x11
585#define PHY_VITESSE_INIT_REG4 0x12
586#define PHY_VITESSE_INIT_MSK1 0xc
587#define PHY_VITESSE_INIT_MSK2 0x0180
588#define PHY_VITESSE_INIT1 0x52b5
589#define PHY_VITESSE_INIT2 0xaf8a
590#define PHY_VITESSE_INIT3 0x8
591#define PHY_VITESSE_INIT4 0x8f8a
592#define PHY_VITESSE_INIT5 0xaf86
593#define PHY_VITESSE_INIT6 0x8f86
594#define PHY_VITESSE_INIT7 0xaf82
595#define PHY_VITESSE_INIT8 0x0100
596#define PHY_VITESSE_INIT9 0x8f82
597#define PHY_VITESSE_INIT10 0x0
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400598#define PHY_REALTEK_INIT_REG1 0x1f
599#define PHY_REALTEK_INIT_REG2 0x19
600#define PHY_REALTEK_INIT_REG3 0x13
601#define PHY_REALTEK_INIT1 0x0000
602#define PHY_REALTEK_INIT2 0x8e00
603#define PHY_REALTEK_INIT3 0x0001
604#define PHY_REALTEK_INIT4 0xad17
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400605
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606#define PHY_GIGABIT 0x0100
607
608#define PHY_TIMEOUT 0x1
609#define PHY_ERROR 0x2
610
611#define PHY_100 0x1
612#define PHY_1000 0x2
613#define PHY_HALF 0x100
614
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400615#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
616#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
617#define NV_PAUSEFRAME_RX_ENABLE 0x0004
618#define NV_PAUSEFRAME_TX_ENABLE 0x0008
Ayaz Abdullab6d07732006-06-10 22:47:42 -0400619#define NV_PAUSEFRAME_RX_REQ 0x0010
620#define NV_PAUSEFRAME_TX_REQ 0x0020
621#define NV_PAUSEFRAME_AUTONEG 0x0040
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500623/* MSI/MSI-X defines */
624#define NV_MSI_X_MAX_VECTORS 8
625#define NV_MSI_X_VECTORS_MASK 0x000f
626#define NV_MSI_CAPABLE 0x0010
627#define NV_MSI_X_CAPABLE 0x0020
628#define NV_MSI_ENABLED 0x0040
629#define NV_MSI_X_ENABLED 0x0080
630
631#define NV_MSI_X_VECTOR_ALL 0x0
632#define NV_MSI_X_VECTOR_RX 0x0
633#define NV_MSI_X_VECTOR_TX 0x1
634#define NV_MSI_X_VECTOR_OTHER 0x2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635
Ayaz Abdullab2976d22008-02-04 15:13:59 -0500636#define NV_RESTART_TX 0x1
637#define NV_RESTART_RX 0x2
638
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500639#define NV_TX_LIMIT_COUNT 16
640
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400641/* statistics */
642struct nv_ethtool_str {
643 char name[ETH_GSTRING_LEN];
644};
645
646static const struct nv_ethtool_str nv_estats_str[] = {
647 { "tx_bytes" },
648 { "tx_zero_rexmt" },
649 { "tx_one_rexmt" },
650 { "tx_many_rexmt" },
651 { "tx_late_collision" },
652 { "tx_fifo_errors" },
653 { "tx_carrier_errors" },
654 { "tx_excess_deferral" },
655 { "tx_retry_error" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400656 { "rx_frame_error" },
657 { "rx_extra_byte" },
658 { "rx_late_collision" },
659 { "rx_runt" },
660 { "rx_frame_too_long" },
661 { "rx_over_errors" },
662 { "rx_crc_errors" },
663 { "rx_frame_align_error" },
664 { "rx_length_error" },
665 { "rx_unicast" },
666 { "rx_multicast" },
667 { "rx_broadcast" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400668 { "rx_packets" },
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500669 { "rx_errors_total" },
670 { "tx_errors_total" },
671
672 /* version 2 stats */
673 { "tx_deferral" },
674 { "tx_packets" },
675 { "rx_bytes" },
676 { "tx_pause" },
677 { "rx_pause" },
678 { "rx_drop_frame" }
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400679};
680
681struct nv_ethtool_stats {
682 u64 tx_bytes;
683 u64 tx_zero_rexmt;
684 u64 tx_one_rexmt;
685 u64 tx_many_rexmt;
686 u64 tx_late_collision;
687 u64 tx_fifo_errors;
688 u64 tx_carrier_errors;
689 u64 tx_excess_deferral;
690 u64 tx_retry_error;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400691 u64 rx_frame_error;
692 u64 rx_extra_byte;
693 u64 rx_late_collision;
694 u64 rx_runt;
695 u64 rx_frame_too_long;
696 u64 rx_over_errors;
697 u64 rx_crc_errors;
698 u64 rx_frame_align_error;
699 u64 rx_length_error;
700 u64 rx_unicast;
701 u64 rx_multicast;
702 u64 rx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400703 u64 rx_packets;
704 u64 rx_errors_total;
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500705 u64 tx_errors_total;
706
707 /* version 2 stats */
708 u64 tx_deferral;
709 u64 tx_packets;
710 u64 rx_bytes;
711 u64 tx_pause;
712 u64 rx_pause;
713 u64 rx_drop_frame;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400714};
715
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500716#define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
717#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
718
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400719/* diagnostics */
720#define NV_TEST_COUNT_BASE 3
721#define NV_TEST_COUNT_EXTENDED 4
722
723static const struct nv_ethtool_str nv_etests_str[] = {
724 { "link (online/offline)" },
725 { "register (offline) " },
726 { "interrupt (offline) " },
727 { "loopback (offline) " }
728};
729
730struct register_test {
Al Viro5bb7ea22007-12-09 16:06:41 +0000731 __u32 reg;
732 __u32 mask;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400733};
734
735static const struct register_test nv_registers_test[] = {
736 { NvRegUnknownSetupReg6, 0x01 },
737 { NvRegMisc1, 0x03c },
738 { NvRegOffloadConfig, 0x03ff },
739 { NvRegMulticastAddrA, 0xffffffff },
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400740 { NvRegTxWatermark, 0x0ff },
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400741 { NvRegWakeUpFlags, 0x07777 },
742 { 0,0 }
743};
744
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500745struct nv_skb_map {
746 struct sk_buff *skb;
747 dma_addr_t dma;
748 unsigned int dma_len;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500749 struct ring_desc_ex *first_tx_desc;
750 struct nv_skb_map *next_tx_ctx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500751};
752
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753/*
754 * SMP locking:
755 * All hardware access under dev->priv->lock, except the performance
756 * critical parts:
757 * - rx is (pseudo-) lockless: it relies on the single-threading provided
758 * by the arch code for interrupts.
Herbert Xu932ff272006-06-09 12:20:56 -0700759 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 * needs dev->priv->lock :-(
Herbert Xu932ff272006-06-09 12:20:56 -0700761 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762 */
763
764/* in dev: base, irq */
765struct fe_priv {
766 spinlock_t lock;
767
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700768 struct net_device *dev;
769 struct napi_struct napi;
770
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771 /* General data:
772 * Locking: spin_lock(&np->lock); */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400773 struct nv_ethtool_stats estats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 int in_shutdown;
775 u32 linkspeed;
776 int duplex;
777 int autoneg;
778 int fixed_mode;
779 int phyaddr;
780 int wolenabled;
781 unsigned int phy_oui;
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400782 unsigned int phy_model;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 u16 gigabit;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400784 int intr_test;
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500785 int recover_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786
787 /* General data: RO fields */
788 dma_addr_t ring_addr;
789 struct pci_dev *pci_dev;
790 u32 orig_mac[2];
791 u32 irqmask;
792 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400793 u32 txrxctl_bits;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500794 u32 vlanctl_bits;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400795 u32 driver_data;
796 u32 register_size;
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -0400797 int rx_csum;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500798 u32 mac_in_use;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799
800 void __iomem *base;
801
802 /* rx specific fields.
803 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
804 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500805 union ring_type get_rx, put_rx, first_rx, last_rx;
806 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
807 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
808 struct nv_skb_map *rx_skb;
809
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700810 union ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200812 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813 struct timer_list oom_kick;
814 struct timer_list nic_poll;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400815 struct timer_list stats_poll;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500816 u32 nic_poll_irq;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400817 int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818
819 /* media detection workaround.
820 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
821 */
822 int need_linktimer;
823 unsigned long link_timeout;
824 /*
825 * tx specific fields.
826 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500827 union ring_type get_tx, put_tx, first_tx, last_tx;
828 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
829 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
830 struct nv_skb_map *tx_skb;
831
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700832 union ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 u32 tx_flags;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400834 int tx_ring_size;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500835 int tx_limit;
836 u32 tx_pkts_in_progress;
837 struct nv_skb_map *tx_change_owner;
838 struct nv_skb_map *tx_end_flip;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -0500839 int tx_stop;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500840
841 /* vlan fields */
842 struct vlan_group *vlangrp;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500843
844 /* msi/msi-x fields */
845 u32 msi_flags;
846 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400847
848 /* flow control */
849 u32 pause_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850};
851
852/*
853 * Maximum number of loops until we assume that a bit in the irq mask
854 * is stuck. Overridable with module param.
855 */
856static int max_interrupt_work = 5;
857
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500858/*
859 * Optimization can be either throuput mode or cpu mode
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400860 *
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500861 * Throughput Mode: Every tx and rx packet will generate an interrupt.
862 * CPU Mode: Interrupts are controlled by a timer.
863 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400864enum {
865 NV_OPTIMIZATION_MODE_THROUGHPUT,
866 NV_OPTIMIZATION_MODE_CPU
867};
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500868static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
869
870/*
871 * Poll interval for timer irq
872 *
873 * This interval determines how frequent an interrupt is generated.
874 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
875 * Min = 0, and Max = 65535
876 */
877static int poll_interval = -1;
878
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500879/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400880 * MSI interrupts
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500881 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400882enum {
883 NV_MSI_INT_DISABLED,
884 NV_MSI_INT_ENABLED
885};
886static int msi = NV_MSI_INT_ENABLED;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500887
888/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400889 * MSIX interrupts
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500890 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400891enum {
892 NV_MSIX_INT_DISABLED,
893 NV_MSIX_INT_ENABLED
894};
Ayaz Abdullacaf96462007-02-20 03:34:40 -0500895static int msix = NV_MSIX_INT_DISABLED;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400896
897/*
898 * DMA 64bit
899 */
900enum {
901 NV_DMA_64BIT_DISABLED,
902 NV_DMA_64BIT_ENABLED
903};
904static int dma_64bit = NV_DMA_64BIT_ENABLED;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -0500905
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906static inline struct fe_priv *get_nvpriv(struct net_device *dev)
907{
908 return netdev_priv(dev);
909}
910
911static inline u8 __iomem *get_hwbase(struct net_device *dev)
912{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400913 return ((struct fe_priv *)netdev_priv(dev))->base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914}
915
916static inline void pci_push(u8 __iomem *base)
917{
918 /* force out pending posted writes */
919 readl(base);
920}
921
922static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
923{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700924 return le32_to_cpu(prd->flaglen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
926}
927
Manfred Spraulee733622005-07-31 18:32:26 +0200928static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
929{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700930 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
Manfred Spraulee733622005-07-31 18:32:26 +0200931}
932
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
934 int delay, int delaymax, const char *msg)
935{
936 u8 __iomem *base = get_hwbase(dev);
937
938 pci_push(base);
939 do {
940 udelay(delay);
941 delaymax -= delay;
942 if (delaymax < 0) {
943 if (msg)
944 printk(msg);
945 return 1;
946 }
947 } while ((readl(base + offset) & mask) != target);
948 return 0;
949}
950
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500951#define NV_SETUP_RX_RING 0x01
952#define NV_SETUP_TX_RING 0x02
953
Al Viro5bb7ea22007-12-09 16:06:41 +0000954static inline u32 dma_low(dma_addr_t addr)
955{
956 return addr;
957}
958
959static inline u32 dma_high(dma_addr_t addr)
960{
961 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
962}
963
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500964static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
965{
966 struct fe_priv *np = get_nvpriv(dev);
967 u8 __iomem *base = get_hwbase(dev);
968
969 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
970 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000971 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500972 }
973 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000974 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500975 }
976 } else {
977 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000978 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
979 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500980 }
981 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000982 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
983 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500984 }
985 }
986}
987
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400988static void free_rings(struct net_device *dev)
989{
990 struct fe_priv *np = get_nvpriv(dev);
991
992 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700993 if (np->rx_ring.orig)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400994 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
995 np->rx_ring.orig, np->ring_addr);
996 } else {
997 if (np->rx_ring.ex)
998 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
999 np->rx_ring.ex, np->ring_addr);
1000 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001001 if (np->rx_skb)
1002 kfree(np->rx_skb);
1003 if (np->tx_skb)
1004 kfree(np->tx_skb);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001005}
1006
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001007static int using_multi_irqs(struct net_device *dev)
1008{
1009 struct fe_priv *np = get_nvpriv(dev);
1010
1011 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1012 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1013 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1014 return 0;
1015 else
1016 return 1;
1017}
1018
1019static void nv_enable_irq(struct net_device *dev)
1020{
1021 struct fe_priv *np = get_nvpriv(dev);
1022
1023 if (!using_multi_irqs(dev)) {
1024 if (np->msi_flags & NV_MSI_X_ENABLED)
1025 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1026 else
Manfred Spraula7475902007-10-17 21:52:33 +02001027 enable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001028 } else {
1029 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1030 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1031 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1032 }
1033}
1034
1035static void nv_disable_irq(struct net_device *dev)
1036{
1037 struct fe_priv *np = get_nvpriv(dev);
1038
1039 if (!using_multi_irqs(dev)) {
1040 if (np->msi_flags & NV_MSI_X_ENABLED)
1041 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1042 else
Manfred Spraula7475902007-10-17 21:52:33 +02001043 disable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001044 } else {
1045 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1046 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1047 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1048 }
1049}
1050
1051/* In MSIX mode, a write to irqmask behaves as XOR */
1052static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1053{
1054 u8 __iomem *base = get_hwbase(dev);
1055
1056 writel(mask, base + NvRegIrqMask);
1057}
1058
1059static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1060{
1061 struct fe_priv *np = get_nvpriv(dev);
1062 u8 __iomem *base = get_hwbase(dev);
1063
1064 if (np->msi_flags & NV_MSI_X_ENABLED) {
1065 writel(mask, base + NvRegIrqMask);
1066 } else {
1067 if (np->msi_flags & NV_MSI_ENABLED)
1068 writel(0, base + NvRegMSIIrqMask);
1069 writel(0, base + NvRegIrqMask);
1070 }
1071}
1072
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073#define MII_READ (-1)
1074/* mii_rw: read/write a register on the PHY.
1075 *
1076 * Caller must guarantee serialization
1077 */
1078static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1079{
1080 u8 __iomem *base = get_hwbase(dev);
1081 u32 reg;
1082 int retval;
1083
Ayaz Abdullaeb798422008-02-04 15:14:04 -05001084 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085
1086 reg = readl(base + NvRegMIIControl);
1087 if (reg & NVREG_MIICTL_INUSE) {
1088 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1089 udelay(NV_MIIBUSY_DELAY);
1090 }
1091
1092 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1093 if (value != MII_READ) {
1094 writel(value, base + NvRegMIIData);
1095 reg |= NVREG_MIICTL_WRITE;
1096 }
1097 writel(reg, base + NvRegMIIControl);
1098
1099 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1100 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1101 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1102 dev->name, miireg, addr);
1103 retval = -1;
1104 } else if (value != MII_READ) {
1105 /* it was a write operation - fewer failures are detectable */
1106 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1107 dev->name, value, miireg, addr);
1108 retval = 0;
1109 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1110 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1111 dev->name, miireg, addr);
1112 retval = -1;
1113 } else {
1114 retval = readl(base + NvRegMIIData);
1115 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1116 dev->name, miireg, addr, retval);
1117 }
1118
1119 return retval;
1120}
1121
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001122static int phy_reset(struct net_device *dev, u32 bmcr_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001124 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125 u32 miicontrol;
1126 unsigned int tries = 0;
1127
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001128 miicontrol = BMCR_RESET | bmcr_setup;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1130 return -1;
1131 }
1132
1133 /* wait for 500ms */
1134 msleep(500);
1135
1136 /* must wait till reset is deasserted */
1137 while (miicontrol & BMCR_RESET) {
1138 msleep(10);
1139 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1140 /* FIXME: 100 tries seem excessive */
1141 if (tries++ > 100)
1142 return -1;
1143 }
1144 return 0;
1145}
1146
1147static int phy_init(struct net_device *dev)
1148{
1149 struct fe_priv *np = get_nvpriv(dev);
1150 u8 __iomem *base = get_hwbase(dev);
1151 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1152
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001153 /* phy errata for E3016 phy */
1154 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1155 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1156 reg &= ~PHY_MARVELL_E3016_INITMASK;
1157 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1158 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1159 return PHY_ERROR;
1160 }
1161 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001162 if (np->phy_oui == PHY_OUI_REALTEK) {
1163 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1164 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165 return PHY_ERROR;
1166 }
1167 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1168 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1169 return PHY_ERROR;
1170 }
1171 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1172 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1173 return PHY_ERROR;
1174 }
1175 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1176 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1177 return PHY_ERROR;
1178 }
1179 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1180 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1181 return PHY_ERROR;
1182 }
1183 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001184
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185 /* set advertise register */
1186 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001187 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1189 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1190 return PHY_ERROR;
1191 }
1192
1193 /* get phy interface type */
1194 phyinterface = readl(base + NvRegPhyInterface);
1195
1196 /* see if gigabit phy */
1197 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1198 if (mii_status & PHY_GIGABIT) {
1199 np->gigabit = PHY_GIGABIT;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001200 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201 mii_control_1000 &= ~ADVERTISE_1000HALF;
1202 if (phyinterface & PHY_RGMII)
1203 mii_control_1000 |= ADVERTISE_1000FULL;
1204 else
1205 mii_control_1000 &= ~ADVERTISE_1000FULL;
1206
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001207 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209 return PHY_ERROR;
1210 }
1211 }
1212 else
1213 np->gigabit = 0;
1214
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001215 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1216 mii_control |= BMCR_ANENABLE;
1217
1218 /* reset the phy
1219 * (certain phys need bmcr to be setup with reset)
1220 */
1221 if (phy_reset(dev, mii_control)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1223 return PHY_ERROR;
1224 }
1225
1226 /* phy vendor specific configuration */
1227 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1228 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001229 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1230 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1232 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233 return PHY_ERROR;
1234 }
1235 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001236 phy_reserved |= PHY_CICADA_INIT5;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1238 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239 return PHY_ERROR;
1240 }
1241 }
1242 if (np->phy_oui == PHY_OUI_CICADA) {
1243 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001244 phy_reserved |= PHY_CICADA_INIT6;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1246 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1247 return PHY_ERROR;
1248 }
1249 }
Ayaz Abdullad215d8a2007-07-15 06:50:53 -04001250 if (np->phy_oui == PHY_OUI_VITESSE) {
1251 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1252 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1253 return PHY_ERROR;
1254 }
1255 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1256 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1257 return PHY_ERROR;
1258 }
1259 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1260 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1261 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1262 return PHY_ERROR;
1263 }
1264 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1265 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1266 phy_reserved |= PHY_VITESSE_INIT3;
1267 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1268 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1269 return PHY_ERROR;
1270 }
1271 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1272 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1273 return PHY_ERROR;
1274 }
1275 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1276 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1277 return PHY_ERROR;
1278 }
1279 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1280 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1281 phy_reserved |= PHY_VITESSE_INIT3;
1282 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1283 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284 return PHY_ERROR;
1285 }
1286 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1287 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1288 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1289 return PHY_ERROR;
1290 }
1291 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1292 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1293 return PHY_ERROR;
1294 }
1295 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1296 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1297 return PHY_ERROR;
1298 }
1299 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1300 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1301 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1302 return PHY_ERROR;
1303 }
1304 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1305 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1306 phy_reserved |= PHY_VITESSE_INIT8;
1307 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1308 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1309 return PHY_ERROR;
1310 }
1311 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1312 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1313 return PHY_ERROR;
1314 }
1315 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1316 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1317 return PHY_ERROR;
1318 }
1319 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001320 if (np->phy_oui == PHY_OUI_REALTEK) {
1321 /* reset could have cleared these out, set them back */
1322 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1323 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324 return PHY_ERROR;
1325 }
1326 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1327 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328 return PHY_ERROR;
1329 }
1330 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1331 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332 return PHY_ERROR;
1333 }
1334 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1335 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1336 return PHY_ERROR;
1337 }
1338 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1339 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1340 return PHY_ERROR;
1341 }
1342 }
1343
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001344 /* some phys clear out pause advertisment on reset, set it back */
1345 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001346
1347 /* restart auto negotiation */
1348 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1349 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1350 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1351 return PHY_ERROR;
1352 }
1353
1354 return 0;
1355}
1356
1357static void nv_start_rx(struct net_device *dev)
1358{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001359 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001360 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001361 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362
1363 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1364 /* Already running? Stop it. */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001365 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1366 rx_ctrl &= ~NVREG_RCVCTL_START;
1367 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368 pci_push(base);
1369 }
1370 writel(np->linkspeed, base + NvRegLinkSpeed);
1371 pci_push(base);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001372 rx_ctrl |= NVREG_RCVCTL_START;
1373 if (np->mac_in_use)
1374 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1375 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1377 dev->name, np->duplex, np->linkspeed);
1378 pci_push(base);
1379}
1380
1381static void nv_stop_rx(struct net_device *dev)
1382{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001383 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001384 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001385 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001386
1387 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001388 if (!np->mac_in_use)
1389 rx_ctrl &= ~NVREG_RCVCTL_START;
1390 else
1391 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1392 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001393 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1394 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1395 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1396
1397 udelay(NV_RXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001398 if (!np->mac_in_use)
1399 writel(0, base + NvRegLinkSpeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001400}
1401
1402static void nv_start_tx(struct net_device *dev)
1403{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001404 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001405 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001406 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407
1408 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001409 tx_ctrl |= NVREG_XMITCTL_START;
1410 if (np->mac_in_use)
1411 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1412 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413 pci_push(base);
1414}
1415
1416static void nv_stop_tx(struct net_device *dev)
1417{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001418 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001420 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421
1422 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001423 if (!np->mac_in_use)
1424 tx_ctrl &= ~NVREG_XMITCTL_START;
1425 else
1426 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1427 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001428 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1429 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1430 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1431
1432 udelay(NV_TXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001433 if (!np->mac_in_use)
1434 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1435 base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436}
1437
1438static void nv_txrx_reset(struct net_device *dev)
1439{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001440 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001441 u8 __iomem *base = get_hwbase(dev);
1442
1443 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001444 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445 pci_push(base);
1446 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001447 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448 pci_push(base);
1449}
1450
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001451static void nv_mac_reset(struct net_device *dev)
1452{
1453 struct fe_priv *np = netdev_priv(dev);
1454 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001455 u32 temp1, temp2, temp3;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001456
1457 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001458
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001459 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1460 pci_push(base);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001461
1462 /* save registers since they will be cleared on reset */
1463 temp1 = readl(base + NvRegMacAddrA);
1464 temp2 = readl(base + NvRegMacAddrB);
1465 temp3 = readl(base + NvRegTransmitPoll);
1466
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001467 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1468 pci_push(base);
1469 udelay(NV_MAC_RESET_DELAY);
1470 writel(0, base + NvRegMacReset);
1471 pci_push(base);
1472 udelay(NV_MAC_RESET_DELAY);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001473
1474 /* restore saved registers */
1475 writel(temp1, base + NvRegMacAddrA);
1476 writel(temp2, base + NvRegMacAddrB);
1477 writel(temp3, base + NvRegTransmitPoll);
1478
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001479 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1480 pci_push(base);
1481}
1482
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001483static void nv_get_hw_stats(struct net_device *dev)
1484{
1485 struct fe_priv *np = netdev_priv(dev);
1486 u8 __iomem *base = get_hwbase(dev);
1487
1488 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1489 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1490 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1491 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1492 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1493 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1494 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1495 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1496 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1497 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1498 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1499 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1500 np->estats.rx_runt += readl(base + NvRegRxRunt);
1501 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1502 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1503 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1504 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1505 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1506 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1507 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1508 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1509 np->estats.rx_packets =
1510 np->estats.rx_unicast +
1511 np->estats.rx_multicast +
1512 np->estats.rx_broadcast;
1513 np->estats.rx_errors_total =
1514 np->estats.rx_crc_errors +
1515 np->estats.rx_over_errors +
1516 np->estats.rx_frame_error +
1517 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1518 np->estats.rx_late_collision +
1519 np->estats.rx_runt +
1520 np->estats.rx_frame_too_long;
1521 np->estats.tx_errors_total =
1522 np->estats.tx_late_collision +
1523 np->estats.tx_fifo_errors +
1524 np->estats.tx_carrier_errors +
1525 np->estats.tx_excess_deferral +
1526 np->estats.tx_retry_error;
1527
1528 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1529 np->estats.tx_deferral += readl(base + NvRegTxDef);
1530 np->estats.tx_packets += readl(base + NvRegTxFrame);
1531 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1532 np->estats.tx_pause += readl(base + NvRegTxPause);
1533 np->estats.rx_pause += readl(base + NvRegRxPause);
1534 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1535 }
1536}
1537
Linus Torvalds1da177e2005-04-16 15:20:36 -07001538/*
1539 * nv_get_stats: dev->get_stats function
1540 * Get latest stats value from the nic.
1541 * Called with read_lock(&dev_base_lock) held for read -
1542 * only synchronized against unregister_netdevice.
1543 */
1544static struct net_device_stats *nv_get_stats(struct net_device *dev)
1545{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001546 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547
Ayaz Abdulla21828162007-01-23 12:27:21 -05001548 /* If the nic supports hw counters then retrieve latest values */
1549 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1550 nv_get_hw_stats(dev);
1551
1552 /* copy to net_device stats */
Jeff Garzik8148ff42007-10-16 20:56:09 -04001553 dev->stats.tx_bytes = np->estats.tx_bytes;
1554 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1555 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1556 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1557 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1558 dev->stats.rx_errors = np->estats.rx_errors_total;
1559 dev->stats.tx_errors = np->estats.tx_errors_total;
Ayaz Abdulla21828162007-01-23 12:27:21 -05001560 }
Jeff Garzik8148ff42007-10-16 20:56:09 -04001561
1562 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563}
1564
1565/*
1566 * nv_alloc_rx: fill rx ring entries.
1567 * Return 1 if the allocations for the skbs failed and the
1568 * rx engine is without Available descriptors
1569 */
1570static int nv_alloc_rx(struct net_device *dev)
1571{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001572 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001573 struct ring_desc* less_rx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001575 less_rx = np->get_rx.orig;
1576 if (less_rx-- == np->first_rx.orig)
1577 less_rx = np->last_rx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001578
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001579 while (np->put_rx.orig != less_rx) {
1580 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001581 if (skb) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001582 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001583 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1584 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001585 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001586 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001587 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001588 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1589 wmb();
1590 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001591 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001592 np->put_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001593 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001594 np->put_rx_ctx = np->first_rx_ctx;
1595 } else {
1596 return 1;
1597 }
1598 }
1599 return 0;
1600}
1601
1602static int nv_alloc_rx_optimized(struct net_device *dev)
1603{
1604 struct fe_priv *np = netdev_priv(dev);
1605 struct ring_desc_ex* less_rx;
1606
1607 less_rx = np->get_rx.ex;
1608 if (less_rx-- == np->first_rx.ex)
1609 less_rx = np->last_rx.ex;
1610
1611 while (np->put_rx.ex != less_rx) {
1612 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1613 if (skb) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001614 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001615 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1616 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001617 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001618 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001619 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Al Viro5bb7ea22007-12-09 16:06:41 +00001620 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1621 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001622 wmb();
1623 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001624 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001625 np->put_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001626 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001627 np->put_rx_ctx = np->first_rx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628 } else {
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001629 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001632 return 0;
1633}
1634
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001635/* If rx bufs are exhausted called after 50ms to attempt to refresh */
1636#ifdef CONFIG_FORCEDETH_NAPI
1637static void nv_do_rx_refill(unsigned long data)
1638{
1639 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001640 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001641
1642 /* Just reschedule NAPI rx processing */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001643 netif_rx_schedule(dev, &np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001644}
1645#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646static void nv_do_rx_refill(unsigned long data)
1647{
1648 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001649 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001650 int retcode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001651
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001652 if (!using_multi_irqs(dev)) {
1653 if (np->msi_flags & NV_MSI_X_ENABLED)
1654 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1655 else
Manfred Spraula7475902007-10-17 21:52:33 +02001656 disable_irq(np->pci_dev->irq);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05001657 } else {
1658 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1659 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001660 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1661 retcode = nv_alloc_rx(dev);
1662 else
1663 retcode = nv_alloc_rx_optimized(dev);
1664 if (retcode) {
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001665 spin_lock_irq(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001666 if (!np->in_shutdown)
1667 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001668 spin_unlock_irq(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001670 if (!using_multi_irqs(dev)) {
1671 if (np->msi_flags & NV_MSI_X_ENABLED)
1672 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1673 else
Manfred Spraula7475902007-10-17 21:52:33 +02001674 enable_irq(np->pci_dev->irq);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05001675 } else {
1676 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1677 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001678}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001679#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001680
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001681static void nv_init_rx(struct net_device *dev)
Manfred Sprauld81c0982005-07-31 18:20:30 +02001682{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001683 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001684 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001685 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1686 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1687 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1688 else
1689 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1690 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1691 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
Manfred Sprauld81c0982005-07-31 18:20:30 +02001692
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001693 for (i = 0; i < np->rx_ring_size; i++) {
1694 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001695 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001696 np->rx_ring.orig[i].buf = 0;
1697 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001698 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001699 np->rx_ring.ex[i].txvlan = 0;
1700 np->rx_ring.ex[i].bufhigh = 0;
1701 np->rx_ring.ex[i].buflow = 0;
1702 }
1703 np->rx_skb[i].skb = NULL;
1704 np->rx_skb[i].dma = 0;
1705 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001706}
1707
1708static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001709{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001710 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001711 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001712 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1713 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1714 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1715 else
1716 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1717 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1718 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001719 np->tx_pkts_in_progress = 0;
1720 np->tx_change_owner = NULL;
1721 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001722
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001723 for (i = 0; i < np->tx_ring_size; i++) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001724 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001725 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001726 np->tx_ring.orig[i].buf = 0;
1727 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001728 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001729 np->tx_ring.ex[i].txvlan = 0;
1730 np->tx_ring.ex[i].bufhigh = 0;
1731 np->tx_ring.ex[i].buflow = 0;
1732 }
1733 np->tx_skb[i].skb = NULL;
1734 np->tx_skb[i].dma = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001735 np->tx_skb[i].dma_len = 0;
1736 np->tx_skb[i].first_tx_desc = NULL;
1737 np->tx_skb[i].next_tx_ctx = NULL;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001738 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001739}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001740
Manfred Sprauld81c0982005-07-31 18:20:30 +02001741static int nv_init_ring(struct net_device *dev)
1742{
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001743 struct fe_priv *np = netdev_priv(dev);
1744
Manfred Sprauld81c0982005-07-31 18:20:30 +02001745 nv_init_tx(dev);
1746 nv_init_rx(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001747 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1748 return nv_alloc_rx(dev);
1749 else
1750 return nv_alloc_rx_optimized(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751}
1752
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001753static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001754{
1755 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08001756
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001757 if (tx_skb->dma) {
1758 pci_unmap_page(np->pci_dev, tx_skb->dma,
1759 tx_skb->dma_len,
Ayaz Abdullafa454592006-01-05 22:45:45 -08001760 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001761 tx_skb->dma = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001762 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001763 if (tx_skb->skb) {
1764 dev_kfree_skb_any(tx_skb->skb);
1765 tx_skb->skb = NULL;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001766 return 1;
1767 } else {
1768 return 0;
1769 }
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001770}
1771
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772static void nv_drain_tx(struct net_device *dev)
1773{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001774 struct fe_priv *np = netdev_priv(dev);
1775 unsigned int i;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001776
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001777 for (i = 0; i < np->tx_ring_size; i++) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001778 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001779 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001780 np->tx_ring.orig[i].buf = 0;
1781 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001782 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001783 np->tx_ring.ex[i].txvlan = 0;
1784 np->tx_ring.ex[i].bufhigh = 0;
1785 np->tx_ring.ex[i].buflow = 0;
1786 }
1787 if (nv_release_txskb(dev, &np->tx_skb[i]))
Jeff Garzik8148ff42007-10-16 20:56:09 -04001788 dev->stats.tx_dropped++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001789 np->tx_skb[i].dma = 0;
1790 np->tx_skb[i].dma_len = 0;
1791 np->tx_skb[i].first_tx_desc = NULL;
1792 np->tx_skb[i].next_tx_ctx = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001793 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001794 np->tx_pkts_in_progress = 0;
1795 np->tx_change_owner = NULL;
1796 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001797}
1798
1799static void nv_drain_rx(struct net_device *dev)
1800{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001801 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001802 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001803
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001804 for (i = 0; i < np->rx_ring_size; i++) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001805 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001806 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001807 np->rx_ring.orig[i].buf = 0;
1808 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001809 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001810 np->rx_ring.ex[i].txvlan = 0;
1811 np->rx_ring.ex[i].bufhigh = 0;
1812 np->rx_ring.ex[i].buflow = 0;
1813 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814 wmb();
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001815 if (np->rx_skb[i].skb) {
1816 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001817 (skb_end_pointer(np->rx_skb[i].skb) -
1818 np->rx_skb[i].skb->data),
1819 PCI_DMA_FROMDEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001820 dev_kfree_skb(np->rx_skb[i].skb);
1821 np->rx_skb[i].skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001822 }
1823 }
1824}
1825
1826static void drain_ring(struct net_device *dev)
1827{
1828 nv_drain_tx(dev);
1829 nv_drain_rx(dev);
1830}
1831
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001832static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1833{
1834 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1835}
1836
Linus Torvalds1da177e2005-04-16 15:20:36 -07001837/*
1838 * nv_start_xmit: dev->hard_start_xmit function
Herbert Xu932ff272006-06-09 12:20:56 -07001839 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001840 */
1841static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1842{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001843 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08001844 u32 tx_flags = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001845 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1846 unsigned int fragments = skb_shinfo(skb)->nr_frags;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001847 unsigned int i;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001848 u32 offset = 0;
1849 u32 bcnt;
1850 u32 size = skb->len-skb->data_len;
1851 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001852 u32 empty_slots;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001853 struct ring_desc* put_tx;
1854 struct ring_desc* start_tx;
1855 struct ring_desc* prev_tx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001856 struct nv_skb_map* prev_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001857
1858 /* add fragments to entries count */
1859 for (i = 0; i < fragments; i++) {
1860 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1861 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1862 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001863
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001864 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001865 if (unlikely(empty_slots <= entries)) {
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05001866 spin_lock_irq(&np->lock);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001867 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05001868 np->tx_stop = 1;
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05001869 spin_unlock_irq(&np->lock);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001870 return NETDEV_TX_BUSY;
1871 }
1872
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001873 start_tx = put_tx = np->put_tx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001874
Ayaz Abdullafa454592006-01-05 22:45:45 -08001875 /* setup the header buffer */
1876 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001877 prev_tx = put_tx;
1878 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001879 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001880 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
Ayaz Abdullafa454592006-01-05 22:45:45 -08001881 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001882 np->put_tx_ctx->dma_len = bcnt;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001883 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1884 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001885
Ayaz Abdullafa454592006-01-05 22:45:45 -08001886 tx_flags = np->tx_flags;
1887 offset += bcnt;
1888 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001889 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001890 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001891 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001892 np->put_tx_ctx = np->first_tx_ctx;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001893 } while (size);
Ayaz Abdullafa454592006-01-05 22:45:45 -08001894
1895 /* setup the fragments */
1896 for (i = 0; i < fragments; i++) {
1897 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1898 u32 size = frag->size;
1899 offset = 0;
1900
1901 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001902 prev_tx = put_tx;
1903 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001904 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001905 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1906 PCI_DMA_TODEVICE);
1907 np->put_tx_ctx->dma_len = bcnt;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001908 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1909 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001910
Ayaz Abdullafa454592006-01-05 22:45:45 -08001911 offset += bcnt;
1912 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001913 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001914 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001915 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001916 np->put_tx_ctx = np->first_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001917 } while (size);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001918 }
1919
Ayaz Abdullafa454592006-01-05 22:45:45 -08001920 /* set last fragment flag */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001921 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
Ayaz Abdullafa454592006-01-05 22:45:45 -08001922
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001923 /* save skb in this slot's context area */
1924 prev_tx_ctx->skb = skb;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001925
Herbert Xu89114af2006-07-08 13:34:32 -07001926 if (skb_is_gso(skb))
Herbert Xu79671682006-06-22 02:40:14 -07001927 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
Manfred Spraulee733622005-07-31 18:32:26 +02001928 else
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01001929 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
Patrick McHardy84fa7932006-08-29 16:44:56 -07001930 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001931
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05001932 spin_lock_irq(&np->lock);
1933
Ayaz Abdullafa454592006-01-05 22:45:45 -08001934 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001935 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1936 np->put_tx.orig = put_tx;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001937
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05001938 spin_unlock_irq(&np->lock);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001939
1940 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1941 dev->name, entries, tx_flags_extra);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942 {
1943 int j;
1944 for (j=0; j<64; j++) {
1945 if ((j%16) == 0)
1946 dprintk("\n%03x:", j);
1947 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1948 }
1949 dprintk("\n");
1950 }
1951
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952 dev->trans_start = jiffies;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001953 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001954 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001955}
1956
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001957static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1958{
1959 struct fe_priv *np = netdev_priv(dev);
1960 u32 tx_flags = 0;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001961 u32 tx_flags_extra;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001962 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1963 unsigned int i;
1964 u32 offset = 0;
1965 u32 bcnt;
1966 u32 size = skb->len-skb->data_len;
1967 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1968 u32 empty_slots;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001969 struct ring_desc_ex* put_tx;
1970 struct ring_desc_ex* start_tx;
1971 struct ring_desc_ex* prev_tx;
1972 struct nv_skb_map* prev_tx_ctx;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001973 struct nv_skb_map* start_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001974
1975 /* add fragments to entries count */
1976 for (i = 0; i < fragments; i++) {
1977 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1978 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1979 }
1980
1981 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05001982 if (unlikely(empty_slots <= entries)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001983 spin_lock_irq(&np->lock);
1984 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05001985 np->tx_stop = 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001986 spin_unlock_irq(&np->lock);
1987 return NETDEV_TX_BUSY;
1988 }
1989
1990 start_tx = put_tx = np->put_tx.ex;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001991 start_tx_ctx = np->put_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001992
1993 /* setup the header buffer */
1994 do {
1995 prev_tx = put_tx;
1996 prev_tx_ctx = np->put_tx_ctx;
1997 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1998 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1999 PCI_DMA_TODEVICE);
2000 np->put_tx_ctx->dma_len = bcnt;
Al Viro5bb7ea22007-12-09 16:06:41 +00002001 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2002 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002003 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002004
2005 tx_flags = NV_TX2_VALID;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002006 offset += bcnt;
2007 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002008 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002009 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002010 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002011 np->put_tx_ctx = np->first_tx_ctx;
2012 } while (size);
2013
2014 /* setup the fragments */
2015 for (i = 0; i < fragments; i++) {
2016 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2017 u32 size = frag->size;
2018 offset = 0;
2019
2020 do {
2021 prev_tx = put_tx;
2022 prev_tx_ctx = np->put_tx_ctx;
2023 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2024 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2025 PCI_DMA_TODEVICE);
2026 np->put_tx_ctx->dma_len = bcnt;
Al Viro5bb7ea22007-12-09 16:06:41 +00002027 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2028 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002029 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002030
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002031 offset += bcnt;
2032 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002033 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002034 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002035 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002036 np->put_tx_ctx = np->first_tx_ctx;
2037 } while (size);
2038 }
2039
2040 /* set last fragment flag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002041 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002042
2043 /* save skb in this slot's context area */
2044 prev_tx_ctx->skb = skb;
2045
2046 if (skb_is_gso(skb))
2047 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2048 else
2049 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2050 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2051
2052 /* vlan tag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002053 if (likely(!np->vlangrp)) {
2054 start_tx->txvlan = 0;
2055 } else {
2056 if (vlan_tx_tag_present(skb))
2057 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2058 else
2059 start_tx->txvlan = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002060 }
2061
2062 spin_lock_irq(&np->lock);
2063
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002064 if (np->tx_limit) {
2065 /* Limit the number of outstanding tx. Setup all fragments, but
2066 * do not set the VALID bit on the first descriptor. Save a pointer
2067 * to that descriptor and also for next skb_map element.
2068 */
2069
2070 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2071 if (!np->tx_change_owner)
2072 np->tx_change_owner = start_tx_ctx;
2073
2074 /* remove VALID bit */
2075 tx_flags &= ~NV_TX2_VALID;
2076 start_tx_ctx->first_tx_desc = start_tx;
2077 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2078 np->tx_end_flip = np->put_tx_ctx;
2079 } else {
2080 np->tx_pkts_in_progress++;
2081 }
2082 }
2083
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002084 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002085 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2086 np->put_tx.ex = put_tx;
2087
2088 spin_unlock_irq(&np->lock);
2089
2090 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2091 dev->name, entries, tx_flags_extra);
2092 {
2093 int j;
2094 for (j=0; j<64; j++) {
2095 if ((j%16) == 0)
2096 dprintk("\n%03x:", j);
2097 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2098 }
2099 dprintk("\n");
2100 }
2101
2102 dev->trans_start = jiffies;
2103 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002104 return NETDEV_TX_OK;
2105}
2106
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002107static inline void nv_tx_flip_ownership(struct net_device *dev)
2108{
2109 struct fe_priv *np = netdev_priv(dev);
2110
2111 np->tx_pkts_in_progress--;
2112 if (np->tx_change_owner) {
2113 __le32 flaglen = le32_to_cpu(np->tx_change_owner->first_tx_desc->flaglen);
2114 flaglen |= NV_TX2_VALID;
2115 np->tx_change_owner->first_tx_desc->flaglen = cpu_to_le32(flaglen);
2116 np->tx_pkts_in_progress++;
2117
2118 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2119 if (np->tx_change_owner == np->tx_end_flip)
2120 np->tx_change_owner = NULL;
2121
2122 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2123 }
2124}
2125
Linus Torvalds1da177e2005-04-16 15:20:36 -07002126/*
2127 * nv_tx_done: check for completed packets, release the skbs.
2128 *
2129 * Caller must own np->lock.
2130 */
2131static void nv_tx_done(struct net_device *dev)
2132{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002133 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002134 u32 flags;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002135 struct ring_desc* orig_get_tx = np->get_tx.orig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002136
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002137 while ((np->get_tx.orig != np->put_tx.orig) &&
2138 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002139
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002140 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2141 dev->name, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002142
2143 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2144 np->get_tx_ctx->dma_len,
2145 PCI_DMA_TODEVICE);
2146 np->get_tx_ctx->dma = 0;
2147
Linus Torvalds1da177e2005-04-16 15:20:36 -07002148 if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002149 if (flags & NV_TX_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002150 if (flags & NV_TX_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002151 if (flags & NV_TX_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002152 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002153 if (flags & NV_TX_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002154 dev->stats.tx_carrier_errors++;
2155 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002156 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002157 dev->stats.tx_packets++;
2158 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002159 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002160 dev_kfree_skb_any(np->get_tx_ctx->skb);
2161 np->get_tx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002162 }
2163 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002164 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002165 if (flags & NV_TX2_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002166 if (flags & NV_TX2_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002167 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002168 if (flags & NV_TX2_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002169 dev->stats.tx_carrier_errors++;
2170 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002171 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002172 dev->stats.tx_packets++;
2173 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002174 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002175 dev_kfree_skb_any(np->get_tx_ctx->skb);
2176 np->get_tx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002177 }
2178 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002179 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002180 np->get_tx.orig = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002181 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002182 np->get_tx_ctx = np->first_tx_ctx;
2183 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002184 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002185 np->tx_stop = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002186 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002187 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002188}
2189
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002190static void nv_tx_done_optimized(struct net_device *dev, int limit)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002191{
2192 struct fe_priv *np = netdev_priv(dev);
2193 u32 flags;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002194 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002195
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002196 while ((np->get_tx.ex != np->put_tx.ex) &&
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002197 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2198 (limit-- > 0)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002199
2200 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2201 dev->name, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002202
2203 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2204 np->get_tx_ctx->dma_len,
2205 PCI_DMA_TODEVICE);
2206 np->get_tx_ctx->dma = 0;
2207
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002208 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05002209 if (!(flags & NV_TX2_ERROR))
Jeff Garzik8148ff42007-10-16 20:56:09 -04002210 dev->stats.tx_packets++;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002211 dev_kfree_skb_any(np->get_tx_ctx->skb);
2212 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002213
2214 if (np->tx_limit) {
2215 nv_tx_flip_ownership(dev);
2216 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002217 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002218 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002219 np->get_tx.ex = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002220 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002221 np->get_tx_ctx = np->first_tx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002222 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002223 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002224 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002225 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002226 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002227}
2228
2229/*
2230 * nv_tx_timeout: dev->tx_timeout function
Herbert Xu932ff272006-06-09 12:20:56 -07002231 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002232 */
2233static void nv_tx_timeout(struct net_device *dev)
2234{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002235 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002236 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05002237 u32 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002238
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05002239 if (np->msi_flags & NV_MSI_X_ENABLED)
2240 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2241 else
2242 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2243
2244 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245
Manfred Spraulc2dba062005-07-31 18:29:47 +02002246 {
2247 int i;
2248
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002249 printk(KERN_INFO "%s: Ring at %lx\n",
2250 dev->name, (unsigned long)np->ring_addr);
Manfred Spraulc2dba062005-07-31 18:29:47 +02002251 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04002252 for (i=0;i<=np->register_size;i+= 32) {
Manfred Spraulc2dba062005-07-31 18:29:47 +02002253 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2254 i,
2255 readl(base + i + 0), readl(base + i + 4),
2256 readl(base + i + 8), readl(base + i + 12),
2257 readl(base + i + 16), readl(base + i + 20),
2258 readl(base + i + 24), readl(base + i + 28));
2259 }
2260 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002261 for (i=0;i<np->tx_ring_size;i+= 4) {
Manfred Spraulee733622005-07-31 18:32:26 +02002262 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2263 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002264 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002265 le32_to_cpu(np->tx_ring.orig[i].buf),
2266 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2267 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2268 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2269 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2270 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2271 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2272 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002273 } else {
2274 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002275 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002276 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2277 le32_to_cpu(np->tx_ring.ex[i].buflow),
2278 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2279 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2280 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2281 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2282 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2283 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2284 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2285 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2286 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2287 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002288 }
Manfred Spraulc2dba062005-07-31 18:29:47 +02002289 }
2290 }
2291
Linus Torvalds1da177e2005-04-16 15:20:36 -07002292 spin_lock_irq(&np->lock);
2293
2294 /* 1) stop tx engine */
2295 nv_stop_tx(dev);
2296
2297 /* 2) check that the packets were not sent already: */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002298 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2299 nv_tx_done(dev);
2300 else
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002301 nv_tx_done_optimized(dev, np->tx_ring_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002302
2303 /* 3) if there are dead entries: clear everything */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002304 if (np->get_tx_ctx != np->put_tx_ctx) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002305 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2306 nv_drain_tx(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002307 nv_init_tx(dev);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002308 setup_hw_rings(dev, NV_SETUP_TX_RING);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002309 }
2310
Ayaz Abdulla3ba4d092007-03-23 05:50:02 -05002311 netif_wake_queue(dev);
2312
Linus Torvalds1da177e2005-04-16 15:20:36 -07002313 /* 4) restart tx engine */
2314 nv_start_tx(dev);
2315 spin_unlock_irq(&np->lock);
2316}
2317
Manfred Spraul22c6d142005-04-19 21:17:09 +02002318/*
2319 * Called when the nic notices a mismatch between the actual data len on the
2320 * wire and the len indicated in the 802 header
2321 */
2322static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2323{
2324 int hdrlen; /* length of the 802 header */
2325 int protolen; /* length as stored in the proto field */
2326
2327 /* 1) calculate len according to header */
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002328 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
Manfred Spraul22c6d142005-04-19 21:17:09 +02002329 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2330 hdrlen = VLAN_HLEN;
2331 } else {
2332 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2333 hdrlen = ETH_HLEN;
2334 }
2335 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2336 dev->name, datalen, protolen, hdrlen);
2337 if (protolen > ETH_DATA_LEN)
2338 return datalen; /* Value in proto field not a len, no checks possible */
2339
2340 protolen += hdrlen;
2341 /* consistency checks: */
2342 if (datalen > ETH_ZLEN) {
2343 if (datalen >= protolen) {
2344 /* more data on wire than in 802 header, trim of
2345 * additional data.
2346 */
2347 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2348 dev->name, protolen);
2349 return protolen;
2350 } else {
2351 /* less data on wire than mentioned in header.
2352 * Discard the packet.
2353 */
2354 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2355 dev->name);
2356 return -1;
2357 }
2358 } else {
2359 /* short packet. Accept only if 802 values are also short */
2360 if (protolen > ETH_ZLEN) {
2361 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2362 dev->name);
2363 return -1;
2364 }
2365 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2366 dev->name, datalen);
2367 return datalen;
2368 }
2369}
2370
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002371static int nv_rx_process(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002372{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002373 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002374 u32 flags;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002375 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002376 struct sk_buff *skb;
2377 int len;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05002378
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002379 while((np->get_rx.orig != np->put_rx.orig) &&
2380 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002381 (rx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002382
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002383 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2384 dev->name, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002385
Linus Torvalds1da177e2005-04-16 15:20:36 -07002386 /*
2387 * the packet is for us - immediately tear down the pci mapping.
2388 * TODO: check if a prefetch of the first cacheline improves
2389 * the performance.
2390 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002391 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2392 np->get_rx_ctx->dma_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002393 PCI_DMA_FROMDEVICE);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002394 skb = np->get_rx_ctx->skb;
2395 np->get_rx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002396
2397 {
2398 int j;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002399 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400 for (j=0; j<64; j++) {
2401 if ((j%16) == 0)
2402 dprintk("\n%03x:", j);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002403 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002404 }
2405 dprintk("\n");
2406 }
2407 /* look at what we actually got: */
2408 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002409 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2410 len = flags & LEN_MASK_V1;
2411 if (unlikely(flags & NV_RX_ERROR)) {
2412 if (flags & NV_RX_ERROR4) {
2413 len = nv_getlen(dev, skb->data, len);
2414 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002415 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002416 dev_kfree_skb(skb);
2417 goto next_pkt;
2418 }
2419 }
2420 /* framing errors are soft errors */
2421 else if (flags & NV_RX_FRAMINGERR) {
2422 if (flags & NV_RX_SUBSTRACT1) {
2423 len--;
2424 }
2425 }
2426 /* the rest are hard errors */
2427 else {
2428 if (flags & NV_RX_MISSEDFRAME)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002429 dev->stats.rx_missed_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002430 if (flags & NV_RX_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002431 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002432 if (flags & NV_RX_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002433 dev->stats.rx_over_errors++;
2434 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002435 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002436 goto next_pkt;
2437 }
2438 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002439 } else {
2440 dev_kfree_skb(skb);
2441 goto next_pkt;
Manfred Spraul22c6d142005-04-19 21:17:09 +02002442 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002443 } else {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002444 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2445 len = flags & LEN_MASK_V2;
2446 if (unlikely(flags & NV_RX2_ERROR)) {
2447 if (flags & NV_RX2_ERROR4) {
2448 len = nv_getlen(dev, skb->data, len);
2449 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002450 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002451 dev_kfree_skb(skb);
2452 goto next_pkt;
2453 }
2454 }
2455 /* framing errors are soft errors */
2456 else if (flags & NV_RX2_FRAMINGERR) {
2457 if (flags & NV_RX2_SUBSTRACT1) {
2458 len--;
2459 }
2460 }
2461 /* the rest are hard errors */
2462 else {
2463 if (flags & NV_RX2_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002464 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002465 if (flags & NV_RX2_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002466 dev->stats.rx_over_errors++;
2467 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002468 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002469 goto next_pkt;
2470 }
2471 }
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002472 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2473 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002474 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002475 } else {
2476 dev_kfree_skb(skb);
2477 goto next_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002478 }
2479 }
2480 /* got a valid packet - forward it to the network core */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002481 skb_put(skb, len);
2482 skb->protocol = eth_type_trans(skb, dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002483 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2484 dev->name, len, skb->protocol);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002485#ifdef CONFIG_FORCEDETH_NAPI
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002486 netif_receive_skb(skb);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002487#else
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002488 netif_rx(skb);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002489#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002490 dev->last_rx = jiffies;
Jeff Garzik8148ff42007-10-16 20:56:09 -04002491 dev->stats.rx_packets++;
2492 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002493next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002494 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002495 np->get_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002496 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002497 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002498
2499 rx_work++;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002500 }
2501
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002502 return rx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002503}
2504
2505static int nv_rx_process_optimized(struct net_device *dev, int limit)
2506{
2507 struct fe_priv *np = netdev_priv(dev);
2508 u32 flags;
2509 u32 vlanflags = 0;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002510 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002511 struct sk_buff *skb;
2512 int len;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002513
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002514 while((np->get_rx.ex != np->put_rx.ex) &&
2515 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
Ingo Molnarc1b71512007-10-17 12:18:23 +02002516 (rx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002517
2518 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2519 dev->name, flags);
2520
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002521 /*
2522 * the packet is for us - immediately tear down the pci mapping.
2523 * TODO: check if a prefetch of the first cacheline improves
2524 * the performance.
2525 */
2526 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2527 np->get_rx_ctx->dma_len,
2528 PCI_DMA_FROMDEVICE);
2529 skb = np->get_rx_ctx->skb;
2530 np->get_rx_ctx->skb = NULL;
2531
2532 {
2533 int j;
2534 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2535 for (j=0; j<64; j++) {
2536 if ((j%16) == 0)
2537 dprintk("\n%03x:", j);
2538 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2539 }
2540 dprintk("\n");
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002541 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002542 /* look at what we actually got: */
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002543 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2544 len = flags & LEN_MASK_V2;
2545 if (unlikely(flags & NV_RX2_ERROR)) {
2546 if (flags & NV_RX2_ERROR4) {
2547 len = nv_getlen(dev, skb->data, len);
2548 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002549 dev_kfree_skb(skb);
2550 goto next_pkt;
2551 }
2552 }
2553 /* framing errors are soft errors */
2554 else if (flags & NV_RX2_FRAMINGERR) {
2555 if (flags & NV_RX2_SUBSTRACT1) {
2556 len--;
2557 }
2558 }
2559 /* the rest are hard errors */
2560 else {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002561 dev_kfree_skb(skb);
2562 goto next_pkt;
2563 }
2564 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002565
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002566 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2567 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002568 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002569
2570 /* got a valid packet - forward it to the network core */
2571 skb_put(skb, len);
2572 skb->protocol = eth_type_trans(skb, dev);
2573 prefetch(skb->data);
2574
2575 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2576 dev->name, len, skb->protocol);
2577
2578 if (likely(!np->vlangrp)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002579#ifdef CONFIG_FORCEDETH_NAPI
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002580 netif_receive_skb(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002581#else
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002582 netif_rx(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002583#endif
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002584 } else {
2585 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2586 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2587#ifdef CONFIG_FORCEDETH_NAPI
2588 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2589 vlanflags & NV_RX3_VLAN_TAG_MASK);
2590#else
2591 vlan_hwaccel_rx(skb, np->vlangrp,
2592 vlanflags & NV_RX3_VLAN_TAG_MASK);
2593#endif
2594 } else {
2595#ifdef CONFIG_FORCEDETH_NAPI
2596 netif_receive_skb(skb);
2597#else
2598 netif_rx(skb);
2599#endif
2600 }
2601 }
2602
2603 dev->last_rx = jiffies;
Jeff Garzik8148ff42007-10-16 20:56:09 -04002604 dev->stats.rx_packets++;
2605 dev->stats.rx_bytes += len;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002606 } else {
2607 dev_kfree_skb(skb);
2608 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002609next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002610 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002611 np->get_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002612 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002613 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002614
2615 rx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002616 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002617
Ingo Molnarc1b71512007-10-17 12:18:23 +02002618 return rx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002619}
2620
Manfred Sprauld81c0982005-07-31 18:20:30 +02002621static void set_bufsize(struct net_device *dev)
2622{
2623 struct fe_priv *np = netdev_priv(dev);
2624
2625 if (dev->mtu <= ETH_DATA_LEN)
2626 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2627 else
2628 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2629}
2630
Linus Torvalds1da177e2005-04-16 15:20:36 -07002631/*
2632 * nv_change_mtu: dev->change_mtu function
2633 * Called with dev_base_lock held for read.
2634 */
2635static int nv_change_mtu(struct net_device *dev, int new_mtu)
2636{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002637 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002638 int old_mtu;
2639
2640 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002641 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002642
2643 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002644 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002645
2646 /* return early if the buffer sizes will not change */
2647 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2648 return 0;
2649 if (old_mtu == new_mtu)
2650 return 0;
2651
2652 /* synchronized against open : rtnl_lock() held by caller */
2653 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002654 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002655 /*
2656 * It seems that the nic preloads valid ring entries into an
2657 * internal buffer. The procedure for flushing everything is
2658 * guessed, there is probably a simpler approach.
2659 * Changing the MTU is a rare event, it shouldn't matter.
2660 */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002661 nv_disable_irq(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002662 netif_tx_lock_bh(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002663 spin_lock(&np->lock);
2664 /* stop engines */
2665 nv_stop_rx(dev);
2666 nv_stop_tx(dev);
2667 nv_txrx_reset(dev);
2668 /* drain rx queue */
2669 nv_drain_rx(dev);
2670 nv_drain_tx(dev);
2671 /* reinit driver view of the rx queue */
Manfred Sprauld81c0982005-07-31 18:20:30 +02002672 set_bufsize(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002673 if (nv_init_ring(dev)) {
Manfred Sprauld81c0982005-07-31 18:20:30 +02002674 if (!np->in_shutdown)
2675 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2676 }
2677 /* reinit nic view of the rx queue */
2678 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002679 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002680 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Manfred Sprauld81c0982005-07-31 18:20:30 +02002681 base + NvRegRingSizes);
2682 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002683 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002684 pci_push(base);
2685
2686 /* restart rx engine */
2687 nv_start_rx(dev);
2688 nv_start_tx(dev);
2689 spin_unlock(&np->lock);
Herbert Xu932ff272006-06-09 12:20:56 -07002690 netif_tx_unlock_bh(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002691 nv_enable_irq(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002692 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002693 return 0;
2694}
2695
Manfred Spraul72b31782005-07-31 18:33:34 +02002696static void nv_copy_mac_to_hw(struct net_device *dev)
2697{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002698 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002699 u32 mac[2];
2700
2701 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2702 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2703 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2704
2705 writel(mac[0], base + NvRegMacAddrA);
2706 writel(mac[1], base + NvRegMacAddrB);
2707}
2708
2709/*
2710 * nv_set_mac_address: dev->set_mac_address function
2711 * Called with rtnl_lock() held.
2712 */
2713static int nv_set_mac_address(struct net_device *dev, void *addr)
2714{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002715 struct fe_priv *np = netdev_priv(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002716 struct sockaddr *macaddr = (struct sockaddr*)addr;
2717
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002718 if (!is_valid_ether_addr(macaddr->sa_data))
Manfred Spraul72b31782005-07-31 18:33:34 +02002719 return -EADDRNOTAVAIL;
2720
2721 /* synchronized against open : rtnl_lock() held by caller */
2722 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2723
2724 if (netif_running(dev)) {
Herbert Xu932ff272006-06-09 12:20:56 -07002725 netif_tx_lock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002726 spin_lock_irq(&np->lock);
2727
2728 /* stop rx engine */
2729 nv_stop_rx(dev);
2730
2731 /* set mac address */
2732 nv_copy_mac_to_hw(dev);
2733
2734 /* restart rx engine */
2735 nv_start_rx(dev);
2736 spin_unlock_irq(&np->lock);
Herbert Xu932ff272006-06-09 12:20:56 -07002737 netif_tx_unlock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002738 } else {
2739 nv_copy_mac_to_hw(dev);
2740 }
2741 return 0;
2742}
2743
Linus Torvalds1da177e2005-04-16 15:20:36 -07002744/*
2745 * nv_set_multicast: dev->set_multicast function
Herbert Xu932ff272006-06-09 12:20:56 -07002746 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002747 */
2748static void nv_set_multicast(struct net_device *dev)
2749{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002750 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002751 u8 __iomem *base = get_hwbase(dev);
2752 u32 addr[2];
2753 u32 mask[2];
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002754 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002755
2756 memset(addr, 0, sizeof(addr));
2757 memset(mask, 0, sizeof(mask));
2758
2759 if (dev->flags & IFF_PROMISC) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002760 pff |= NVREG_PFF_PROMISC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002761 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002762 pff |= NVREG_PFF_MYADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002763
2764 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2765 u32 alwaysOff[2];
2766 u32 alwaysOn[2];
2767
2768 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2769 if (dev->flags & IFF_ALLMULTI) {
2770 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2771 } else {
2772 struct dev_mc_list *walk;
2773
2774 walk = dev->mc_list;
2775 while (walk != NULL) {
2776 u32 a, b;
Al Viro5bb7ea22007-12-09 16:06:41 +00002777 a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2778 b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002779 alwaysOn[0] &= a;
2780 alwaysOff[0] &= ~a;
2781 alwaysOn[1] &= b;
2782 alwaysOff[1] &= ~b;
2783 walk = walk->next;
2784 }
2785 }
2786 addr[0] = alwaysOn[0];
2787 addr[1] = alwaysOn[1];
2788 mask[0] = alwaysOn[0] | alwaysOff[0];
2789 mask[1] = alwaysOn[1] | alwaysOff[1];
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05002790 } else {
2791 mask[0] = NVREG_MCASTMASKA_NONE;
2792 mask[1] = NVREG_MCASTMASKB_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002793 }
2794 }
2795 addr[0] |= NVREG_MCASTADDRA_FORCE;
2796 pff |= NVREG_PFF_ALWAYS;
2797 spin_lock_irq(&np->lock);
2798 nv_stop_rx(dev);
2799 writel(addr[0], base + NvRegMulticastAddrA);
2800 writel(addr[1], base + NvRegMulticastAddrB);
2801 writel(mask[0], base + NvRegMulticastMaskA);
2802 writel(mask[1], base + NvRegMulticastMaskB);
2803 writel(pff, base + NvRegPacketFilterFlags);
2804 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2805 dev->name);
2806 nv_start_rx(dev);
2807 spin_unlock_irq(&np->lock);
2808}
2809
Adrian Bunkc7985052006-06-22 12:03:29 +02002810static void nv_update_pause(struct net_device *dev, u32 pause_flags)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002811{
2812 struct fe_priv *np = netdev_priv(dev);
2813 u8 __iomem *base = get_hwbase(dev);
2814
2815 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2816
2817 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2818 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2819 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2820 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2821 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2822 } else {
2823 writel(pff, base + NvRegPacketFilterFlags);
2824 }
2825 }
2826 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2827 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2828 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05002829 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
2830 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
2831 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
2832 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
2833 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
2834 writel(pause_enable, base + NvRegTxPauseFrame);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002835 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2836 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2837 } else {
2838 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2839 writel(regmisc, base + NvRegMisc1);
2840 }
2841 }
2842}
2843
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05002844/**
2845 * nv_update_linkspeed: Setup the MAC according to the link partner
2846 * @dev: Network device to be configured
2847 *
2848 * The function queries the PHY and checks if there is a link partner.
2849 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2850 * set to 10 MBit HD.
2851 *
2852 * The function returns 0 if there is no link partner and 1 if there is
2853 * a good link partner.
2854 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002855static int nv_update_linkspeed(struct net_device *dev)
2856{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002857 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002858 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04002859 int adv = 0;
2860 int lpa = 0;
2861 int adv_lpa, adv_pause, lpa_pause;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002862 int newls = np->linkspeed;
2863 int newdup = np->duplex;
2864 int mii_status;
2865 int retval = 0;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04002866 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
Ayaz Abdullab2976d22008-02-04 15:13:59 -05002867 u32 txrxFlags = 0;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05002868 u32 phy_exp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002869
2870 /* BMSR_LSTATUS is latched, read it twice:
2871 * we want the current value.
2872 */
2873 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2874 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2875
2876 if (!(mii_status & BMSR_LSTATUS)) {
2877 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2878 dev->name);
2879 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2880 newdup = 0;
2881 retval = 0;
2882 goto set_speed;
2883 }
2884
2885 if (np->autoneg == 0) {
2886 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2887 dev->name, np->fixed_mode);
2888 if (np->fixed_mode & LPA_100FULL) {
2889 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2890 newdup = 1;
2891 } else if (np->fixed_mode & LPA_100HALF) {
2892 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2893 newdup = 0;
2894 } else if (np->fixed_mode & LPA_10FULL) {
2895 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2896 newdup = 1;
2897 } else {
2898 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2899 newdup = 0;
2900 }
2901 retval = 1;
2902 goto set_speed;
2903 }
2904 /* check auto negotiation is complete */
2905 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2906 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2907 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2908 newdup = 0;
2909 retval = 0;
2910 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2911 goto set_speed;
2912 }
2913
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002914 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2915 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2916 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2917 dev->name, adv, lpa);
2918
Linus Torvalds1da177e2005-04-16 15:20:36 -07002919 retval = 1;
2920 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04002921 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2922 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002923
2924 if ((control_1000 & ADVERTISE_1000FULL) &&
2925 (status_1000 & LPA_1000FULL)) {
2926 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2927 dev->name);
2928 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2929 newdup = 1;
2930 goto set_speed;
2931 }
2932 }
2933
Linus Torvalds1da177e2005-04-16 15:20:36 -07002934 /* FIXME: handle parallel detection properly */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04002935 adv_lpa = lpa & adv;
2936 if (adv_lpa & LPA_100FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002937 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2938 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04002939 } else if (adv_lpa & LPA_100HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002940 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2941 newdup = 0;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04002942 } else if (adv_lpa & LPA_10FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002943 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2944 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04002945 } else if (adv_lpa & LPA_10HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002946 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2947 newdup = 0;
2948 } else {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04002949 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002950 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2951 newdup = 0;
2952 }
2953
2954set_speed:
2955 if (np->duplex == newdup && np->linkspeed == newls)
2956 return retval;
2957
2958 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2959 dev->name, np->linkspeed, np->duplex, newls, newdup);
2960
2961 np->duplex = newdup;
2962 np->linkspeed = newls;
2963
Ayaz Abdullab2976d22008-02-04 15:13:59 -05002964 /* The transmitter and receiver must be restarted for safe update */
2965 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
2966 txrxFlags |= NV_RESTART_TX;
2967 nv_stop_tx(dev);
2968 }
2969 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
2970 txrxFlags |= NV_RESTART_RX;
2971 nv_stop_rx(dev);
2972 }
2973
Linus Torvalds1da177e2005-04-16 15:20:36 -07002974 if (np->gigabit == PHY_GIGABIT) {
2975 phyreg = readl(base + NvRegRandomSeed);
2976 phyreg &= ~(0x3FF00);
2977 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2978 phyreg |= NVREG_RNDSEED_FORCE3;
2979 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2980 phyreg |= NVREG_RNDSEED_FORCE2;
2981 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2982 phyreg |= NVREG_RNDSEED_FORCE;
2983 writel(phyreg, base + NvRegRandomSeed);
2984 }
2985
2986 phyreg = readl(base + NvRegPhyInterface);
2987 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2988 if (np->duplex == 0)
2989 phyreg |= PHY_HALF;
2990 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2991 phyreg |= PHY_100;
2992 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2993 phyreg |= PHY_1000;
2994 writel(phyreg, base + NvRegPhyInterface);
2995
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05002996 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
Ayaz Abdulla9744e212006-07-06 16:45:58 -04002997 if (phyreg & PHY_RGMII) {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05002998 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
Ayaz Abdulla9744e212006-07-06 16:45:58 -04002999 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003000 } else {
3001 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3002 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3003 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3004 else
3005 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3006 } else {
3007 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3008 }
3009 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003010 } else {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003011 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3012 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3013 else
3014 txreg = NVREG_TX_DEFERRAL_DEFAULT;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003015 }
3016 writel(txreg, base + NvRegTxDeferral);
3017
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04003018 if (np->desc_ver == DESC_VER_1) {
3019 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3020 } else {
3021 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3022 txreg = NVREG_TX_WM_DESC2_3_1000;
3023 else
3024 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3025 }
3026 writel(txreg, base + NvRegTxWatermark);
3027
Linus Torvalds1da177e2005-04-16 15:20:36 -07003028 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3029 base + NvRegMisc1);
3030 pci_push(base);
3031 writel(np->linkspeed, base + NvRegLinkSpeed);
3032 pci_push(base);
3033
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003034 pause_flags = 0;
3035 /* setup pause frame */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003036 if (np->duplex != 0) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003037 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3038 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3039 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003040
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003041 switch (adv_pause) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003042 case ADVERTISE_PAUSE_CAP:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003043 if (lpa_pause & LPA_PAUSE_CAP) {
3044 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3045 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3046 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3047 }
3048 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003049 case ADVERTISE_PAUSE_ASYM:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003050 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3051 {
3052 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3053 }
3054 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003055 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003056 if (lpa_pause & LPA_PAUSE_CAP)
3057 {
3058 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3059 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3060 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3061 }
3062 if (lpa_pause == LPA_PAUSE_ASYM)
3063 {
3064 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3065 }
3066 break;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003067 }
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003068 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003069 pause_flags = np->pause_flags;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003070 }
3071 }
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003072 nv_update_pause(dev, pause_flags);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003073
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003074 if (txrxFlags & NV_RESTART_TX)
3075 nv_start_tx(dev);
3076 if (txrxFlags & NV_RESTART_RX)
3077 nv_start_rx(dev);
3078
Linus Torvalds1da177e2005-04-16 15:20:36 -07003079 return retval;
3080}
3081
3082static void nv_linkchange(struct net_device *dev)
3083{
3084 if (nv_update_linkspeed(dev)) {
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003085 if (!netif_carrier_ok(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003086 netif_carrier_on(dev);
3087 printk(KERN_INFO "%s: link up.\n", dev->name);
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003088 nv_start_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003089 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003090 } else {
3091 if (netif_carrier_ok(dev)) {
3092 netif_carrier_off(dev);
3093 printk(KERN_INFO "%s: link down.\n", dev->name);
3094 nv_stop_rx(dev);
3095 }
3096 }
3097}
3098
3099static void nv_link_irq(struct net_device *dev)
3100{
3101 u8 __iomem *base = get_hwbase(dev);
3102 u32 miistat;
3103
3104 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05003105 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003106 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3107
3108 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3109 nv_linkchange(dev);
3110 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3111}
3112
David Howells7d12e782006-10-05 14:55:46 +01003113static irqreturn_t nv_nic_irq(int foo, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003114{
3115 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003116 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003117 u8 __iomem *base = get_hwbase(dev);
3118 u32 events;
3119 int i;
3120
3121 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3122
3123 for (i=0; ; i++) {
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003124 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3125 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3126 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3127 } else {
3128 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3129 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3130 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003131 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3132 if (!(events & np->irqmask))
3133 break;
3134
Ayaz Abdullaa971c322005-11-11 08:30:38 -05003135 spin_lock(&np->lock);
3136 nv_tx_done(dev);
3137 spin_unlock(&np->lock);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003138
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003139#ifdef CONFIG_FORCEDETH_NAPI
3140 if (events & NVREG_IRQ_RX_ALL) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003141 netif_rx_schedule(dev, &np->napi);
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003142
3143 /* Disable furthur receive irq's */
3144 spin_lock(&np->lock);
3145 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3146
3147 if (np->msi_flags & NV_MSI_X_ENABLED)
3148 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3149 else
3150 writel(np->irqmask, base + NvRegIrqMask);
3151 spin_unlock(&np->lock);
3152 }
3153#else
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003154 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003155 if (unlikely(nv_alloc_rx(dev))) {
3156 spin_lock(&np->lock);
3157 if (!np->in_shutdown)
3158 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3159 spin_unlock(&np->lock);
3160 }
3161 }
3162#endif
3163 if (unlikely(events & NVREG_IRQ_LINK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003164 spin_lock(&np->lock);
3165 nv_link_irq(dev);
3166 spin_unlock(&np->lock);
3167 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003168 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003169 spin_lock(&np->lock);
3170 nv_linkchange(dev);
3171 spin_unlock(&np->lock);
3172 np->link_timeout = jiffies + LINK_TIMEOUT;
3173 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003174 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003175 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3176 dev->name, events);
3177 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003178 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003179 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3180 dev->name, events);
3181 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003182 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3183 spin_lock(&np->lock);
3184 /* disable interrupts on the nic */
3185 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3186 writel(0, base + NvRegIrqMask);
3187 else
3188 writel(np->irqmask, base + NvRegIrqMask);
3189 pci_push(base);
3190
3191 if (!np->in_shutdown) {
3192 np->nic_poll_irq = np->irqmask;
3193 np->recover_error = 1;
3194 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3195 }
3196 spin_unlock(&np->lock);
3197 break;
3198 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003199 if (unlikely(i > max_interrupt_work)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003200 spin_lock(&np->lock);
3201 /* disable interrupts on the nic */
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003202 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3203 writel(0, base + NvRegIrqMask);
3204 else
3205 writel(np->irqmask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003206 pci_push(base);
3207
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003208 if (!np->in_shutdown) {
3209 np->nic_poll_irq = np->irqmask;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003210 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003211 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003212 spin_unlock(&np->lock);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003213 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003214 break;
3215 }
3216
3217 }
3218 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3219
3220 return IRQ_RETVAL(i);
3221}
3222
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003223/**
3224 * All _optimized functions are used to help increase performance
3225 * (reduce CPU and increase throughput). They use descripter version 3,
3226 * compiler directives, and reduce memory accesses.
3227 */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003228static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3229{
3230 struct net_device *dev = (struct net_device *) data;
3231 struct fe_priv *np = netdev_priv(dev);
3232 u8 __iomem *base = get_hwbase(dev);
3233 u32 events;
3234 int i;
3235
3236 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3237
3238 for (i=0; ; i++) {
3239 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3240 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3241 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3242 } else {
3243 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3244 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3245 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003246 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3247 if (!(events & np->irqmask))
3248 break;
3249
3250 spin_lock(&np->lock);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003251 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003252 spin_unlock(&np->lock);
3253
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003254#ifdef CONFIG_FORCEDETH_NAPI
3255 if (events & NVREG_IRQ_RX_ALL) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003256 netif_rx_schedule(dev, &np->napi);
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003257
3258 /* Disable furthur receive irq's */
3259 spin_lock(&np->lock);
3260 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3261
3262 if (np->msi_flags & NV_MSI_X_ENABLED)
3263 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3264 else
3265 writel(np->irqmask, base + NvRegIrqMask);
3266 spin_unlock(&np->lock);
3267 }
3268#else
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003269 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003270 if (unlikely(nv_alloc_rx_optimized(dev))) {
3271 spin_lock(&np->lock);
3272 if (!np->in_shutdown)
3273 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3274 spin_unlock(&np->lock);
3275 }
3276 }
3277#endif
3278 if (unlikely(events & NVREG_IRQ_LINK)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003279 spin_lock(&np->lock);
3280 nv_link_irq(dev);
3281 spin_unlock(&np->lock);
3282 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003283 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003284 spin_lock(&np->lock);
3285 nv_linkchange(dev);
3286 spin_unlock(&np->lock);
3287 np->link_timeout = jiffies + LINK_TIMEOUT;
3288 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003289 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003290 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3291 dev->name, events);
3292 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003293 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003294 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3295 dev->name, events);
3296 }
3297 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3298 spin_lock(&np->lock);
3299 /* disable interrupts on the nic */
3300 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3301 writel(0, base + NvRegIrqMask);
3302 else
3303 writel(np->irqmask, base + NvRegIrqMask);
3304 pci_push(base);
3305
3306 if (!np->in_shutdown) {
3307 np->nic_poll_irq = np->irqmask;
3308 np->recover_error = 1;
3309 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3310 }
3311 spin_unlock(&np->lock);
3312 break;
3313 }
3314
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003315 if (unlikely(i > max_interrupt_work)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003316 spin_lock(&np->lock);
3317 /* disable interrupts on the nic */
3318 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3319 writel(0, base + NvRegIrqMask);
3320 else
3321 writel(np->irqmask, base + NvRegIrqMask);
3322 pci_push(base);
3323
3324 if (!np->in_shutdown) {
3325 np->nic_poll_irq = np->irqmask;
3326 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3327 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003328 spin_unlock(&np->lock);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003329 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003330 break;
3331 }
3332
3333 }
3334 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3335
3336 return IRQ_RETVAL(i);
3337}
3338
David Howells7d12e782006-10-05 14:55:46 +01003339static irqreturn_t nv_nic_irq_tx(int foo, void *data)
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003340{
3341 struct net_device *dev = (struct net_device *) data;
3342 struct fe_priv *np = netdev_priv(dev);
3343 u8 __iomem *base = get_hwbase(dev);
3344 u32 events;
3345 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003346 unsigned long flags;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003347
3348 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3349
3350 for (i=0; ; i++) {
3351 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3352 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003353 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3354 if (!(events & np->irqmask))
3355 break;
3356
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003357 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003358 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003359 spin_unlock_irqrestore(&np->lock, flags);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003360
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003361 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003362 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3363 dev->name, events);
3364 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003365 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003366 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003367 /* disable interrupts on the nic */
3368 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3369 pci_push(base);
3370
3371 if (!np->in_shutdown) {
3372 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3373 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3374 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003375 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003376 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003377 break;
3378 }
3379
3380 }
3381 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3382
3383 return IRQ_RETVAL(i);
3384}
3385
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003386#ifdef CONFIG_FORCEDETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003387static int nv_napi_poll(struct napi_struct *napi, int budget)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003388{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003389 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3390 struct net_device *dev = np->dev;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003391 u8 __iomem *base = get_hwbase(dev);
Francois Romieud15e9c42006-12-17 23:03:15 +01003392 unsigned long flags;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003393 int pkts, retcode;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003394
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003395 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003396 pkts = nv_rx_process(dev, budget);
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003397 retcode = nv_alloc_rx(dev);
3398 } else {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003399 pkts = nv_rx_process_optimized(dev, budget);
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003400 retcode = nv_alloc_rx_optimized(dev);
3401 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003402
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003403 if (retcode) {
Francois Romieud15e9c42006-12-17 23:03:15 +01003404 spin_lock_irqsave(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003405 if (!np->in_shutdown)
3406 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Francois Romieud15e9c42006-12-17 23:03:15 +01003407 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003408 }
3409
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003410 if (pkts < budget) {
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003411 /* re-enable receive interrupts */
Francois Romieud15e9c42006-12-17 23:03:15 +01003412 spin_lock_irqsave(&np->lock, flags);
3413
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003414 __netif_rx_complete(dev, napi);
3415
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003416 np->irqmask |= NVREG_IRQ_RX_ALL;
3417 if (np->msi_flags & NV_MSI_X_ENABLED)
3418 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3419 else
3420 writel(np->irqmask, base + NvRegIrqMask);
Francois Romieud15e9c42006-12-17 23:03:15 +01003421
3422 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003423 }
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003424 return pkts;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003425}
3426#endif
3427
3428#ifdef CONFIG_FORCEDETH_NAPI
David Howells7d12e782006-10-05 14:55:46 +01003429static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003430{
3431 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003432 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003433 u8 __iomem *base = get_hwbase(dev);
3434 u32 events;
3435
3436 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3437 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3438
3439 if (events) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003440 netif_rx_schedule(dev, &np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003441 /* disable receive interrupts on the nic */
3442 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3443 pci_push(base);
3444 }
3445 return IRQ_HANDLED;
3446}
3447#else
David Howells7d12e782006-10-05 14:55:46 +01003448static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003449{
3450 struct net_device *dev = (struct net_device *) data;
3451 struct fe_priv *np = netdev_priv(dev);
3452 u8 __iomem *base = get_hwbase(dev);
3453 u32 events;
3454 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003455 unsigned long flags;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003456
3457 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3458
3459 for (i=0; ; i++) {
3460 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3461 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003462 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3463 if (!(events & np->irqmask))
3464 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003465
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003466 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003467 if (unlikely(nv_alloc_rx_optimized(dev))) {
3468 spin_lock_irqsave(&np->lock, flags);
3469 if (!np->in_shutdown)
3470 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3471 spin_unlock_irqrestore(&np->lock, flags);
3472 }
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003473 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003474
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003475 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003476 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003477 /* disable interrupts on the nic */
3478 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3479 pci_push(base);
3480
3481 if (!np->in_shutdown) {
3482 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3483 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3484 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003485 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003486 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003487 break;
3488 }
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003489 }
3490 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3491
3492 return IRQ_RETVAL(i);
3493}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003494#endif
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003495
David Howells7d12e782006-10-05 14:55:46 +01003496static irqreturn_t nv_nic_irq_other(int foo, void *data)
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003497{
3498 struct net_device *dev = (struct net_device *) data;
3499 struct fe_priv *np = netdev_priv(dev);
3500 u8 __iomem *base = get_hwbase(dev);
3501 u32 events;
3502 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003503 unsigned long flags;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003504
3505 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3506
3507 for (i=0; ; i++) {
3508 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3509 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003510 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3511 if (!(events & np->irqmask))
3512 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003513
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003514 /* check tx in case we reached max loop limit in tx isr */
3515 spin_lock_irqsave(&np->lock, flags);
3516 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3517 spin_unlock_irqrestore(&np->lock, flags);
3518
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003519 if (events & NVREG_IRQ_LINK) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003520 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003521 nv_link_irq(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003522 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003523 }
3524 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003525 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003526 nv_linkchange(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003527 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003528 np->link_timeout = jiffies + LINK_TIMEOUT;
3529 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003530 if (events & NVREG_IRQ_RECOVER_ERROR) {
3531 spin_lock_irq(&np->lock);
3532 /* disable interrupts on the nic */
3533 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3534 pci_push(base);
3535
3536 if (!np->in_shutdown) {
3537 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3538 np->recover_error = 1;
3539 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3540 }
3541 spin_unlock_irq(&np->lock);
3542 break;
3543 }
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003544 if (events & (NVREG_IRQ_UNKNOWN)) {
3545 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3546 dev->name, events);
3547 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003548 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003549 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003550 /* disable interrupts on the nic */
3551 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3552 pci_push(base);
3553
3554 if (!np->in_shutdown) {
3555 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3556 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3557 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003558 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003559 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003560 break;
3561 }
3562
3563 }
3564 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3565
3566 return IRQ_RETVAL(i);
3567}
3568
David Howells7d12e782006-10-05 14:55:46 +01003569static irqreturn_t nv_nic_irq_test(int foo, void *data)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003570{
3571 struct net_device *dev = (struct net_device *) data;
3572 struct fe_priv *np = netdev_priv(dev);
3573 u8 __iomem *base = get_hwbase(dev);
3574 u32 events;
3575
3576 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3577
3578 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3579 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3580 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3581 } else {
3582 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3583 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3584 }
3585 pci_push(base);
3586 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3587 if (!(events & NVREG_IRQ_TIMER))
3588 return IRQ_RETVAL(0);
3589
3590 spin_lock(&np->lock);
3591 np->intr_test = 1;
3592 spin_unlock(&np->lock);
3593
3594 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3595
3596 return IRQ_RETVAL(1);
3597}
3598
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003599static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3600{
3601 u8 __iomem *base = get_hwbase(dev);
3602 int i;
3603 u32 msixmap = 0;
3604
3605 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3606 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3607 * the remaining 8 interrupts.
3608 */
3609 for (i = 0; i < 8; i++) {
3610 if ((irqmask >> i) & 0x1) {
3611 msixmap |= vector << (i << 2);
3612 }
3613 }
3614 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3615
3616 msixmap = 0;
3617 for (i = 0; i < 8; i++) {
3618 if ((irqmask >> (i + 8)) & 0x1) {
3619 msixmap |= vector << (i << 2);
3620 }
3621 }
3622 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3623}
3624
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003625static int nv_request_irq(struct net_device *dev, int intr_test)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003626{
3627 struct fe_priv *np = get_nvpriv(dev);
3628 u8 __iomem *base = get_hwbase(dev);
3629 int ret = 1;
3630 int i;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003631 irqreturn_t (*handler)(int foo, void *data);
3632
3633 if (intr_test) {
3634 handler = nv_nic_irq_test;
3635 } else {
3636 if (np->desc_ver == DESC_VER_3)
3637 handler = nv_nic_irq_optimized;
3638 else
3639 handler = nv_nic_irq;
3640 }
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003641
3642 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3643 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3644 np->msi_x_entry[i].entry = i;
3645 }
3646 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3647 np->msi_flags |= NV_MSI_X_ENABLED;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003648 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003649 /* Request irq for rx handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003650 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003651 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3652 pci_disable_msix(np->pci_dev);
3653 np->msi_flags &= ~NV_MSI_X_ENABLED;
3654 goto out_err;
3655 }
3656 /* Request irq for tx handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003657 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003658 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3659 pci_disable_msix(np->pci_dev);
3660 np->msi_flags &= ~NV_MSI_X_ENABLED;
3661 goto out_free_rx;
3662 }
3663 /* Request irq for link and timer handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003664 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003665 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3666 pci_disable_msix(np->pci_dev);
3667 np->msi_flags &= ~NV_MSI_X_ENABLED;
3668 goto out_free_tx;
3669 }
3670 /* map interrupts to their respective vector */
3671 writel(0, base + NvRegMSIXMap0);
3672 writel(0, base + NvRegMSIXMap1);
3673 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3674 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3675 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3676 } else {
3677 /* Request irq for all interrupts */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003678 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003679 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3680 pci_disable_msix(np->pci_dev);
3681 np->msi_flags &= ~NV_MSI_X_ENABLED;
3682 goto out_err;
3683 }
3684
3685 /* map interrupts to vector 0 */
3686 writel(0, base + NvRegMSIXMap0);
3687 writel(0, base + NvRegMSIXMap1);
3688 }
3689 }
3690 }
3691 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3692 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3693 np->msi_flags |= NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003694 dev->irq = np->pci_dev->irq;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003695 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003696 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3697 pci_disable_msi(np->pci_dev);
3698 np->msi_flags &= ~NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003699 dev->irq = np->pci_dev->irq;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003700 goto out_err;
3701 }
3702
3703 /* map interrupts to vector 0 */
3704 writel(0, base + NvRegMSIMap0);
3705 writel(0, base + NvRegMSIMap1);
3706 /* enable msi vector 0 */
3707 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3708 }
3709 }
3710 if (ret != 0) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003711 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003712 goto out_err;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003713
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003714 }
3715
3716 return 0;
3717out_free_tx:
3718 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3719out_free_rx:
3720 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3721out_err:
3722 return 1;
3723}
3724
3725static void nv_free_irq(struct net_device *dev)
3726{
3727 struct fe_priv *np = get_nvpriv(dev);
3728 int i;
3729
3730 if (np->msi_flags & NV_MSI_X_ENABLED) {
3731 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3732 free_irq(np->msi_x_entry[i].vector, dev);
3733 }
3734 pci_disable_msix(np->pci_dev);
3735 np->msi_flags &= ~NV_MSI_X_ENABLED;
3736 } else {
3737 free_irq(np->pci_dev->irq, dev);
3738 if (np->msi_flags & NV_MSI_ENABLED) {
3739 pci_disable_msi(np->pci_dev);
3740 np->msi_flags &= ~NV_MSI_ENABLED;
3741 }
3742 }
3743}
3744
Linus Torvalds1da177e2005-04-16 15:20:36 -07003745static void nv_do_nic_poll(unsigned long data)
3746{
3747 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003748 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003749 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003750 u32 mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003751
Linus Torvalds1da177e2005-04-16 15:20:36 -07003752 /*
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003753 * First disable irq(s) and then
Linus Torvalds1da177e2005-04-16 15:20:36 -07003754 * reenable interrupts on the nic, we have to do this before calling
3755 * nv_nic_irq because that may decide to do otherwise
3756 */
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003757
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003758 if (!using_multi_irqs(dev)) {
3759 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003760 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003761 else
Manfred Spraula7475902007-10-17 21:52:33 +02003762 disable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003763 mask = np->irqmask;
3764 } else {
3765 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003766 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003767 mask |= NVREG_IRQ_RX_ALL;
3768 }
3769 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003770 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003771 mask |= NVREG_IRQ_TX_ALL;
3772 }
3773 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003774 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003775 mask |= NVREG_IRQ_OTHER;
3776 }
3777 }
3778 np->nic_poll_irq = 0;
3779
Manfred Spraula7475902007-10-17 21:52:33 +02003780 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3781
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003782 if (np->recover_error) {
3783 np->recover_error = 0;
3784 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3785 if (netif_running(dev)) {
3786 netif_tx_lock_bh(dev);
3787 spin_lock(&np->lock);
3788 /* stop engines */
3789 nv_stop_rx(dev);
3790 nv_stop_tx(dev);
3791 nv_txrx_reset(dev);
3792 /* drain rx queue */
3793 nv_drain_rx(dev);
3794 nv_drain_tx(dev);
3795 /* reinit driver view of the rx queue */
3796 set_bufsize(dev);
3797 if (nv_init_ring(dev)) {
3798 if (!np->in_shutdown)
3799 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3800 }
3801 /* reinit nic view of the rx queue */
3802 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3803 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3804 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3805 base + NvRegRingSizes);
3806 pci_push(base);
3807 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3808 pci_push(base);
3809
3810 /* restart rx engine */
3811 nv_start_rx(dev);
3812 nv_start_tx(dev);
3813 spin_unlock(&np->lock);
3814 netif_tx_unlock_bh(dev);
3815 }
3816 }
3817
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003818
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003819 writel(mask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003820 pci_push(base);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003821
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003822 if (!using_multi_irqs(dev)) {
Ayaz Abdullafcc5f262007-03-23 05:49:37 -05003823 if (np->desc_ver == DESC_VER_3)
3824 nv_nic_irq_optimized(0, dev);
3825 else
3826 nv_nic_irq(0, dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003827 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003828 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003829 else
Manfred Spraula7475902007-10-17 21:52:33 +02003830 enable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003831 } else {
3832 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
David Howells7d12e782006-10-05 14:55:46 +01003833 nv_nic_irq_rx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003834 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003835 }
3836 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
David Howells7d12e782006-10-05 14:55:46 +01003837 nv_nic_irq_tx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003838 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003839 }
3840 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
David Howells7d12e782006-10-05 14:55:46 +01003841 nv_nic_irq_other(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003842 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05003843 }
3844 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003845}
3846
Michal Schmidt2918c352005-05-12 19:42:06 -04003847#ifdef CONFIG_NET_POLL_CONTROLLER
3848static void nv_poll_controller(struct net_device *dev)
3849{
3850 nv_do_nic_poll((unsigned long) dev);
3851}
3852#endif
3853
Ayaz Abdulla52da3572006-06-10 22:48:04 -04003854static void nv_do_stats_poll(unsigned long data)
3855{
3856 struct net_device *dev = (struct net_device *) data;
3857 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04003858
Ayaz Abdulla57fff692007-01-23 12:27:00 -05003859 nv_get_hw_stats(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04003860
3861 if (!np->in_shutdown)
3862 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3863}
3864
Linus Torvalds1da177e2005-04-16 15:20:36 -07003865static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3866{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003867 struct fe_priv *np = netdev_priv(dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04003868 strcpy(info->driver, DRV_NAME);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003869 strcpy(info->version, FORCEDETH_VERSION);
3870 strcpy(info->bus_info, pci_name(np->pci_dev));
3871}
3872
3873static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3874{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003875 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003876 wolinfo->supported = WAKE_MAGIC;
3877
3878 spin_lock_irq(&np->lock);
3879 if (np->wolenabled)
3880 wolinfo->wolopts = WAKE_MAGIC;
3881 spin_unlock_irq(&np->lock);
3882}
3883
3884static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3885{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003886 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003887 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04003888 u32 flags = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003889
Linus Torvalds1da177e2005-04-16 15:20:36 -07003890 if (wolinfo->wolopts == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003891 np->wolenabled = 0;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04003892 } else if (wolinfo->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003893 np->wolenabled = 1;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04003894 flags = NVREG_WAKEUPFLAGS_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003895 }
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04003896 if (netif_running(dev)) {
3897 spin_lock_irq(&np->lock);
3898 writel(flags, base + NvRegWakeUpFlags);
3899 spin_unlock_irq(&np->lock);
3900 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003901 return 0;
3902}
3903
3904static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3905{
3906 struct fe_priv *np = netdev_priv(dev);
3907 int adv;
3908
3909 spin_lock_irq(&np->lock);
3910 ecmd->port = PORT_MII;
3911 if (!netif_running(dev)) {
3912 /* We do not track link speed / duplex setting if the
3913 * interface is disabled. Force a link check */
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04003914 if (nv_update_linkspeed(dev)) {
3915 if (!netif_carrier_ok(dev))
3916 netif_carrier_on(dev);
3917 } else {
3918 if (netif_carrier_ok(dev))
3919 netif_carrier_off(dev);
3920 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003921 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04003922
3923 if (netif_carrier_ok(dev)) {
3924 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003925 case NVREG_LINKSPEED_10:
3926 ecmd->speed = SPEED_10;
3927 break;
3928 case NVREG_LINKSPEED_100:
3929 ecmd->speed = SPEED_100;
3930 break;
3931 case NVREG_LINKSPEED_1000:
3932 ecmd->speed = SPEED_1000;
3933 break;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04003934 }
3935 ecmd->duplex = DUPLEX_HALF;
3936 if (np->duplex)
3937 ecmd->duplex = DUPLEX_FULL;
3938 } else {
3939 ecmd->speed = -1;
3940 ecmd->duplex = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003941 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003942
3943 ecmd->autoneg = np->autoneg;
3944
3945 ecmd->advertising = ADVERTISED_MII;
3946 if (np->autoneg) {
3947 ecmd->advertising |= ADVERTISED_Autoneg;
3948 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04003949 if (adv & ADVERTISE_10HALF)
3950 ecmd->advertising |= ADVERTISED_10baseT_Half;
3951 if (adv & ADVERTISE_10FULL)
3952 ecmd->advertising |= ADVERTISED_10baseT_Full;
3953 if (adv & ADVERTISE_100HALF)
3954 ecmd->advertising |= ADVERTISED_100baseT_Half;
3955 if (adv & ADVERTISE_100FULL)
3956 ecmd->advertising |= ADVERTISED_100baseT_Full;
3957 if (np->gigabit == PHY_GIGABIT) {
3958 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3959 if (adv & ADVERTISE_1000FULL)
3960 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3961 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003962 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003963 ecmd->supported = (SUPPORTED_Autoneg |
3964 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3965 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3966 SUPPORTED_MII);
3967 if (np->gigabit == PHY_GIGABIT)
3968 ecmd->supported |= SUPPORTED_1000baseT_Full;
3969
3970 ecmd->phy_address = np->phyaddr;
3971 ecmd->transceiver = XCVR_EXTERNAL;
3972
3973 /* ignore maxtxpkt, maxrxpkt for now */
3974 spin_unlock_irq(&np->lock);
3975 return 0;
3976}
3977
3978static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3979{
3980 struct fe_priv *np = netdev_priv(dev);
3981
3982 if (ecmd->port != PORT_MII)
3983 return -EINVAL;
3984 if (ecmd->transceiver != XCVR_EXTERNAL)
3985 return -EINVAL;
3986 if (ecmd->phy_address != np->phyaddr) {
3987 /* TODO: support switching between multiple phys. Should be
3988 * trivial, but not enabled due to lack of test hardware. */
3989 return -EINVAL;
3990 }
3991 if (ecmd->autoneg == AUTONEG_ENABLE) {
3992 u32 mask;
3993
3994 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3995 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3996 if (np->gigabit == PHY_GIGABIT)
3997 mask |= ADVERTISED_1000baseT_Full;
3998
3999 if ((ecmd->advertising & mask) == 0)
4000 return -EINVAL;
4001
4002 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4003 /* Note: autonegotiation disable, speed 1000 intentionally
4004 * forbidden - noone should need that. */
4005
4006 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4007 return -EINVAL;
4008 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4009 return -EINVAL;
4010 } else {
4011 return -EINVAL;
4012 }
4013
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004014 netif_carrier_off(dev);
4015 if (netif_running(dev)) {
4016 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004017 netif_tx_lock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004018 spin_lock(&np->lock);
4019 /* stop engines */
4020 nv_stop_rx(dev);
4021 nv_stop_tx(dev);
4022 spin_unlock(&np->lock);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004023 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004024 }
4025
Linus Torvalds1da177e2005-04-16 15:20:36 -07004026 if (ecmd->autoneg == AUTONEG_ENABLE) {
4027 int adv, bmcr;
4028
4029 np->autoneg = 1;
4030
4031 /* advertise only what has been requested */
4032 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004033 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004034 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4035 adv |= ADVERTISE_10HALF;
4036 if (ecmd->advertising & ADVERTISED_10baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004037 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004038 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4039 adv |= ADVERTISE_100HALF;
4040 if (ecmd->advertising & ADVERTISED_100baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004041 adv |= ADVERTISE_100FULL;
4042 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4043 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4044 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4045 adv |= ADVERTISE_PAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004046 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4047
4048 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004049 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004050 adv &= ~ADVERTISE_1000FULL;
4051 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4052 adv |= ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004053 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004054 }
4055
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004056 if (netif_running(dev))
4057 printk(KERN_INFO "%s: link down.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004058 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004059 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4060 bmcr |= BMCR_ANENABLE;
4061 /* reset the phy in order for settings to stick,
4062 * and cause autoneg to start */
4063 if (phy_reset(dev, bmcr)) {
4064 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4065 return -EINVAL;
4066 }
4067 } else {
4068 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4069 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4070 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004071 } else {
4072 int adv, bmcr;
4073
4074 np->autoneg = 0;
4075
4076 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004077 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004078 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4079 adv |= ADVERTISE_10HALF;
4080 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004081 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004082 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4083 adv |= ADVERTISE_100HALF;
4084 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004085 adv |= ADVERTISE_100FULL;
4086 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4087 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4088 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4089 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4090 }
4091 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4092 adv |= ADVERTISE_PAUSE_ASYM;
4093 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4094 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004095 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4096 np->fixed_mode = adv;
4097
4098 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004099 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004100 adv &= ~ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004101 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004102 }
4103
4104 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004105 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4106 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004107 bmcr |= BMCR_FULLDPLX;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004108 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004109 bmcr |= BMCR_SPEED100;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004110 if (np->phy_oui == PHY_OUI_MARVELL) {
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004111 /* reset the phy in order for forced mode settings to stick */
4112 if (phy_reset(dev, bmcr)) {
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004113 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4114 return -EINVAL;
4115 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004116 } else {
4117 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4118 if (netif_running(dev)) {
4119 /* Wait a bit and then reconfigure the nic. */
4120 udelay(10);
4121 nv_linkchange(dev);
4122 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004123 }
4124 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004125
4126 if (netif_running(dev)) {
4127 nv_start_rx(dev);
4128 nv_start_tx(dev);
4129 nv_enable_irq(dev);
4130 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004131
4132 return 0;
4133}
4134
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004135#define FORCEDETH_REGS_VER 1
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004136
4137static int nv_get_regs_len(struct net_device *dev)
4138{
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004139 struct fe_priv *np = netdev_priv(dev);
4140 return np->register_size;
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004141}
4142
4143static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4144{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004145 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004146 u8 __iomem *base = get_hwbase(dev);
4147 u32 *rbuf = buf;
4148 int i;
4149
4150 regs->version = FORCEDETH_REGS_VER;
4151 spin_lock_irq(&np->lock);
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004152 for (i = 0;i <= np->register_size/sizeof(u32); i++)
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004153 rbuf[i] = readl(base + i*sizeof(u32));
4154 spin_unlock_irq(&np->lock);
4155}
4156
4157static int nv_nway_reset(struct net_device *dev)
4158{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004159 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004160 int ret;
4161
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004162 if (np->autoneg) {
4163 int bmcr;
4164
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004165 netif_carrier_off(dev);
4166 if (netif_running(dev)) {
4167 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004168 netif_tx_lock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004169 spin_lock(&np->lock);
4170 /* stop engines */
4171 nv_stop_rx(dev);
4172 nv_stop_tx(dev);
4173 spin_unlock(&np->lock);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004174 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004175 printk(KERN_INFO "%s: link down.\n", dev->name);
4176 }
4177
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004178 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004179 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4180 bmcr |= BMCR_ANENABLE;
4181 /* reset the phy in order for settings to stick*/
4182 if (phy_reset(dev, bmcr)) {
4183 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4184 return -EINVAL;
4185 }
4186 } else {
4187 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4188 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4189 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004190
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004191 if (netif_running(dev)) {
4192 nv_start_rx(dev);
4193 nv_start_tx(dev);
4194 nv_enable_irq(dev);
4195 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004196 ret = 0;
4197 } else {
4198 ret = -EINVAL;
4199 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004200
4201 return ret;
4202}
4203
Zachary Amsden0674d592006-06-04 02:51:38 -07004204static int nv_set_tso(struct net_device *dev, u32 value)
4205{
4206 struct fe_priv *np = netdev_priv(dev);
4207
4208 if ((np->driver_data & DEV_HAS_CHECKSUM))
4209 return ethtool_op_set_tso(dev, value);
4210 else
Ayaz Abdulla6a788142006-06-10 22:47:26 -04004211 return -EOPNOTSUPP;
Zachary Amsden0674d592006-06-04 02:51:38 -07004212}
Zachary Amsden0674d592006-06-04 02:51:38 -07004213
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004214static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4215{
4216 struct fe_priv *np = netdev_priv(dev);
4217
4218 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4219 ring->rx_mini_max_pending = 0;
4220 ring->rx_jumbo_max_pending = 0;
4221 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4222
4223 ring->rx_pending = np->rx_ring_size;
4224 ring->rx_mini_pending = 0;
4225 ring->rx_jumbo_pending = 0;
4226 ring->tx_pending = np->tx_ring_size;
4227}
4228
4229static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4230{
4231 struct fe_priv *np = netdev_priv(dev);
4232 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004233 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004234 dma_addr_t ring_addr;
4235
4236 if (ring->rx_pending < RX_RING_MIN ||
4237 ring->tx_pending < TX_RING_MIN ||
4238 ring->rx_mini_pending != 0 ||
4239 ring->rx_jumbo_pending != 0 ||
4240 (np->desc_ver == DESC_VER_1 &&
4241 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4242 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4243 (np->desc_ver != DESC_VER_1 &&
4244 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4245 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4246 return -EINVAL;
4247 }
4248
4249 /* allocate new rings */
4250 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4251 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4252 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4253 &ring_addr);
4254 } else {
4255 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4256 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4257 &ring_addr);
4258 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004259 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4260 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4261 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004262 /* fall back to old rings */
4263 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004264 if (rxtx_ring)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004265 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4266 rxtx_ring, ring_addr);
4267 } else {
4268 if (rxtx_ring)
4269 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4270 rxtx_ring, ring_addr);
4271 }
4272 if (rx_skbuff)
4273 kfree(rx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004274 if (tx_skbuff)
4275 kfree(tx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004276 goto exit;
4277 }
4278
4279 if (netif_running(dev)) {
4280 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004281 netif_tx_lock_bh(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004282 spin_lock(&np->lock);
4283 /* stop engines */
4284 nv_stop_rx(dev);
4285 nv_stop_tx(dev);
4286 nv_txrx_reset(dev);
4287 /* drain queues */
4288 nv_drain_rx(dev);
4289 nv_drain_tx(dev);
4290 /* delete queues */
4291 free_rings(dev);
4292 }
4293
4294 /* set new values */
4295 np->rx_ring_size = ring->rx_pending;
4296 np->tx_ring_size = ring->tx_pending;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004297 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4298 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4299 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4300 } else {
4301 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4302 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4303 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004304 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4305 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004306 np->ring_addr = ring_addr;
4307
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004308 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4309 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004310
4311 if (netif_running(dev)) {
4312 /* reinit driver view of the queues */
4313 set_bufsize(dev);
4314 if (nv_init_ring(dev)) {
4315 if (!np->in_shutdown)
4316 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4317 }
4318
4319 /* reinit nic view of the queues */
4320 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4321 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4322 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4323 base + NvRegRingSizes);
4324 pci_push(base);
4325 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4326 pci_push(base);
4327
4328 /* restart engines */
4329 nv_start_rx(dev);
4330 nv_start_tx(dev);
4331 spin_unlock(&np->lock);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004332 netif_tx_unlock_bh(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004333 nv_enable_irq(dev);
4334 }
4335 return 0;
4336exit:
4337 return -ENOMEM;
4338}
4339
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004340static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4341{
4342 struct fe_priv *np = netdev_priv(dev);
4343
4344 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4345 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4346 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4347}
4348
4349static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4350{
4351 struct fe_priv *np = netdev_priv(dev);
4352 int adv, bmcr;
4353
4354 if ((!np->autoneg && np->duplex == 0) ||
4355 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4356 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4357 dev->name);
4358 return -EINVAL;
4359 }
4360 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4361 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4362 return -EINVAL;
4363 }
4364
4365 netif_carrier_off(dev);
4366 if (netif_running(dev)) {
4367 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004368 netif_tx_lock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004369 spin_lock(&np->lock);
4370 /* stop engines */
4371 nv_stop_rx(dev);
4372 nv_stop_tx(dev);
4373 spin_unlock(&np->lock);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004374 netif_tx_unlock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004375 }
4376
4377 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4378 if (pause->rx_pause)
4379 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4380 if (pause->tx_pause)
4381 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4382
4383 if (np->autoneg && pause->autoneg) {
4384 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4385
4386 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4387 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4388 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4389 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4390 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4391 adv |= ADVERTISE_PAUSE_ASYM;
4392 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4393
4394 if (netif_running(dev))
4395 printk(KERN_INFO "%s: link down.\n", dev->name);
4396 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4397 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4398 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4399 } else {
4400 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4401 if (pause->rx_pause)
4402 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4403 if (pause->tx_pause)
4404 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4405
4406 if (!netif_running(dev))
4407 nv_update_linkspeed(dev);
4408 else
4409 nv_update_pause(dev, np->pause_flags);
4410 }
4411
4412 if (netif_running(dev)) {
4413 nv_start_rx(dev);
4414 nv_start_tx(dev);
4415 nv_enable_irq(dev);
4416 }
4417 return 0;
4418}
4419
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004420static u32 nv_get_rx_csum(struct net_device *dev)
4421{
4422 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004423 return (np->rx_csum) != 0;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004424}
4425
4426static int nv_set_rx_csum(struct net_device *dev, u32 data)
4427{
4428 struct fe_priv *np = netdev_priv(dev);
4429 u8 __iomem *base = get_hwbase(dev);
4430 int retcode = 0;
4431
4432 if (np->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004433 if (data) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004434 np->rx_csum = 1;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004435 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004436 } else {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004437 np->rx_csum = 0;
4438 /* vlan is dependent on rx checksum offload */
4439 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4440 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004441 }
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004442 if (netif_running(dev)) {
4443 spin_lock_irq(&np->lock);
4444 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4445 spin_unlock_irq(&np->lock);
4446 }
4447 } else {
4448 return -EINVAL;
4449 }
4450
4451 return retcode;
4452}
4453
4454static int nv_set_tx_csum(struct net_device *dev, u32 data)
4455{
4456 struct fe_priv *np = netdev_priv(dev);
4457
4458 if (np->driver_data & DEV_HAS_CHECKSUM)
4459 return ethtool_op_set_tx_hw_csum(dev, data);
4460 else
4461 return -EOPNOTSUPP;
4462}
4463
4464static int nv_set_sg(struct net_device *dev, u32 data)
4465{
4466 struct fe_priv *np = netdev_priv(dev);
4467
4468 if (np->driver_data & DEV_HAS_CHECKSUM)
4469 return ethtool_op_set_sg(dev, data);
4470 else
4471 return -EOPNOTSUPP;
4472}
4473
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004474static int nv_get_sset_count(struct net_device *dev, int sset)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004475{
4476 struct fe_priv *np = netdev_priv(dev);
4477
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004478 switch (sset) {
4479 case ETH_SS_TEST:
4480 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4481 return NV_TEST_COUNT_EXTENDED;
4482 else
4483 return NV_TEST_COUNT_BASE;
4484 case ETH_SS_STATS:
4485 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4486 return NV_DEV_STATISTICS_V1_COUNT;
4487 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4488 return NV_DEV_STATISTICS_V2_COUNT;
4489 else
4490 return 0;
4491 default:
4492 return -EOPNOTSUPP;
4493 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004494}
4495
4496static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4497{
4498 struct fe_priv *np = netdev_priv(dev);
4499
4500 /* update stats */
4501 nv_do_stats_poll((unsigned long)dev);
4502
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004503 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004504}
4505
4506static int nv_link_test(struct net_device *dev)
4507{
4508 struct fe_priv *np = netdev_priv(dev);
4509 int mii_status;
4510
4511 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4512 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4513
4514 /* check phy link status */
4515 if (!(mii_status & BMSR_LSTATUS))
4516 return 0;
4517 else
4518 return 1;
4519}
4520
4521static int nv_register_test(struct net_device *dev)
4522{
4523 u8 __iomem *base = get_hwbase(dev);
4524 int i = 0;
4525 u32 orig_read, new_read;
4526
4527 do {
4528 orig_read = readl(base + nv_registers_test[i].reg);
4529
4530 /* xor with mask to toggle bits */
4531 orig_read ^= nv_registers_test[i].mask;
4532
4533 writel(orig_read, base + nv_registers_test[i].reg);
4534
4535 new_read = readl(base + nv_registers_test[i].reg);
4536
4537 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4538 return 0;
4539
4540 /* restore original value */
4541 orig_read ^= nv_registers_test[i].mask;
4542 writel(orig_read, base + nv_registers_test[i].reg);
4543
4544 } while (nv_registers_test[++i].reg != 0);
4545
4546 return 1;
4547}
4548
4549static int nv_interrupt_test(struct net_device *dev)
4550{
4551 struct fe_priv *np = netdev_priv(dev);
4552 u8 __iomem *base = get_hwbase(dev);
4553 int ret = 1;
4554 int testcnt;
4555 u32 save_msi_flags, save_poll_interval = 0;
4556
4557 if (netif_running(dev)) {
4558 /* free current irq */
4559 nv_free_irq(dev);
4560 save_poll_interval = readl(base+NvRegPollingInterval);
4561 }
4562
4563 /* flag to test interrupt handler */
4564 np->intr_test = 0;
4565
4566 /* setup test irq */
4567 save_msi_flags = np->msi_flags;
4568 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4569 np->msi_flags |= 0x001; /* setup 1 vector */
4570 if (nv_request_irq(dev, 1))
4571 return 0;
4572
4573 /* setup timer interrupt */
4574 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4575 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4576
4577 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4578
4579 /* wait for at least one interrupt */
4580 msleep(100);
4581
4582 spin_lock_irq(&np->lock);
4583
4584 /* flag should be set within ISR */
4585 testcnt = np->intr_test;
4586 if (!testcnt)
4587 ret = 2;
4588
4589 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4590 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4591 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4592 else
4593 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4594
4595 spin_unlock_irq(&np->lock);
4596
4597 nv_free_irq(dev);
4598
4599 np->msi_flags = save_msi_flags;
4600
4601 if (netif_running(dev)) {
4602 writel(save_poll_interval, base + NvRegPollingInterval);
4603 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4604 /* restore original irq */
4605 if (nv_request_irq(dev, 0))
4606 return 0;
4607 }
4608
4609 return ret;
4610}
4611
4612static int nv_loopback_test(struct net_device *dev)
4613{
4614 struct fe_priv *np = netdev_priv(dev);
4615 u8 __iomem *base = get_hwbase(dev);
4616 struct sk_buff *tx_skb, *rx_skb;
4617 dma_addr_t test_dma_addr;
4618 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004619 u32 flags;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004620 int len, i, pkt_len;
4621 u8 *pkt_data;
4622 u32 filter_flags = 0;
4623 u32 misc1_flags = 0;
4624 int ret = 1;
4625
4626 if (netif_running(dev)) {
4627 nv_disable_irq(dev);
4628 filter_flags = readl(base + NvRegPacketFilterFlags);
4629 misc1_flags = readl(base + NvRegMisc1);
4630 } else {
4631 nv_txrx_reset(dev);
4632 }
4633
4634 /* reinit driver view of the rx queue */
4635 set_bufsize(dev);
4636 nv_init_ring(dev);
4637
4638 /* setup hardware for loopback */
4639 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4640 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4641
4642 /* reinit nic view of the rx queue */
4643 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4644 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4645 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4646 base + NvRegRingSizes);
4647 pci_push(base);
4648
4649 /* restart rx engine */
4650 nv_start_rx(dev);
4651 nv_start_tx(dev);
4652
4653 /* setup packet for tx */
4654 pkt_len = ETH_DATA_LEN;
4655 tx_skb = dev_alloc_skb(pkt_len);
Jesper Juhl46798c82006-09-25 16:39:24 -07004656 if (!tx_skb) {
4657 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4658 " of %s\n", dev->name);
4659 ret = 0;
4660 goto out;
4661 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03004662 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4663 skb_tailroom(tx_skb),
4664 PCI_DMA_FROMDEVICE);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004665 pkt_data = skb_put(tx_skb, pkt_len);
4666 for (i = 0; i < pkt_len; i++)
4667 pkt_data[i] = (u8)(i & 0xff);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004668
4669 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004670 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4671 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004672 } else {
Al Viro5bb7ea22007-12-09 16:06:41 +00004673 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4674 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004675 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004676 }
4677 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4678 pci_push(get_hwbase(dev));
4679
4680 msleep(500);
4681
4682 /* check for rx of the packet */
4683 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004684 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004685 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4686
4687 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004688 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004689 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4690 }
4691
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004692 if (flags & NV_RX_AVAIL) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004693 ret = 0;
4694 } else if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004695 if (flags & NV_RX_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004696 ret = 0;
4697 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004698 if (flags & NV_RX2_ERROR) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004699 ret = 0;
4700 }
4701 }
4702
4703 if (ret) {
4704 if (len != pkt_len) {
4705 ret = 0;
4706 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4707 dev->name, len, pkt_len);
4708 } else {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004709 rx_skb = np->rx_skb[0].skb;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004710 for (i = 0; i < pkt_len; i++) {
4711 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4712 ret = 0;
4713 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4714 dev->name, i);
4715 break;
4716 }
4717 }
4718 }
4719 } else {
4720 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4721 }
4722
4723 pci_unmap_page(np->pci_dev, test_dma_addr,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07004724 (skb_end_pointer(tx_skb) - tx_skb->data),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004725 PCI_DMA_TODEVICE);
4726 dev_kfree_skb_any(tx_skb);
Jesper Juhl46798c82006-09-25 16:39:24 -07004727 out:
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004728 /* stop engines */
4729 nv_stop_rx(dev);
4730 nv_stop_tx(dev);
4731 nv_txrx_reset(dev);
4732 /* drain rx queue */
4733 nv_drain_rx(dev);
4734 nv_drain_tx(dev);
4735
4736 if (netif_running(dev)) {
4737 writel(misc1_flags, base + NvRegMisc1);
4738 writel(filter_flags, base + NvRegPacketFilterFlags);
4739 nv_enable_irq(dev);
4740 }
4741
4742 return ret;
4743}
4744
4745static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4746{
4747 struct fe_priv *np = netdev_priv(dev);
4748 u8 __iomem *base = get_hwbase(dev);
4749 int result;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004750 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004751
4752 if (!nv_link_test(dev)) {
4753 test->flags |= ETH_TEST_FL_FAILED;
4754 buffer[0] = 1;
4755 }
4756
4757 if (test->flags & ETH_TEST_FL_OFFLINE) {
4758 if (netif_running(dev)) {
4759 netif_stop_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004760#ifdef CONFIG_FORCEDETH_NAPI
4761 napi_disable(&np->napi);
4762#endif
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004763 netif_tx_lock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004764 spin_lock_irq(&np->lock);
4765 nv_disable_hw_interrupts(dev, np->irqmask);
4766 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4767 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4768 } else {
4769 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4770 }
4771 /* stop engines */
4772 nv_stop_rx(dev);
4773 nv_stop_tx(dev);
4774 nv_txrx_reset(dev);
4775 /* drain rx queue */
4776 nv_drain_rx(dev);
4777 nv_drain_tx(dev);
4778 spin_unlock_irq(&np->lock);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004779 netif_tx_unlock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004780 }
4781
4782 if (!nv_register_test(dev)) {
4783 test->flags |= ETH_TEST_FL_FAILED;
4784 buffer[1] = 1;
4785 }
4786
4787 result = nv_interrupt_test(dev);
4788 if (result != 1) {
4789 test->flags |= ETH_TEST_FL_FAILED;
4790 buffer[2] = 1;
4791 }
4792 if (result == 0) {
4793 /* bail out */
4794 return;
4795 }
4796
4797 if (!nv_loopback_test(dev)) {
4798 test->flags |= ETH_TEST_FL_FAILED;
4799 buffer[3] = 1;
4800 }
4801
4802 if (netif_running(dev)) {
4803 /* reinit driver view of the rx queue */
4804 set_bufsize(dev);
4805 if (nv_init_ring(dev)) {
4806 if (!np->in_shutdown)
4807 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4808 }
4809 /* reinit nic view of the rx queue */
4810 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4811 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4812 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4813 base + NvRegRingSizes);
4814 pci_push(base);
4815 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4816 pci_push(base);
4817 /* restart rx engine */
4818 nv_start_rx(dev);
4819 nv_start_tx(dev);
4820 netif_start_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004821#ifdef CONFIG_FORCEDETH_NAPI
4822 napi_enable(&np->napi);
4823#endif
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004824 nv_enable_hw_interrupts(dev, np->irqmask);
4825 }
4826 }
4827}
4828
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004829static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4830{
4831 switch (stringset) {
4832 case ETH_SS_STATS:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004833 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004834 break;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004835 case ETH_SS_TEST:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004836 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004837 break;
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004838 }
4839}
4840
Jeff Garzik7282d492006-09-13 14:30:00 -04004841static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004842 .get_drvinfo = nv_get_drvinfo,
4843 .get_link = ethtool_op_get_link,
4844 .get_wol = nv_get_wol,
4845 .set_wol = nv_set_wol,
4846 .get_settings = nv_get_settings,
4847 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004848 .get_regs_len = nv_get_regs_len,
4849 .get_regs = nv_get_regs,
4850 .nway_reset = nv_nway_reset,
Ayaz Abdulla6a788142006-06-10 22:47:26 -04004851 .set_tso = nv_set_tso,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004852 .get_ringparam = nv_get_ringparam,
4853 .set_ringparam = nv_set_ringparam,
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004854 .get_pauseparam = nv_get_pauseparam,
4855 .set_pauseparam = nv_set_pauseparam,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004856 .get_rx_csum = nv_get_rx_csum,
4857 .set_rx_csum = nv_set_rx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004858 .set_tx_csum = nv_set_tx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004859 .set_sg = nv_set_sg,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004860 .get_strings = nv_get_strings,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004861 .get_ethtool_stats = nv_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004862 .get_sset_count = nv_get_sset_count,
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004863 .self_test = nv_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004864};
4865
Ayaz Abdullaee407b02006-02-04 13:13:17 -05004866static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4867{
4868 struct fe_priv *np = get_nvpriv(dev);
4869
4870 spin_lock_irq(&np->lock);
4871
4872 /* save vlan group */
4873 np->vlangrp = grp;
4874
4875 if (grp) {
4876 /* enable vlan on MAC */
4877 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4878 } else {
4879 /* disable vlan on MAC */
4880 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4881 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4882 }
4883
4884 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4885
4886 spin_unlock_irq(&np->lock);
Stephen Hemminger25805dc2007-06-01 09:44:01 -07004887}
Ayaz Abdullaee407b02006-02-04 13:13:17 -05004888
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05004889/* The mgmt unit and driver use a semaphore to access the phy during init */
4890static int nv_mgmt_acquire_sema(struct net_device *dev)
4891{
4892 u8 __iomem *base = get_hwbase(dev);
4893 int i;
4894 u32 tx_ctrl, mgmt_sema;
4895
4896 for (i = 0; i < 10; i++) {
4897 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4898 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4899 break;
4900 msleep(500);
4901 }
4902
4903 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4904 return 0;
4905
4906 for (i = 0; i < 2; i++) {
4907 tx_ctrl = readl(base + NvRegTransmitterControl);
4908 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4909 writel(tx_ctrl, base + NvRegTransmitterControl);
4910
4911 /* verify that semaphore was acquired */
4912 tx_ctrl = readl(base + NvRegTransmitterControl);
4913 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4914 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4915 return 1;
4916 else
4917 udelay(50);
4918 }
4919
4920 return 0;
4921}
4922
Linus Torvalds1da177e2005-04-16 15:20:36 -07004923static int nv_open(struct net_device *dev)
4924{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004925 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004926 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05004927 int ret = 1;
4928 int oom, i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004929
4930 dprintk(KERN_DEBUG "nv_open: begin\n");
4931
Ayaz Abdullaf1489652006-07-31 12:04:45 -04004932 /* erase previous misconfiguration */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004933 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4934 nv_mac_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004935 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4936 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05004937 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4938 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004939 writel(0, base + NvRegPacketFilterFlags);
4940
4941 writel(0, base + NvRegTransmitterControl);
4942 writel(0, base + NvRegReceiverControl);
4943
4944 writel(0, base + NvRegAdapterControl);
4945
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004946 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4947 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4948
Ayaz Abdullaf1489652006-07-31 12:04:45 -04004949 /* initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02004950 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004951 oom = nv_init_ring(dev);
4952
4953 writel(0, base + NvRegLinkSpeed);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04004954 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004955 nv_txrx_reset(dev);
4956 writel(0, base + NvRegUnknownSetupReg6);
4957
4958 np->in_shutdown = 0;
4959
Ayaz Abdullaf1489652006-07-31 12:04:45 -04004960 /* give hw rings */
Ayaz Abdulla0832b252006-02-04 13:13:26 -05004961 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004962 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07004963 base + NvRegRingSizes);
4964
Linus Torvalds1da177e2005-04-16 15:20:36 -07004965 writel(np->linkspeed, base + NvRegLinkSpeed);
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04004966 if (np->desc_ver == DESC_VER_1)
4967 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4968 else
4969 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04004970 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Ayaz Abdullaee407b02006-02-04 13:13:17 -05004971 writel(np->vlanctl_bits, base + NvRegVlanControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004972 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04004973 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004974 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4975 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4976 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4977
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05004978 writel(0, base + NvRegMIIMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004979 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05004980 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004981
Linus Torvalds1da177e2005-04-16 15:20:36 -07004982 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4983 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4984 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02004985 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004986
4987 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4988 get_random_bytes(&i, sizeof(i));
4989 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
Ayaz Abdulla9744e212006-07-06 16:45:58 -04004990 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4991 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05004992 if (poll_interval == -1) {
4993 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4994 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4995 else
4996 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4997 }
4998 else
4999 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005000 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5001 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5002 base + NvRegAdapterControl);
5003 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005004 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04005005 if (np->wolenabled)
5006 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005007
5008 i = readl(base + NvRegPowerState);
5009 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5010 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5011
5012 pci_push(base);
5013 udelay(10);
5014 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5015
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005016 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005017 pci_push(base);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005018 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005019 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5020 pci_push(base);
5021
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005022 if (nv_request_irq(dev, 0)) {
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005023 goto out_drain;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05005024 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005025
5026 /* ask for interrupts */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005027 nv_enable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005028
5029 spin_lock_irq(&np->lock);
5030 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5031 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005032 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5033 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005034 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5035 /* One manual link speed update: Interrupts are enabled, future link
5036 * speed changes cause interrupts and are handled by nv_link_irq().
5037 */
5038 {
5039 u32 miistat;
5040 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005041 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005042 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5043 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02005044 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5045 * to init hw */
5046 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005047 ret = nv_update_linkspeed(dev);
5048 nv_start_rx(dev);
5049 nv_start_tx(dev);
5050 netif_start_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005051#ifdef CONFIG_FORCEDETH_NAPI
5052 napi_enable(&np->napi);
5053#endif
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005054
Linus Torvalds1da177e2005-04-16 15:20:36 -07005055 if (ret) {
5056 netif_carrier_on(dev);
5057 } else {
Ed Swierkf7ab6972007-09-28 22:42:13 -07005058 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005059 netif_carrier_off(dev);
5060 }
5061 if (oom)
5062 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005063
5064 /* start statistics timer */
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005065 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005066 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
5067
Linus Torvalds1da177e2005-04-16 15:20:36 -07005068 spin_unlock_irq(&np->lock);
5069
5070 return 0;
5071out_drain:
5072 drain_ring(dev);
5073 return ret;
5074}
5075
5076static int nv_close(struct net_device *dev)
5077{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005078 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005079 u8 __iomem *base;
5080
5081 spin_lock_irq(&np->lock);
5082 np->in_shutdown = 1;
5083 spin_unlock_irq(&np->lock);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005084#ifdef CONFIG_FORCEDETH_NAPI
5085 napi_disable(&np->napi);
5086#endif
Manfred Spraula7475902007-10-17 21:52:33 +02005087 synchronize_irq(np->pci_dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005088
5089 del_timer_sync(&np->oom_kick);
5090 del_timer_sync(&np->nic_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005091 del_timer_sync(&np->stats_poll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005092
5093 netif_stop_queue(dev);
5094 spin_lock_irq(&np->lock);
5095 nv_stop_tx(dev);
5096 nv_stop_rx(dev);
5097 nv_txrx_reset(dev);
5098
5099 /* disable interrupts on the nic or we will lock up */
5100 base = get_hwbase(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005101 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005102 pci_push(base);
5103 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5104
5105 spin_unlock_irq(&np->lock);
5106
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005107 nv_free_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005108
5109 drain_ring(dev);
5110
Tim Mann2cc49a52007-06-14 13:16:38 -07005111 if (np->wolenabled) {
5112 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005113 nv_start_rx(dev);
Tim Mann2cc49a52007-06-14 13:16:38 -07005114 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005115
5116 /* FIXME: power down nic */
5117
5118 return 0;
5119}
5120
5121static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5122{
5123 struct net_device *dev;
5124 struct fe_priv *np;
5125 unsigned long addr;
5126 u8 __iomem *base;
5127 int err, i;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005128 u32 powerstate, txreg;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005129 u32 phystate_orig = 0, phystate;
5130 int phyinitialized = 0;
Joe Perches0795af52007-10-03 17:59:30 -07005131 DECLARE_MAC_BUF(mac);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005132 static int printed_version;
5133
5134 if (!printed_version++)
5135 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5136 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005137
5138 dev = alloc_etherdev(sizeof(struct fe_priv));
5139 err = -ENOMEM;
5140 if (!dev)
5141 goto out;
5142
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005143 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005144 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005145 np->pci_dev = pci_dev;
5146 spin_lock_init(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005147 SET_NETDEV_DEV(dev, &pci_dev->dev);
5148
5149 init_timer(&np->oom_kick);
5150 np->oom_kick.data = (unsigned long) dev;
5151 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5152 init_timer(&np->nic_poll);
5153 np->nic_poll.data = (unsigned long) dev;
5154 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005155 init_timer(&np->stats_poll);
5156 np->stats_poll.data = (unsigned long) dev;
5157 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005158
5159 err = pci_enable_device(pci_dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005160 if (err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005161 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005162
5163 pci_set_master(pci_dev);
5164
5165 err = pci_request_regions(pci_dev, DRV_NAME);
5166 if (err < 0)
5167 goto out_disable;
5168
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005169 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5170 np->register_size = NV_PCI_REGSZ_VER3;
5171 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005172 np->register_size = NV_PCI_REGSZ_VER2;
5173 else
5174 np->register_size = NV_PCI_REGSZ_VER1;
5175
Linus Torvalds1da177e2005-04-16 15:20:36 -07005176 err = -EINVAL;
5177 addr = 0;
5178 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5179 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5180 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5181 pci_resource_len(pci_dev, i),
5182 pci_resource_flags(pci_dev, i));
5183 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005184 pci_resource_len(pci_dev, i) >= np->register_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005185 addr = pci_resource_start(pci_dev, i);
5186 break;
5187 }
5188 }
5189 if (i == DEVICE_COUNT_RESOURCE) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005190 dev_printk(KERN_INFO, &pci_dev->dev,
5191 "Couldn't find register window\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005192 goto out_relreg;
5193 }
5194
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005195 /* copy of driver data */
5196 np->driver_data = id->driver_data;
5197
Linus Torvalds1da177e2005-04-16 15:20:36 -07005198 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02005199 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5200 /* packet format 3: supports 40-bit addressing */
5201 np->desc_ver = DESC_VER_3;
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005202 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005203 if (dma_64bit) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005204 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5205 dev_printk(KERN_INFO, &pci_dev->dev,
5206 "64-bit DMA failed, using 32-bit addressing\n");
5207 else
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005208 dev->features |= NETIF_F_HIGHDMA;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005209 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005210 dev_printk(KERN_INFO, &pci_dev->dev,
5211 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005212 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005213 }
Manfred Spraulee733622005-07-31 18:32:26 +02005214 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5215 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005216 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005217 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02005218 } else {
5219 /* original packet format */
5220 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005221 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02005222 }
Manfred Spraulee733622005-07-31 18:32:26 +02005223
5224 np->pkt_limit = NV_PKTLIMIT_1;
5225 if (id->driver_data & DEV_HAS_LARGEDESC)
5226 np->pkt_limit = NV_PKTLIMIT_2;
5227
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005228 if (id->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04005229 np->rx_csum = 1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005230 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005231 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
Ayaz Abdullafa454592006-01-05 22:45:45 -08005232 dev->features |= NETIF_F_TSO;
Ayaz Abdulla21828162007-01-23 12:27:21 -05005233 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005234
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005235 np->vlanctl_bits = 0;
5236 if (id->driver_data & DEV_HAS_VLAN) {
5237 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5238 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5239 dev->vlan_rx_register = nv_vlan_rx_register;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005240 }
5241
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05005242 np->msi_flags = 0;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005243 if ((id->driver_data & DEV_HAS_MSI) && msi) {
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05005244 np->msi_flags |= NV_MSI_CAPABLE;
5245 }
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005246 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05005247 np->msi_flags |= NV_MSI_X_CAPABLE;
5248 }
5249
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005250 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005251 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5252 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5253 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005254 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005255 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005256
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005257
Linus Torvalds1da177e2005-04-16 15:20:36 -07005258 err = -ENOMEM;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005259 np->base = ioremap(addr, np->register_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005260 if (!np->base)
5261 goto out_relreg;
5262 dev->base_addr = (unsigned long)np->base;
Manfred Spraulee733622005-07-31 18:32:26 +02005263
Linus Torvalds1da177e2005-04-16 15:20:36 -07005264 dev->irq = pci_dev->irq;
Manfred Spraulee733622005-07-31 18:32:26 +02005265
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005266 np->rx_ring_size = RX_RING_DEFAULT;
5267 np->tx_ring_size = TX_RING_DEFAULT;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005268
Manfred Spraulee733622005-07-31 18:32:26 +02005269 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
5270 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005271 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005272 &np->ring_addr);
5273 if (!np->rx_ring.orig)
5274 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005275 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005276 } else {
5277 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005278 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005279 &np->ring_addr);
5280 if (!np->rx_ring.ex)
5281 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005282 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005283 }
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07005284 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5285 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005286 if (!np->rx_skb || !np->tx_skb)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005287 goto out_freering;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005288
5289 dev->open = nv_open;
5290 dev->stop = nv_close;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05005291 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5292 dev->hard_start_xmit = nv_start_xmit;
5293 else
5294 dev->hard_start_xmit = nv_start_xmit_optimized;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005295 dev->get_stats = nv_get_stats;
5296 dev->change_mtu = nv_change_mtu;
Manfred Spraul72b31782005-07-31 18:33:34 +02005297 dev->set_mac_address = nv_set_mac_address;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005298 dev->set_multicast_list = nv_set_multicast;
Michal Schmidt2918c352005-05-12 19:42:06 -04005299#ifdef CONFIG_NET_POLL_CONTROLLER
5300 dev->poll_controller = nv_poll_controller;
5301#endif
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005302#ifdef CONFIG_FORCEDETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005303 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005304#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07005305 SET_ETHTOOL_OPS(dev, &ops);
5306 dev->tx_timeout = nv_tx_timeout;
5307 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5308
5309 pci_set_drvdata(pci_dev, dev);
5310
5311 /* read the mac address */
5312 base = get_hwbase(dev);
5313 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5314 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5315
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005316 /* check the workaround bit for correct mac address order */
5317 txreg = readl(base + NvRegTransmitPoll);
Ayaz Abdullaef756b32007-07-26 23:46:00 -04005318 if ((txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) ||
5319 (id->driver_data & DEV_HAS_CORRECT_MACADDR)) {
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005320 /* mac address is already in correct order */
5321 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5322 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5323 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5324 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5325 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5326 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5327 } else {
5328 /* need to reverse mac address to correct order */
5329 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5330 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5331 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5332 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5333 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5334 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005335 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5336 }
John W. Linvillec704b852005-09-12 10:48:56 -04005337 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005338
John W. Linvillec704b852005-09-12 10:48:56 -04005339 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005340 /*
5341 * Bad mac address. At least one bios sets the mac address
5342 * to 01:23:45:67:89:ab
5343 */
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005344 dev_printk(KERN_ERR, &pci_dev->dev,
5345 "Invalid Mac address detected: %s\n",
5346 print_mac(mac, dev->dev_addr));
5347 dev_printk(KERN_ERR, &pci_dev->dev,
5348 "Please complain to your hardware vendor. Switching to a random MAC.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005349 dev->dev_addr[0] = 0x00;
5350 dev->dev_addr[1] = 0x00;
5351 dev->dev_addr[2] = 0x6c;
5352 get_random_bytes(&dev->dev_addr[3], 3);
5353 }
5354
Joe Perches0795af52007-10-03 17:59:30 -07005355 dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5356 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005357
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005358 /* set mac address */
5359 nv_copy_mac_to_hw(dev);
5360
Linus Torvalds1da177e2005-04-16 15:20:36 -07005361 /* disable WOL */
5362 writel(0, base + NvRegWakeUpFlags);
5363 np->wolenabled = 0;
5364
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005365 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005366
5367 /* take phy and nic out of low power mode */
5368 powerstate = readl(base + NvRegPowerState2);
5369 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5370 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5371 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
Auke Kok44c10132007-06-08 15:46:36 -07005372 pci_dev->revision >= 0xA3)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005373 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5374 writel(powerstate, base + NvRegPowerState2);
5375 }
5376
Linus Torvalds1da177e2005-04-16 15:20:36 -07005377 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005378 np->tx_flags = NV_TX_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005379 } else {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005380 np->tx_flags = NV_TX2_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005381 }
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05005382 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005383 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05005384 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5385 np->msi_flags |= 0x0003;
5386 } else {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005387 np->irqmask = NVREG_IRQMASK_CPU;
Ayaz Abdullad33a73c2006-02-04 13:13:31 -05005388 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5389 np->msi_flags |= 0x0001;
5390 }
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005391
Linus Torvalds1da177e2005-04-16 15:20:36 -07005392 if (id->driver_data & DEV_NEED_TIMERIRQ)
5393 np->irqmask |= NVREG_IRQ_TIMER;
5394 if (id->driver_data & DEV_NEED_LINKTIMER) {
5395 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5396 np->need_linktimer = 1;
5397 np->link_timeout = jiffies + LINK_TIMEOUT;
5398 } else {
5399 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5400 np->need_linktimer = 0;
5401 }
5402
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005403 /* Limit the number of tx's outstanding for hw bug */
5404 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5405 np->tx_limit = 1;
5406 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5407 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5408 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5409 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5410 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5411 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5412 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5413 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5414 pci_dev->revision >= 0xA2)
5415 np->tx_limit = 0;
5416 }
5417
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005418 /* clear phy state and temporarily halt phy interrupts */
5419 writel(0, base + NvRegMIIMask);
5420 phystate = readl(base + NvRegAdapterControl);
5421 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5422 phystate_orig = 1;
5423 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5424 writel(phystate, base + NvRegAdapterControl);
5425 }
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005426 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005427
5428 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005429 /* management unit running on the mac? */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005430 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5431 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5432 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
Ayaz Abdulla9e555932007-11-21 15:02:58 -08005433 if (nv_mgmt_acquire_sema(dev)) {
5434 /* management unit setup the phy already? */
5435 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5436 NVREG_XMITCTL_SYNC_PHY_INIT) {
5437 /* phy is inited by mgmt unit */
5438 phyinitialized = 1;
5439 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5440 } else {
5441 /* we need to init the phy */
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005442 }
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005443 }
5444 }
5445 }
5446
Linus Torvalds1da177e2005-04-16 15:20:36 -07005447 /* find a suitable phy */
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005448 for (i = 1; i <= 32; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005449 int id1, id2;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005450 int phyaddr = i & 0x1F;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005451
5452 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005453 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005454 spin_unlock_irq(&np->lock);
5455 if (id1 < 0 || id1 == 0xffff)
5456 continue;
5457 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005458 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005459 spin_unlock_irq(&np->lock);
5460 if (id2 < 0 || id2 == 0xffff)
5461 continue;
5462
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04005463 np->phy_model = id2 & PHYID2_MODEL_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005464 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5465 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5466 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005467 pci_name(pci_dev), id1, id2, phyaddr);
5468 np->phyaddr = phyaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005469 np->phy_oui = id1 | id2;
5470 break;
5471 }
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005472 if (i == 33) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005473 dev_printk(KERN_INFO, &pci_dev->dev,
5474 "open: Could not find a valid PHY.\n");
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005475 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005476 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005477
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005478 if (!phyinitialized) {
5479 /* reset it */
5480 phy_init(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005481 } else {
5482 /* see if it is a gigabit phy */
5483 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5484 if (mii_status & PHY_GIGABIT) {
5485 np->gigabit = PHY_GIGABIT;
5486 }
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005487 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005488
5489 /* set default link speed settings */
5490 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5491 np->duplex = 0;
5492 np->autoneg = 1;
5493
5494 err = register_netdev(dev);
5495 if (err) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005496 dev_printk(KERN_INFO, &pci_dev->dev,
5497 "unable to register netdev: %d\n", err);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005498 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005499 }
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005500
5501 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5502 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5503 dev->name,
5504 np->phy_oui,
5505 np->phyaddr,
5506 dev->dev_addr[0],
5507 dev->dev_addr[1],
5508 dev->dev_addr[2],
5509 dev->dev_addr[3],
5510 dev->dev_addr[4],
5511 dev->dev_addr[5]);
5512
5513 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5514 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5515 dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5516 "csum " : "",
5517 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5518 "vlan " : "",
5519 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5520 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5521 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5522 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5523 np->need_linktimer ? "lnktim " : "",
5524 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5525 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5526 np->desc_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005527
5528 return 0;
5529
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005530out_error:
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005531 if (phystate_orig)
5532 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005533 pci_set_drvdata(pci_dev, NULL);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005534out_freering:
5535 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005536out_unmap:
5537 iounmap(get_hwbase(dev));
5538out_relreg:
5539 pci_release_regions(pci_dev);
5540out_disable:
5541 pci_disable_device(pci_dev);
5542out_free:
5543 free_netdev(dev);
5544out:
5545 return err;
5546}
5547
5548static void __devexit nv_remove(struct pci_dev *pci_dev)
5549{
5550 struct net_device *dev = pci_get_drvdata(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005551 struct fe_priv *np = netdev_priv(dev);
5552 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005553
5554 unregister_netdev(dev);
5555
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005556 /* special op: write back the misordered MAC address - otherwise
5557 * the next nv_probe would see a wrong address.
5558 */
5559 writel(np->orig_mac[0], base + NvRegMacAddrA);
5560 writel(np->orig_mac[1], base + NvRegMacAddrB);
Björn Steinbrink2e3884b2008-01-07 23:22:53 -08005561 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5562 base + NvRegTransmitPoll);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005563
Linus Torvalds1da177e2005-04-16 15:20:36 -07005564 /* free all structures */
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005565 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005566 iounmap(get_hwbase(dev));
5567 pci_release_regions(pci_dev);
5568 pci_disable_device(pci_dev);
5569 free_netdev(dev);
5570 pci_set_drvdata(pci_dev, NULL);
5571}
5572
Francois Romieua1893172006-10-10 14:33:27 -07005573#ifdef CONFIG_PM
5574static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5575{
5576 struct net_device *dev = pci_get_drvdata(pdev);
5577 struct fe_priv *np = netdev_priv(dev);
5578
5579 if (!netif_running(dev))
5580 goto out;
5581
5582 netif_device_detach(dev);
5583
5584 // Gross.
5585 nv_close(dev);
5586
5587 pci_save_state(pdev);
5588 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5589 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5590out:
5591 return 0;
5592}
5593
5594static int nv_resume(struct pci_dev *pdev)
5595{
5596 struct net_device *dev = pci_get_drvdata(pdev);
5597 int rc = 0;
5598
5599 if (!netif_running(dev))
5600 goto out;
5601
5602 netif_device_attach(dev);
5603
5604 pci_set_power_state(pdev, PCI_D0);
5605 pci_restore_state(pdev);
5606 pci_enable_wake(pdev, PCI_D0, 0);
5607
5608 rc = nv_open(dev);
5609out:
5610 return rc;
5611}
5612#else
5613#define nv_suspend NULL
5614#define nv_resume NULL
5615#endif /* CONFIG_PM */
5616
Linus Torvalds1da177e2005-04-16 15:20:36 -07005617static struct pci_device_id pci_tbl[] = {
5618 { /* nForce Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005619 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005620 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005621 },
5622 { /* nForce2 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005623 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005624 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005625 },
5626 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005627 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005628 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005629 },
5630 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005631 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005632 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005633 },
5634 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005635 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005636 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005637 },
5638 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005639 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005640 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005641 },
5642 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005643 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005644 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005645 },
5646 { /* CK804 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005647 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005648 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005649 },
5650 { /* CK804 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005651 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005652 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005653 },
5654 { /* MCP04 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005655 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005656 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005657 },
5658 { /* MCP04 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005659 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005660 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005661 },
5662 { /* MCP51 Ethernet Controller */
5663 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005664 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005665 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02005666 { /* MCP51 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005667 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005668 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02005669 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005670 { /* MCP55 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005671 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005672 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005673 },
5674 { /* MCP55 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005675 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005676 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005677 },
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005678 { /* MCP61 Ethernet Controller */
5679 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005680 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005681 },
5682 { /* MCP61 Ethernet Controller */
5683 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005684 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005685 },
5686 { /* MCP61 Ethernet Controller */
5687 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005688 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005689 },
5690 { /* MCP61 Ethernet Controller */
5691 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005692 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005693 },
5694 { /* MCP65 Ethernet Controller */
5695 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005696 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005697 },
5698 { /* MCP65 Ethernet Controller */
5699 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005700 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005701 },
5702 { /* MCP65 Ethernet Controller */
5703 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005704 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005705 },
5706 { /* MCP65 Ethernet Controller */
5707 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005708 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005709 },
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005710 { /* MCP67 Ethernet Controller */
5711 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005712 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005713 },
5714 { /* MCP67 Ethernet Controller */
5715 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005716 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005717 },
5718 { /* MCP67 Ethernet Controller */
5719 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005720 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005721 },
5722 { /* MCP67 Ethernet Controller */
5723 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005724 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08005725 },
Ayaz Abdulla13986612007-07-22 20:43:26 -04005726 { /* MCP73 Ethernet Controller */
5727 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005728 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04005729 },
5730 { /* MCP73 Ethernet Controller */
5731 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005732 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04005733 },
5734 { /* MCP73 Ethernet Controller */
5735 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005736 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04005737 },
5738 { /* MCP73 Ethernet Controller */
5739 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005740 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04005741 },
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005742 { /* MCP77 Ethernet Controller */
5743 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005744 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005745 },
5746 { /* MCP77 Ethernet Controller */
5747 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005748 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005749 },
5750 { /* MCP77 Ethernet Controller */
5751 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005752 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005753 },
5754 { /* MCP77 Ethernet Controller */
5755 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005756 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04005757 },
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005758 { /* MCP79 Ethernet Controller */
5759 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005760 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005761 },
5762 { /* MCP79 Ethernet Controller */
5763 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005764 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005765 },
5766 { /* MCP79 Ethernet Controller */
5767 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005768 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005769 },
5770 { /* MCP79 Ethernet Controller */
5771 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005772 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05005773 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07005774 {0,},
5775};
5776
5777static struct pci_driver driver = {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005778 .name = DRV_NAME,
5779 .id_table = pci_tbl,
5780 .probe = nv_probe,
5781 .remove = __devexit_p(nv_remove),
5782 .suspend = nv_suspend,
5783 .resume = nv_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005784};
5785
Linus Torvalds1da177e2005-04-16 15:20:36 -07005786static int __init init_nic(void)
5787{
Jeff Garzik29917622006-08-19 17:48:59 -04005788 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005789}
5790
5791static void __exit exit_nic(void)
5792{
5793 pci_unregister_driver(&driver);
5794}
5795
5796module_param(max_interrupt_work, int, 0);
5797MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005798module_param(optimization_mode, int, 0);
5799MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5800module_param(poll_interval, int, 0);
5801MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005802module_param(msi, int, 0);
5803MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5804module_param(msix, int, 0);
5805MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5806module_param(dma_64bit, int, 0);
5807MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005808
5809MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5810MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5811MODULE_LICENSE("GPL");
5812
5813MODULE_DEVICE_TABLE(pci, pci_tbl);
5814
5815module_init(init_nic);
5816module_exit(exit_nic);