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gerrit-public.fairphone.software / kernel / msm / b4482a4b2e2ff5ed96d8d16d72e83e75064062c5 / . / include / asm-powerpc / mpc52xx.h
blob: 24751df791ac603519dc00d77175f99587a37948 [file] [log] [blame]
Nicolas DET0f6c95d2006-11-08 17:14:43 +0100[diff] [blame]1/*
2 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
3 * May need to be cleaned as the port goes on ...
4 *
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003 MontaVista, Software, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#ifndef __ASM_POWERPC_MPC52xx_H__
14#define __ASM_POWERPC_MPC52xx_H__
15
16#ifndef __ASSEMBLY__
17#include <asm/types.h>
18#include <asm/prom.h>
19#endif /* __ASSEMBLY__ */
20
21
22/* ======================================================================== */
Nicolas DET0f6c95d2006-11-08 17:14:43 +0100[diff] [blame]23/* Structures mapping of some unit register set */
24/* ======================================================================== */
25
26#ifndef __ASSEMBLY__
27
Nicolas DET0f6c95d2006-11-08 17:14:43 +0100[diff] [blame]28/* Memory Mapping Control */
29struct mpc52xx_mmap_ctl {
30 u32 mbar; /* MMAP_CTRL + 0x00 */
31
32 u32 cs0_start; /* MMAP_CTRL + 0x04 */
33 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
34 u32 cs1_start; /* MMAP_CTRL + 0x0c */
35 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
36 u32 cs2_start; /* MMAP_CTRL + 0x14 */
37 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
38 u32 cs3_start; /* MMAP_CTRL + 0x1c */
39 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
40 u32 cs4_start; /* MMAP_CTRL + 0x24 */
41 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
42 u32 cs5_start; /* MMAP_CTRL + 0x2c */
43 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
44
45 u32 sdram0; /* MMAP_CTRL + 0x34 */
46 u32 sdram1; /* MMAP_CTRL + 0X38 */
47
48 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
49
50 u32 boot_start; /* MMAP_CTRL + 0x4c */
51 u32 boot_stop; /* MMAP_CTRL + 0x50 */
52
53 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
54
55 u32 cs6_start; /* MMAP_CTRL + 0x58 */
56 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
57 u32 cs7_start; /* MMAP_CTRL + 0x60 */
58 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
59};
60
61/* SDRAM control */
62struct mpc52xx_sdram {
63 u32 mode; /* SDRAM + 0x00 */
64 u32 ctrl; /* SDRAM + 0x04 */
65 u32 config1; /* SDRAM + 0x08 */
66 u32 config2; /* SDRAM + 0x0c */
67};
68
69/* SDMA */
70struct mpc52xx_sdma {
71 u32 taskBar; /* SDMA + 0x00 */
72 u32 currentPointer; /* SDMA + 0x04 */
73 u32 endPointer; /* SDMA + 0x08 */
74 u32 variablePointer; /* SDMA + 0x0c */
75
76 u8 IntVect1; /* SDMA + 0x10 */
77 u8 IntVect2; /* SDMA + 0x11 */
78 u16 PtdCntrl; /* SDMA + 0x12 */
79
80 u32 IntPend; /* SDMA + 0x14 */
81 u32 IntMask; /* SDMA + 0x18 */
82
83 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
84
85 u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
86
87 u32 cReqSelect; /* SDMA + 0x5c */
88 u32 task_size0; /* SDMA + 0x60 */
89 u32 task_size1; /* SDMA + 0x64 */
90 u32 MDEDebug; /* SDMA + 0x68 */
91 u32 ADSDebug; /* SDMA + 0x6c */
92 u32 Value1; /* SDMA + 0x70 */
93 u32 Value2; /* SDMA + 0x74 */
94 u32 Control; /* SDMA + 0x78 */
95 u32 Status; /* SDMA + 0x7c */
96 u32 PTDDebug; /* SDMA + 0x80 */
97};
98
99/* GPT */
100struct mpc52xx_gpt {
101 u32 mode; /* GPTx + 0x00 */
102 u32 count; /* GPTx + 0x04 */
103 u32 pwm; /* GPTx + 0x08 */
104 u32 status; /* GPTx + 0X0c */
105};
106
107/* GPIO */
108struct mpc52xx_gpio {
109 u32 port_config; /* GPIO + 0x00 */
110 u32 simple_gpioe; /* GPIO + 0x04 */
111 u32 simple_ode; /* GPIO + 0x08 */
112 u32 simple_ddr; /* GPIO + 0x0c */
113 u32 simple_dvo; /* GPIO + 0x10 */
114 u32 simple_ival; /* GPIO + 0x14 */
115 u8 outo_gpioe; /* GPIO + 0x18 */
116 u8 reserved1[3]; /* GPIO + 0x19 */
117 u8 outo_dvo; /* GPIO + 0x1c */
118 u8 reserved2[3]; /* GPIO + 0x1d */
119 u8 sint_gpioe; /* GPIO + 0x20 */
120 u8 reserved3[3]; /* GPIO + 0x21 */
121 u8 sint_ode; /* GPIO + 0x24 */
122 u8 reserved4[3]; /* GPIO + 0x25 */
123 u8 sint_ddr; /* GPIO + 0x28 */
124 u8 reserved5[3]; /* GPIO + 0x29 */
125 u8 sint_dvo; /* GPIO + 0x2c */
126 u8 reserved6[3]; /* GPIO + 0x2d */
127 u8 sint_inten; /* GPIO + 0x30 */
128 u8 reserved7[3]; /* GPIO + 0x31 */
129 u16 sint_itype; /* GPIO + 0x34 */
130 u16 reserved8; /* GPIO + 0x36 */
131 u8 gpio_control; /* GPIO + 0x38 */
132 u8 reserved9[3]; /* GPIO + 0x39 */
133 u8 sint_istat; /* GPIO + 0x3c */
134 u8 sint_ival; /* GPIO + 0x3d */
135 u8 bus_errs; /* GPIO + 0x3e */
136 u8 reserved10; /* GPIO + 0x3f */
137};
138
139#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
140#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
141#define MPC52xx_GPIO_PCI_DIS (1<<15)
142
143/* GPIO with WakeUp*/
144struct mpc52xx_gpio_wkup {
145 u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
146 u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
147 u8 wkup_ode; /* GPIO_WKUP + 0x04 */
148 u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
149 u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
150 u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
151 u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
152 u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
153 u8 wkup_inten; /* GPIO_WKUP + 0x10 */
154 u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
155 u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
156 u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
157 u16 wkup_itype; /* GPIO_WKUP + 0x18 */
158 u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
159 u8 wkup_maste; /* GPIO_WKUP + 0x1C */
160 u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
161 u8 wkup_ival; /* GPIO_WKUP + 0x20 */
162 u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
163 u8 wkup_istat; /* GPIO_WKUP + 0x24 */
164 u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
165};
166
167/* XLB Bus control */
168struct mpc52xx_xlb {
169 u8 reserved[0x40];
170 u32 config; /* XLB + 0x40 */
171 u32 version; /* XLB + 0x44 */
172 u32 status; /* XLB + 0x48 */
173 u32 int_enable; /* XLB + 0x4c */
174 u32 addr_capture; /* XLB + 0x50 */
175 u32 bus_sig_capture; /* XLB + 0x54 */
176 u32 addr_timeout; /* XLB + 0x58 */
177 u32 data_timeout; /* XLB + 0x5c */
178 u32 bus_act_timeout; /* XLB + 0x60 */
179 u32 master_pri_enable; /* XLB + 0x64 */
180 u32 master_priority; /* XLB + 0x68 */
181 u32 base_address; /* XLB + 0x6c */
182 u32 snoop_window; /* XLB + 0x70 */
183};
184
185#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
186#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
187
188/* Clock Distribution control */
189struct mpc52xx_cdm {
190 u32 jtag_id; /* CDM + 0x00 reg0 read only */
191 u32 rstcfg; /* CDM + 0x04 reg1 read only */
192 u32 breadcrumb; /* CDM + 0x08 reg2 */
193
194 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
195 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
196 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
197 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
198
199 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
200 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
201 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
202
203 u32 clk_enables; /* CDM + 0x14 reg5 */
204
205 u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
206 u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
207
208 u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
209 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
210 u8 reserved1; /* CDM + 0x1e reg7 byte2 */
211 u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
212
213 u8 soft_reset; /* CDM + 0x20 u8 byte0 */
214 u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
215 u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
216
217 u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
218 u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
219 u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
220 u8 reserved3; /* CDM + 0x27 reg9 byte3 */
221
222 u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
223 u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
224
225 u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
226 u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
227
228 u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
229 u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
230
231 u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
232 u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
233};
234
235#endif /* __ASSEMBLY__ */
236
237
238/* ========================================================================= */
239/* Prototypes for MPC52xx sysdev */
240/* ========================================================================= */
241
242#ifndef __ASSEMBLY__
243
Grant Likely60651702006-11-27 14:16:27 -0700[diff] [blame]244extern void __iomem * mpc52xx_find_and_map(const char *);
245extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
Grant Likely4de3b992007-10-09 14:45:28 -0600[diff] [blame]246extern void mpc5200_setup_xlb_arbiter(void);
Sylvain Munaut5c334ee2007-01-02 23:29:53 +0100[diff] [blame]247extern void mpc52xx_declare_of_platform_devices(void);
Grant Likely60651702006-11-27 14:16:27 -0700[diff] [blame]248
Nicolas DET0f6c95d2006-11-08 17:14:43 +0100[diff] [blame]249extern void mpc52xx_init_irq(void);
250extern unsigned int mpc52xx_get_irq(void);
251
Grant Likelyf42963f2006-12-12 15:13:19 -0700[diff] [blame]252extern int __init mpc52xx_add_bridge(struct device_node *node);
253
Nicolas DET0f6c95d2006-11-08 17:14:43 +0100[diff] [blame]254#endif /* __ASSEMBLY__ */
255
Domen Puncer2e1ee1f2007-05-07 01:38:52 +1000[diff] [blame]256#ifdef CONFIG_PM
257struct mpc52xx_suspend {
258 void (*board_suspend_prepare)(void __iomem *mbar);
259 void (*board_resume_finish)(void __iomem *mbar);
260};
261
262extern struct mpc52xx_suspend mpc52xx_suspend;
263extern int __init mpc52xx_pm_init(void);
264extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
Domen Punceree983072007-07-18 06:32:31 +1000[diff] [blame]265
266#ifdef CONFIG_PPC_LITE5200
267extern int __init lite5200_pm_init(void);
268
269/* lite5200 calls mpc5200 suspend functions, so here they are */
270extern int mpc52xx_pm_prepare(suspend_state_t);
271extern int mpc52xx_pm_enter(suspend_state_t);
272extern int mpc52xx_pm_finish(suspend_state_t);
273extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
274#endif
Domen Puncer2e1ee1f2007-05-07 01:38:52 +1000[diff] [blame]275#endif /* CONFIG_PM */
276
Nicolas DET0f6c95d2006-11-08 17:14:43 +0100[diff] [blame]277#endif /* __ASM_POWERPC_MPC52xx_H__ */
278