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gerrit-public.fairphone.software / kernel / msm / b65a0e0c84cf489bfa00d6aa6c48abc5a237100f / . / drivers / net / e1000e / e1000.h
blob: e610e1369053154abf27e8665d60ca1392a2d0ff [file] [log] [blame]
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
Bruce Allan0d6057e2011-01-04 01:16:44 +0000[diff] [blame]4 Copyright(c) 1999 - 2011 Intel Corporation.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
34#include <linux/types.h>
35#include <linux/timer.h>
36#include <linux/workqueue.h>
37#include <linux/io.h>
38#include <linux/netdevice.h>
Bruce Alland8014db2009-11-20 23:24:48 +0000[diff] [blame]39#include <linux/pci.h>
Bruce Allan6f461f62010-04-27 03:33:04 +0000[diff] [blame]40#include <linux/pci-aspm.h>
Bruce Allanfe46f582011-01-06 14:29:51 +0000[diff] [blame]41#include <linux/crc32.h>
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]42
43#include "hw.h"
44
45struct e1000_info;
46
Jeff Kirsher44defeb2008-08-04 17:20:41 -0700[diff] [blame]47#define e_dbg(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +0000[diff] [blame]48 netdev_dbg(hw->adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -0700[diff] [blame]49#define e_err(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +0000[diff] [blame]50 netdev_err(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -0700[diff] [blame]51#define e_info(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +0000[diff] [blame]52 netdev_info(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -0700[diff] [blame]53#define e_warn(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +0000[diff] [blame]54 netdev_warn(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -0700[diff] [blame]55#define e_notice(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +0000[diff] [blame]56 netdev_notice(adapter->netdev, format, ## arg)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]57
58
Martin Olsson98a17082009-04-22 18:21:29 +0200[diff] [blame]59/* Interrupt modes, as used by the IntMode parameter */
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]60#define E1000E_INT_MODE_LEGACY 0
61#define E1000E_INT_MODE_MSI 1
62#define E1000E_INT_MODE_MSIX 2
63
Bruce Allanad680762008-03-28 09:15:03 -0700[diff] [blame]64/* Tx/Rx descriptor defines */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]65#define E1000_DEFAULT_TXD 256
66#define E1000_MAX_TXD 4096
Auke Kok7b1be192008-04-23 11:09:19 -0700[diff] [blame]67#define E1000_MIN_TXD 64
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]68
69#define E1000_DEFAULT_RXD 256
70#define E1000_MAX_RXD 4096
Auke Kok7b1be192008-04-23 11:09:19 -0700[diff] [blame]71#define E1000_MIN_RXD 64
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]72
Auke Kokde5b3072008-04-23 11:09:08 -0700[diff] [blame]73#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
74#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
75
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]76/* Early Receive defines */
77#define E1000_ERT_2048 0x100
78
79#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
80
81/* How many Tx Descriptors do we need to call netif_wake_queue ? */
82/* How many Rx Buffers do we bundle into one write to the hardware ? */
83#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
84
85#define AUTO_ALL_MODES 0
86#define E1000_EEPROM_APME 0x0400
87
88#define E1000_MNG_VLAN_NONE (-1)
89
90/* Number of packet split data buffers (not including the header buffer) */
91#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
92
Bruce Allan2adc55c2009-06-02 11:28:58 +0000[diff] [blame]93#define DEFAULT_JUMBO 9234
94
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]95/* BM/HV Specific Registers */
96#define BM_PORT_CTRL_PAGE 769
97
98#define PHY_UPPER_SHIFT 21
99#define BM_PHY_REG(page, reg) \
100 (((reg) & MAX_PHY_REG_ADDRESS) |\
101 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
102 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
103
104/* PHY Wakeup Registers and defines */
105#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
106#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
107#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
108#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
109#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
110#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
111#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
112#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
113#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
114
115#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
116#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
117#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
118#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
119#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
120#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
121#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
122
123#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
124#define HV_SCC_LOWER PHY_REG(778, 17)
125#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
126#define HV_ECOL_LOWER PHY_REG(778, 19)
127#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
128#define HV_MCC_LOWER PHY_REG(778, 21)
129#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
130#define HV_LATECOL_LOWER PHY_REG(778, 24)
131#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
132#define HV_COLC_LOWER PHY_REG(778, 26)
133#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
134#define HV_DC_LOWER PHY_REG(778, 28)
135#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
136#define HV_TNCRS_LOWER PHY_REG(778, 30)
137
Bruce Allan38eb3942009-11-19 12:34:20 +0000[diff] [blame]138#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
139
Bruce Allan1d5846b2009-10-29 13:46:05 +0000[diff] [blame]140/* BM PHY Copper Specific Status */
141#define BM_CS_STATUS 17
142#define BM_CS_STATUS_LINK_UP 0x0400
143#define BM_CS_STATUS_RESOLVED 0x0800
144#define BM_CS_STATUS_SPEED_MASK 0xC000
145#define BM_CS_STATUS_SPEED_1000 0x8000
146
147/* 82577 Mobile Phy Status Register */
148#define HV_M_STATUS 26
149#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
150#define HV_M_STATUS_SPEED_MASK 0x0300
151#define HV_M_STATUS_SPEED_1000 0x0200
152#define HV_M_STATUS_LINK_UP 0x0040
153
Rafael J. Wysocki23606cf2010-03-14 14:35:17 +0000[diff] [blame]154/* Time to wait before putting the device into D3 if there's no link (in ms). */
155#define LINK_TIMEOUT 100
156
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +0000[diff] [blame]157#define DEFAULT_RDTR 0
158#define DEFAULT_RADV 8
159#define BURST_RDTR 0x20
160#define BURST_RADV 0x20
161
162/*
163 * in the case of WTHRESH, it appears at least the 82571/2 hardware
164 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
165 * WTHRESH=4, and since we want 64 bytes at a time written back, set
166 * it to 5
167 */
168#define E1000_TXDCTL_DMA_BURST_ENABLE \
169 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
170 E1000_TXDCTL_COUNT_DESC | \
171 (5 << 16) | /* wthresh must be +1 more than desired */\
172 (1 << 8) | /* hthresh */ \
173 0x1f) /* pthresh */
174
175#define E1000_RXDCTL_DMA_BURST_ENABLE \
176 (0x01000000 | /* set descriptor granularity */ \
177 (4 << 16) | /* set writeback threshold */ \
178 (4 << 8) | /* set prefetch threshold */ \
179 0x20) /* set hthresh */
180
181#define E1000_TIDV_FPD (1 << 31)
182#define E1000_RDTR_FPD (1 << 31)
183
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]184enum e1000_boards {
185 board_82571,
186 board_82572,
187 board_82573,
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]188 board_82574,
Alexander Duyck8c81c9c2009-03-19 01:12:27 +0000[diff] [blame]189 board_82583,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]190 board_80003es2lan,
191 board_ich8lan,
192 board_ich9lan,
Bruce Allanf4187b52008-08-26 18:36:50 -0700[diff] [blame]193 board_ich10lan,
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]194 board_pchlan,
Bruce Alland3738bb2010-06-16 13:27:28 +0000[diff] [blame]195 board_pch2lan,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]196};
197
198struct e1000_queue_stats {
199 u64 packets;
200 u64 bytes;
201};
202
203struct e1000_ps_page {
204 struct page *page;
205 u64 dma; /* must be u64 - written to hw */
206};
207
208/*
209 * wrappers around a pointer to a socket buffer,
210 * so a DMA handle can be stored along with the buffer
211 */
212struct e1000_buffer {
213 dma_addr_t dma;
214 struct sk_buff *skb;
215 union {
Bruce Allanad680762008-03-28 09:15:03 -0700[diff] [blame]216 /* Tx */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]217 struct {
218 unsigned long time_stamp;
219 u16 length;
220 u16 next_to_watch;
Tom Herbert9ed318d2010-05-05 14:02:27 +0000[diff] [blame]221 unsigned int segs;
222 unsigned int bytecount;
Alexander Duyck03b13202009-12-02 16:45:31 +0000[diff] [blame]223 u16 mapped_as_page;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]224 };
Bruce Allanad680762008-03-28 09:15:03 -0700[diff] [blame]225 /* Rx */
Alexander Duyck03b13202009-12-02 16:45:31 +0000[diff] [blame]226 struct {
227 /* arrays of page information for packet split */
228 struct e1000_ps_page *ps_pages;
229 struct page *page;
230 };
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]231 };
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]232};
233
234struct e1000_ring {
235 void *desc; /* pointer to ring memory */
236 dma_addr_t dma; /* phys address of ring */
237 unsigned int size; /* length of ring in bytes */
238 unsigned int count; /* number of desc. in ring */
239
240 u16 next_to_use;
241 u16 next_to_clean;
242
243 u16 head;
244 u16 tail;
245
246 /* array of buffer information structs */
247 struct e1000_buffer *buffer_info;
248
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]249 char name[IFNAMSIZ + 5];
250 u32 ims_val;
251 u32 itr_val;
252 u16 itr_register;
253 int set_itr;
254
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]255 struct sk_buff *rx_skb_top;
256
257 struct e1000_queue_stats stats;
258};
259
Bruce Allan7c257692008-04-23 11:09:00 -0700[diff] [blame]260/* PHY register snapshot values */
261struct e1000_phy_regs {
262 u16 bmcr; /* basic mode control register */
263 u16 bmsr; /* basic mode status register */
264 u16 advertise; /* auto-negotiation advertisement */
265 u16 lpa; /* link partner ability register */
266 u16 expansion; /* auto-negotiation expansion reg */
267 u16 ctrl1000; /* 1000BASE-T control register */
268 u16 stat1000; /* 1000BASE-T status register */
269 u16 estatus; /* extended status register */
270};
271
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]272/* board specific private data structure */
273struct e1000_adapter {
274 struct timer_list watchdog_timer;
275 struct timer_list phy_info_timer;
276 struct timer_list blink_timer;
277
278 struct work_struct reset_task;
279 struct work_struct watchdog_task;
280
281 const struct e1000_info *ei;
282
283 struct vlan_group *vlgrp;
284 u32 bd_number;
285 u32 rx_buffer_len;
286 u16 mng_vlan_id;
287 u16 link_speed;
288 u16 link_duplex;
Bruce Allan84527592008-11-21 17:00:22 -0800[diff] [blame]289 u16 eeprom_vers;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]290
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]291 /* track device up/down/testing state */
292 unsigned long state;
293
294 /* Interrupt Throttle Rate */
295 u32 itr;
296 u32 itr_setting;
297 u16 tx_itr;
298 u16 rx_itr;
299
300 /*
Bruce Allanad680762008-03-28 09:15:03 -0700[diff] [blame]301 * Tx
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]302 */
303 struct e1000_ring *tx_ring /* One per active queue */
304 ____cacheline_aligned_in_smp;
305
306 struct napi_struct napi;
307
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]308 unsigned int restart_queue;
309 u32 txd_cmd;
310
311 bool detect_tx_hung;
312 u8 tx_timeout_factor;
313
314 u32 tx_int_delay;
315 u32 tx_abs_int_delay;
316
317 unsigned int total_tx_bytes;
318 unsigned int total_tx_packets;
319 unsigned int total_rx_bytes;
320 unsigned int total_rx_packets;
321
Bruce Allanad680762008-03-28 09:15:03 -0700[diff] [blame]322 /* Tx stats */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]323 u64 tpt_old;
324 u64 colc_old;
Bruce Allan7c257692008-04-23 11:09:00 -0700[diff] [blame]325 u32 gotc;
326 u64 gotc_old;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]327 u32 tx_timeout_count;
328 u32 tx_fifo_head;
329 u32 tx_head_addr;
330 u32 tx_fifo_size;
331 u32 tx_dma_failed;
332
333 /*
Bruce Allanad680762008-03-28 09:15:03 -0700[diff] [blame]334 * Rx
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]335 */
336 bool (*clean_rx) (struct e1000_adapter *adapter,
337 int *work_done, int work_to_do)
338 ____cacheline_aligned_in_smp;
339 void (*alloc_rx_buf) (struct e1000_adapter *adapter,
340 int cleaned_count);
341 struct e1000_ring *rx_ring;
342
343 u32 rx_int_delay;
344 u32 rx_abs_int_delay;
345
Bruce Allanad680762008-03-28 09:15:03 -0700[diff] [blame]346 /* Rx stats */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]347 u64 hw_csum_err;
348 u64 hw_csum_good;
349 u64 rx_hdr_split;
Bruce Allan7c257692008-04-23 11:09:00 -0700[diff] [blame]350 u32 gorc;
351 u64 gorc_old;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]352 u32 alloc_rx_buff_failed;
353 u32 rx_dma_failed;
354
355 unsigned int rx_ps_pages;
356 u16 rx_ps_bsize0;
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700[diff] [blame]357 u32 max_frame_size;
358 u32 min_frame_size;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]359
360 /* OS defined structs */
361 struct net_device *netdev;
362 struct pci_dev *pdev;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]363
364 /* structs defined in e1000_hw.h */
365 struct e1000_hw hw;
366
367 struct e1000_hw_stats stats;
368 struct e1000_phy_info phy_info;
369 struct e1000_phy_stats phy_stats;
370
Bruce Allan7c257692008-04-23 11:09:00 -0700[diff] [blame]371 /* Snapshot of PHY registers */
372 struct e1000_phy_regs phy_regs;
373
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]374 struct e1000_ring test_tx_ring;
375 struct e1000_ring test_rx_ring;
376 u32 test_icr;
377
378 u32 msg_enable;
Jeff Kirsher8e86acd2010-08-02 14:27:23 +0000[diff] [blame]379 unsigned int num_vectors;
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]380 struct msix_entry *msix_entries;
381 int int_mode;
382 u32 eiac_mask;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]383
384 u32 eeprom_wol;
385 u32 wol;
386 u32 pba;
Bruce Allan2adc55c2009-06-02 11:28:58 +0000[diff] [blame]387 u32 max_hw_frame_size;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]388
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700[diff] [blame]389 bool fc_autoneg;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]390
391 unsigned long led_status;
392
393 unsigned int flags;
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000[diff] [blame]394 unsigned int flags2;
Jesse Brandeburga8f88ff2008-10-02 16:33:25 -0700[diff] [blame]395 struct work_struct downshift_task;
396 struct work_struct update_phy_task;
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]397 struct work_struct led_blink_task;
Bruce Allan41cec6f2009-11-20 23:28:56 +0000[diff] [blame]398 struct work_struct print_hang_task;
Rafael J. Wysocki23606cf2010-03-14 14:35:17 +0000[diff] [blame]399
400 bool idle_check;
Carolyn Wybornyff10e132010-10-28 00:59:53 +0000[diff] [blame]401 int phy_hang_count;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]402};
403
404struct e1000_info {
405 enum e1000_mac_type mac;
406 unsigned int flags;
Bruce Allan6f461f62010-04-27 03:33:04 +0000[diff] [blame]407 unsigned int flags2;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]408 u32 pba;
Bruce Allan2adc55c2009-06-02 11:28:58 +0000[diff] [blame]409 u32 max_hw_frame_size;
Jeff Kirsher69e3fd82008-04-02 13:48:18 -0700[diff] [blame]410 s32 (*get_variants)(struct e1000_adapter *);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]411 struct e1000_mac_operations *mac_ops;
412 struct e1000_phy_operations *phy_ops;
413 struct e1000_nvm_operations *nvm_ops;
414};
415
416/* hardware capability, feature, and workaround flags */
417#define FLAG_HAS_AMT (1 << 0)
418#define FLAG_HAS_FLASH (1 << 1)
419#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
420#define FLAG_HAS_WOL (1 << 3)
421#define FLAG_HAS_ERT (1 << 4)
422#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
423#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
424#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
Bruce Allan4a770352008-10-01 17:18:35 -0700[diff] [blame]425#define FLAG_READ_ONLY_NVM (1 << 8)
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700[diff] [blame]426#define FLAG_IS_ICH (1 << 9)
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]427#define FLAG_HAS_MSIX (1 << 10)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]428#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
429#define FLAG_IS_QUAD_PORT_A (1 << 12)
430#define FLAG_IS_QUAD_PORT (1 << 13)
431#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
432#define FLAG_APME_IN_WUC (1 << 15)
433#define FLAG_APME_IN_CTRL3 (1 << 16)
434#define FLAG_APME_CHECK_PORT_B (1 << 17)
435#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
436#define FLAG_NO_WAKE_UCAST (1 << 19)
437#define FLAG_MNG_PT_ENABLED (1 << 20)
438#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
439#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
440#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
441#define FLAG_RX_NEEDS_RESTART (1 << 24)
442#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
443#define FLAG_SMART_POWER_DOWN (1 << 26)
444#define FLAG_MSI_ENABLED (1 << 27)
445#define FLAG_RX_CSUM_ENABLED (1 << 28)
446#define FLAG_TSO_FORCE (1 << 29)
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700[diff] [blame]447#define FLAG_RX_RESTART_NOW (1 << 30)
Bruce Allanf8d59f72008-08-08 18:36:11 -0700[diff] [blame]448#define FLAG_MSI_TEST_FAILED (1 << 31)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]449
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000[diff] [blame]450/* CRC Stripping defines */
451#define FLAG2_CRC_STRIPPING (1 << 0)
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]452#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
Jesse Brandeburgb94b5022010-01-19 14:15:59 +0000[diff] [blame]453#define FLAG2_IS_DISCARDING (1 << 2)
Bruce Allan6f461f62010-04-27 03:33:04 +0000[diff] [blame]454#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
Bruce Allan8c7bbb92010-06-16 13:26:41 +0000[diff] [blame]455#define FLAG2_HAS_PHY_STATS (1 << 4)
Bruce Allane52997f2010-06-16 13:27:49 +0000[diff] [blame]456#define FLAG2_HAS_EEE (1 << 5)
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +0000[diff] [blame]457#define FLAG2_DMA_BURST (1 << 6)
Bruce Allan828bac82010-09-29 21:39:37 +0000[diff] [blame]458#define FLAG2_DISABLE_AIM (1 << 8)
Carolyn Wybornyff10e132010-10-28 00:59:53 +0000[diff] [blame]459#define FLAG2_CHECK_PHY_HANG (1 << 9)
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000[diff] [blame]460
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]461#define E1000_RX_DESC_PS(R, i) \
462 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
463#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
464#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
465#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
466#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
467
468enum e1000_state_t {
469 __E1000_TESTING,
470 __E1000_RESETTING,
471 __E1000_DOWN
472};
473
474enum latency_range {
475 lowest_latency = 0,
476 low_latency = 1,
477 bulk_latency = 2,
478 latency_invalid = 255
479};
480
481extern char e1000e_driver_name[];
482extern const char e1000e_driver_version[];
483
484extern void e1000e_check_options(struct e1000_adapter *adapter);
485extern void e1000e_set_ethtool_ops(struct net_device *netdev);
Holger Eitzenberger9633e632010-11-17 15:43:52 +0000[diff] [blame]486extern void e1000e_led_blink_task(struct work_struct *work);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]487
488extern int e1000e_up(struct e1000_adapter *adapter);
489extern void e1000e_down(struct e1000_adapter *adapter);
490extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
491extern void e1000e_reset(struct e1000_adapter *adapter);
492extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
493extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
494extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
495extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
496extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
497extern void e1000e_update_stats(struct e1000_adapter *adapter);
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]498extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
499extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
Bruce Allan31dbe5b2011-01-06 14:29:52 +0000[diff] [blame]500extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
501extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
Bruce Allan6f461f62010-04-27 03:33:04 +0000[diff] [blame]502extern void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]503
504extern unsigned int copybreak;
505
506extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
507
508extern struct e1000_info e1000_82571_info;
509extern struct e1000_info e1000_82572_info;
510extern struct e1000_info e1000_82573_info;
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]511extern struct e1000_info e1000_82574_info;
Alexander Duyck8c81c9c2009-03-19 01:12:27 +0000[diff] [blame]512extern struct e1000_info e1000_82583_info;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]513extern struct e1000_info e1000_ich8_info;
514extern struct e1000_info e1000_ich9_info;
Bruce Allanf4187b52008-08-26 18:36:50 -0700[diff] [blame]515extern struct e1000_info e1000_ich10_info;
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]516extern struct e1000_info e1000_pch_info;
Bruce Alland3738bb2010-06-16 13:27:28 +0000[diff] [blame]517extern struct e1000_info e1000_pch2_info;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]518extern struct e1000_info e1000_es2_info;
519
Bruce Allan073287c2010-11-24 06:01:51 +0000[diff] [blame]520extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
521 u32 pba_num_size);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]522
523extern s32 e1000e_commit_phy(struct e1000_hw *hw);
524
525extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
526
527extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
528extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
529
Bruce Allan4a770352008-10-01 17:18:35 -0700[diff] [blame]530extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]531extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
532 bool state);
533extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
534extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700[diff] [blame]535extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
Bruce Allanbb436b22009-11-20 23:24:11 +0000[diff] [blame]536extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
Bruce Alland3738bb2010-06-16 13:27:28 +0000[diff] [blame]537extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
538extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]539
540extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
541extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
542extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]543extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]544extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
545extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
546extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
547extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
Bruce Allanf4d2dd42010-01-13 02:05:18 +0000[diff] [blame]548extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
549extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]550extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
551extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
552extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
553extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
554extern s32 e1000e_id_led_init(struct e1000_hw *hw);
555extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
556extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
557extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
558extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
559extern s32 e1000e_setup_link(struct e1000_hw *hw);
Bruce Allancaaddaf2009-12-01 15:46:43 +0000[diff] [blame]560extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]561extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
Jeff Kirshere2de3eb2008-03-28 09:15:11 -0700[diff] [blame]562extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
563 u8 *mc_addr_list,
Bruce Allanab8932f2010-01-13 02:05:38 +0000[diff] [blame]564 u32 mc_addr_count);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]565extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
566extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
567extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
568extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
569extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
570extern void e1000e_config_collision_dist(struct e1000_hw *hw);
571extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
572extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
573extern s32 e1000e_blink_led(struct e1000_hw *hw);
Bruce Allancaaddaf2009-12-01 15:46:43 +0000[diff] [blame]574extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
Bruce Allan608f8a02010-01-13 02:04:58 +0000[diff] [blame]575extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]576extern void e1000e_reset_adaptive(struct e1000_hw *hw);
577extern void e1000e_update_adaptive(struct e1000_hw *hw);
578
579extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
580extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
581extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
582extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
583extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
584extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
585extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
586extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000[diff] [blame]587extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
588 u16 *data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]589extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
590extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
591extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000[diff] [blame]592extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
593 u16 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]594extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
595extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
596extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
597extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
598extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
599extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
600extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
Bruce Allanf4187b52008-08-26 18:36:50 -0700[diff] [blame]601extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]602extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700[diff] [blame]603extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
604extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
605extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]606extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
607extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]608extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
609extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000[diff] [blame]610extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
611 u16 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]612extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000[diff] [blame]613extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
614 u16 *data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]615extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
616 u32 usec_interval, bool *success);
617extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
Bruce Allan17f208d2009-12-01 15:47:22 +0000[diff] [blame]618extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
619extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
David Graham2d9498f2008-04-23 11:09:14 -0700[diff] [blame]620extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
621extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]622extern s32 e1000e_check_downshift(struct e1000_hw *hw);
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]623extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000[diff] [blame]624extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
625 u16 *data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]626extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000[diff] [blame]627extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
628 u16 data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000[diff] [blame]629extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
630extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
631extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
632extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
633extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
634extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]635
Bruce Allan0be84012009-12-02 17:03:18 +0000[diff] [blame]636extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
637extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
638extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
639extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
640extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
Carolyn Wybornyff10e132010-10-28 00:59:53 +0000[diff] [blame]641extern bool e1000_check_phy_82574(struct e1000_hw *hw);
Bruce Allan0be84012009-12-02 17:03:18 +0000[diff] [blame]642
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]643static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
644{
Bruce Allan94d81862009-11-20 23:25:26 +0000[diff] [blame]645 return hw->phy.ops.reset(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]646}
647
648static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
649{
650 return hw->phy.ops.check_reset_block(hw);
651}
652
653static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
654{
Bruce Allan94d81862009-11-20 23:25:26 +0000[diff] [blame]655 return hw->phy.ops.read_reg(hw, offset, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]656}
657
658static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
659{
Bruce Allan94d81862009-11-20 23:25:26 +0000[diff] [blame]660 return hw->phy.ops.write_reg(hw, offset, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]661}
662
663static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
664{
665 return hw->phy.ops.get_cable_length(hw);
666}
667
668extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
669extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
670extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
671extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]672extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
673extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
674extern void e1000e_release_nvm(struct e1000_hw *hw);
675extern void e1000e_reload_nvm(struct e1000_hw *hw);
Bruce Allan608f8a02010-01-13 02:04:58 +0000[diff] [blame]676extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
677
678static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
679{
680 if (hw->mac.ops.read_mac_addr)
681 return hw->mac.ops.read_mac_addr(hw);
682
683 return e1000_read_mac_addr_generic(hw);
684}
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]685
686static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
687{
Bruce Allan94d81862009-11-20 23:25:26 +0000[diff] [blame]688 return hw->nvm.ops.validate(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]689}
690
691static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
692{
Bruce Allan94d81862009-11-20 23:25:26 +0000[diff] [blame]693 return hw->nvm.ops.update(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]694}
695
696static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
697{
Bruce Allan94d81862009-11-20 23:25:26 +0000[diff] [blame]698 return hw->nvm.ops.read(hw, offset, words, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]699}
700
701static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
702{
Bruce Allan94d81862009-11-20 23:25:26 +0000[diff] [blame]703 return hw->nvm.ops.write(hw, offset, words, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]704}
705
706static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
707{
Bruce Allan94d81862009-11-20 23:25:26 +0000[diff] [blame]708 return hw->phy.ops.get_info(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]709}
710
Bruce Allan4662e822008-08-26 18:37:06 -0700[diff] [blame]711static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
712{
713 return hw->mac.ops.check_mng_mode(hw);
714}
715
716extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700[diff] [blame]717extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
718extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
719
720static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
721{
722 return readl(hw->hw_addr + reg);
723}
724
725static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
726{
727 writel(val, hw->hw_addr + reg);
728}
729
730#endif /* _E1000_H_ */