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gerrit-public.fairphone.software / kernel / msm / b6ad47303228775d0c9c8c6c54d958aaf5c11519 / . / arch / arm / mach-msm / clock-8226.c
blob: 78613d6aa94cdb54a2b1a342f7d6192765b6a658 [file] [log] [blame]
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/iopoll.h>
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]22#include <linux/regulator/consumer.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]23
24#include <mach/rpm-regulator-smd.h>
25#include <mach/socinfo.h>
26#include <mach/rpm-smd.h>
27
28#include "clock-local2.h"
29#include "clock-pll.h"
30#include "clock-rpm.h"
31#include "clock-voter.h"
32#include "clock-mdss-8974.h"
33#include "clock.h"
34
35enum {
36 GCC_BASE,
37 MMSS_BASE,
38 LPASS_BASE,
39 APCS_BASE,
40 APCS_PLL_BASE,
41 N_BASES,
42};
43
44static void __iomem *virt_bases[N_BASES];
45
46#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
47#define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x))
48#define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x))
49#define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x))
50
51/* Mux source select values */
52#define xo_source_val 0
53#define gpll0_source_val 1
54#define gpll1_source_val 2
55
56#define xo_mm_source_val 0
57#define mmpll0_pll_mm_source_val 1
58#define mmpll1_pll_mm_source_val 2
59#define mmpll2_pll_mm_source_val 3
60#define gpll0_mm_source_val 5
61#define dsipll_750_mm_source_val 1
62#define dsipll_667_mm_source_val 1
63
64#define gpll1_hsic_source_val 4
65
66#define xo_lpass_source_val 0
67#define lpaaudio_pll_lpass_source_val 1
68#define gpll0_lpass_source_val 5
69
70/* Prevent a divider of -1 */
71#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
72
73#define F_GCC(f, s, div, m, n) \
74 { \
75 .freq_hz = (f), \
76 .src_clk = &s.c, \
77 .m_val = (m), \
78 .n_val = ~((n)-(m)) * !!(n), \
79 .d_val = ~(n),\
80 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
81 | BVAL(10, 8, s##_source_val), \
82 }
83
84#define F_MMSS(f, s, div, m, n) \
85 { \
86 .freq_hz = (f), \
87 .src_clk = &s.c, \
88 .m_val = (m), \
89 .n_val = ~((n)-(m)) * !!(n), \
90 .d_val = ~(n),\
91 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
92 | BVAL(10, 8, s##_mm_source_val), \
93 }
94
95#define F_MDSS(f, s, div, m, n) \
96 { \
97 .freq_hz = (f), \
98 .m_val = (m), \
99 .n_val = ~((n)-(m)) * !!(n), \
100 .d_val = ~(n),\
101 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
102 | BVAL(10, 8, s##_mm_source_val), \
103 }
104
105#define F_HSIC(f, s, div, m, n) \
106 { \
107 .freq_hz = (f), \
108 .src_clk = &s.c, \
109 .m_val = (m), \
110 .n_val = ~((n)-(m)) * !!(n), \
111 .d_val = ~(n),\
112 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
113 | BVAL(10, 8, s##_hsic_source_val), \
114 }
115
116#define F_LPASS(f, s, div, m, n) \
117 { \
118 .freq_hz = (f), \
119 .src_clk = &s.c, \
120 .m_val = (m), \
121 .n_val = ~((n)-(m)) * !!(n), \
122 .d_val = ~(n),\
123 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
124 | BVAL(10, 8, s##_lpass_source_val), \
125 }
126
127#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \
128 { \
129 .freq_hz = (f), \
130 .l_val = (l), \
131 .m_val = (m), \
132 .n_val = (n), \
133 .pre_div_val = BVAL(12, 12, (pre_div)), \
134 .post_div_val = BVAL(9, 8, (post_div)), \
135 .vco_val = BVAL(29, 28, (vco)), \
136 }
137
138#define VDD_DIG_FMAX_MAP1(l1, f1) \
139 .vdd_class = &vdd_dig, \
140 .fmax = (unsigned long[VDD_DIG_NUM]) { \
141 [VDD_DIG_##l1] = (f1), \
142 }, \
143 .num_fmax = VDD_DIG_NUM
144
145#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
146 .vdd_class = &vdd_dig, \
147 .fmax = (unsigned long[VDD_DIG_NUM]) { \
148 [VDD_DIG_##l1] = (f1), \
149 [VDD_DIG_##l2] = (f2), \
150 }, \
151 .num_fmax = VDD_DIG_NUM
152
153#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
154 .vdd_class = &vdd_dig, \
155 .fmax = (unsigned long[VDD_DIG_NUM]) { \
156 [VDD_DIG_##l1] = (f1), \
157 [VDD_DIG_##l2] = (f2), \
158 [VDD_DIG_##l3] = (f3), \
159 }, \
160 .num_fmax = VDD_DIG_NUM
161
162enum vdd_dig_levels {
163 VDD_DIG_NONE,
164 VDD_DIG_LOW,
165 VDD_DIG_NOMINAL,
166 VDD_DIG_HIGH,
167 VDD_DIG_NUM
168};
169
170static const int vdd_corner[] = {
171 [VDD_DIG_NONE] = RPM_REGULATOR_CORNER_NONE,
172 [VDD_DIG_LOW] = RPM_REGULATOR_CORNER_SVS_SOC,
173 [VDD_DIG_NOMINAL] = RPM_REGULATOR_CORNER_NORMAL,
174 [VDD_DIG_HIGH] = RPM_REGULATOR_CORNER_SUPER_TURBO,
175};
176
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]177static struct regulator *vdd_dig_reg;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]178
179static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
180{
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]181 return regulator_set_voltage(vdd_dig_reg, vdd_corner[level],
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]182 RPM_REGULATOR_CORNER_SUPER_TURBO);
183}
184
185static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig, VDD_DIG_NUM);
186
187#define RPM_MISC_CLK_TYPE 0x306b6c63
188#define RPM_BUS_CLK_TYPE 0x316b6c63
189#define RPM_MEM_CLK_TYPE 0x326b6c63
190
191#define RPM_SMD_KEY_ENABLE 0x62616E45
192
193#define CXO_ID 0x0
194#define QDSS_ID 0x1
195
196#define PNOC_ID 0x0
197#define SNOC_ID 0x1
198#define CNOC_ID 0x2
199#define MMSSNOC_AHB_ID 0x3
200
201#define BIMC_ID 0x0
202#define OXILI_ID 0x1
203#define OCMEM_ID 0x2
204
205#define D0_ID 1
206#define D1_ID 2
207#define A0_ID 4
208#define A1_ID 5
209#define A2_ID 6
210#define DIFF_CLK_ID 7
211#define DIV_CLK1_ID 11
212#define DIV_CLK2_ID 12
213
214DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL);
215DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
216DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL);
217DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE,
218 MMSSNOC_AHB_ID, NULL);
219
220DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
221DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID,
222 NULL);
223DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID,
224 NULL);
225
226DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk,
227 RPM_MISC_CLK_TYPE, CXO_ID, 19200000);
228DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
229
230DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID);
231DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID);
232DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID);
233DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID);
234DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID);
235DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID);
236DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID);
237DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID);
238
239DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID);
240DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID);
241DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID);
242DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID);
243DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID);
244
245struct measure_mux_entry {
246 struct clk *c;
247 int base;
248 u32 debug_mux;
249};
250
251static struct branch_clk oxilicx_axi_clk;
252
253#define MSS_DEBUG_CLOCK_CTL 0x0078
254#define LPASS_DEBUG_CLK_CTL 0x29000
255#define GLB_CLK_DIAG 0x01C
256#define GLB_TEST_BUS_SEL 0x020
257
258#define MMPLL0_PLL_MODE (0x0000)
259#define MMPLL0_PLL_L_VAL (0x0004)
260#define MMPLL0_PLL_M_VAL (0x0008)
261#define MMPLL0_PLL_N_VAL (0x000C)
262#define MMPLL0_PLL_USER_CTL (0x0010)
263#define MMPLL0_PLL_STATUS (0x001C)
264#define MMPLL1_PLL_MODE (0x0040)
265#define MMPLL1_PLL_L_VAL (0x0044)
266#define MMPLL1_PLL_M_VAL (0x0048)
267#define MMPLL1_PLL_N_VAL (0x004C)
268#define MMPLL1_PLL_USER_CTL (0x0050)
269#define MMPLL1_PLL_STATUS (0x005C)
270#define MMSS_PLL_VOTE_APCS (0x0100)
271#define VCODEC0_CMD_RCGR (0x1000)
272#define VENUS0_VCODEC0_CBCR (0x1028)
273#define VENUS0_AHB_CBCR (0x1030)
274#define VENUS0_AXI_CBCR (0x1034)
275#define PCLK0_CMD_RCGR (0x2000)
276#define MDP_CMD_RCGR (0x2040)
277#define VSYNC_CMD_RCGR (0x2080)
278#define BYTE0_CMD_RCGR (0x2120)
279#define ESC0_CMD_RCGR (0x2160)
280#define MDSS_AHB_CBCR (0x2308)
281#define MDSS_AXI_CBCR (0x2310)
282#define MDSS_PCLK0_CBCR (0x2314)
283#define MDSS_MDP_CBCR (0x231C)
284#define MDSS_MDP_LUT_CBCR (0x2320)
285#define MDSS_VSYNC_CBCR (0x2328)
286#define MDSS_BYTE0_CBCR (0x233C)
287#define MDSS_ESC0_CBCR (0x2344)
288#define CSI0PHYTIMER_CMD_RCGR (0x3000)
289#define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024)
290#define CSI1PHYTIMER_CMD_RCGR (0x3030)
291#define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054)
292#define CSI0_CMD_RCGR (0x3090)
293#define CAMSS_CSI0_CBCR (0x30B4)
294#define CAMSS_CSI0_AHB_CBCR (0x30BC)
295#define CAMSS_CSI0PHY_CBCR (0x30C4)
296#define CAMSS_CSI0RDI_CBCR (0x30D4)
297#define CAMSS_CSI0PIX_CBCR (0x30E4)
298#define CSI1_CMD_RCGR (0x3100)
299#define CAMSS_CSI1_CBCR (0x3124)
300#define CAMSS_CSI1_AHB_CBCR (0x3128)
301#define CAMSS_CSI1PHY_CBCR (0x3134)
302#define CAMSS_CSI1RDI_CBCR (0x3144)
303#define CAMSS_CSI1PIX_CBCR (0x3154)
304#define CAMSS_ISPIF_AHB_CBCR (0x3224)
305#define CCI_CMD_RCGR (0x3300)
306#define CAMSS_CCI_CCI_CBCR (0x3344)
307#define CAMSS_CCI_CCI_AHB_CBCR (0x3348)
308#define MCLK0_CMD_RCGR (0x3360)
309#define CAMSS_MCLK0_CBCR (0x3384)
310#define MCLK1_CMD_RCGR (0x3390)
311#define CAMSS_MCLK1_CBCR (0x33B4)
312#define MMSS_GP0_CMD_RCGR (0x3420)
313#define CAMSS_GP0_CBCR (0x3444)
314#define MMSS_GP1_CMD_RCGR (0x3450)
315#define CAMSS_GP1_CBCR (0x3474)
316#define CAMSS_TOP_AHB_CBCR (0x3484)
317#define CAMSS_MICRO_AHB_CBCR (0x3494)
318#define JPEG0_CMD_RCGR (0x3500)
319#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
320#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
321#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
322#define VFE0_CMD_RCGR (0x3600)
323#define CPP_CMD_RCGR (0x3640)
324#define CAMSS_VFE_VFE0_CBCR (0x36A8)
325#define CAMSS_VFE_CPP_CBCR (0x36B0)
326#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
327#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
328#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
329#define CAMSS_CSI_VFE0_CBCR (0x3704)
330#define OXILI_GFX3D_CBCR (0x4028)
331#define OXILICX_AXI_CBCR (0x4038)
332#define OXILICX_AHB_CBCR (0x403C)
333#define OCMEMCX_AHB_CBCR (0x405C)
334#define MMPLL2_PLL_MODE (0x4100)
335#define MMPLL2_PLL_STATUS (0x411C)
336#define MMSS_MMSSNOC_AHB_CBCR (0x5024)
337#define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028)
338#define MMSS_MISC_AHB_CBCR (0x502C)
339#define AXI_CMD_RCGR (0x5040)
340#define MMSS_S0_AXI_CBCR (0x5064)
341#define MMSS_MMSSNOC_AXI_CBCR (0x506C)
342#define MMSS_DEBUG_CLK_CTL (0x0900)
343#define GPLL0_MODE (0x0000)
344#define GPLL0_L_VAL (0x0004)
345#define GPLL0_M_VAL (0x0008)
346#define GPLL0_N_VAL (0x000C)
347#define GPLL0_USER_CTL (0x0010)
348#define GPLL0_STATUS (0x001C)
349#define GPLL1_MODE (0x0040)
350#define GPLL1_L_VAL (0x0044)
351#define GPLL1_M_VAL (0x0048)
352#define GPLL1_N_VAL (0x004C)
353#define GPLL1_USER_CTL (0x0050)
354#define GPLL1_STATUS (0x005C)
355#define PERIPH_NOC_AHB_CBCR (0x0184)
356#define NOC_CONF_XPU_AHB_CBCR (0x01C0)
357#define MMSS_NOC_CFG_AHB_CBCR (0x024C)
358#define MSS_CFG_AHB_CBCR (0x0280)
359#define MSS_Q6_BIMC_AXI_CBCR (0x0284)
360#define USB_HS_HSIC_BCR (0x0400)
361#define USB_HSIC_AHB_CBCR (0x0408)
362#define USB_HSIC_SYSTEM_CMD_RCGR (0x041C)
363#define USB_HSIC_SYSTEM_CBCR (0x040C)
364#define USB_HSIC_CMD_RCGR (0x0440)
365#define USB_HSIC_CBCR (0x0410)
366#define USB_HSIC_IO_CAL_CMD_RCGR (0x0458)
367#define USB_HSIC_IO_CAL_CBCR (0x0414)
368#define USB_HS_BCR (0x0480)
369#define USB_HS_SYSTEM_CBCR (0x0484)
370#define USB_HS_AHB_CBCR (0x0488)
371#define USB_HS_SYSTEM_CMD_RCGR (0x0490)
372#define USB2A_PHY_SLEEP_CBCR (0x04AC)
373#define SDCC1_APPS_CMD_RCGR (0x04D0)
374#define SDCC1_APPS_CBCR (0x04C4)
375#define SDCC1_AHB_CBCR (0x04C8)
376#define SDCC2_APPS_CMD_RCGR (0x0510)
377#define SDCC2_APPS_CBCR (0x0504)
378#define SDCC2_AHB_CBCR (0x0508)
379#define SDCC3_APPS_CMD_RCGR (0x0550)
380#define SDCC3_APPS_CBCR (0x0544)
381#define SDCC3_AHB_CBCR (0x0548)
382#define BLSP1_AHB_CBCR (0x05C4)
383#define BLSP1_QUP1_SPI_APPS_CBCR (0x0644)
384#define BLSP1_QUP1_I2C_APPS_CBCR (0x0648)
385#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660)
386#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0)
387#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760)
388#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0)
389#define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860)
390#define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0)
391#define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C)
392#define BLSP1_UART1_APPS_CBCR (0x0684)
393#define BLSP1_UART1_APPS_CMD_RCGR (0x068C)
394#define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4)
395#define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8)
396#define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC)
397#define BLSP1_UART2_APPS_CBCR (0x0704)
398#define BLSP1_UART2_APPS_CMD_RCGR (0x070C)
399#define BLSP1_QUP3_SPI_APPS_CBCR (0x0744)
400#define BLSP1_QUP3_I2C_APPS_CBCR (0x0748)
401#define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C)
402#define BLSP1_UART3_APPS_CBCR (0x0784)
403#define BLSP1_UART3_APPS_CMD_RCGR (0x078C)
404#define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4)
405#define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8)
406#define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC)
407#define BLSP1_UART4_APPS_CBCR (0x0804)
408#define BLSP1_UART4_APPS_CMD_RCGR (0x080C)
409#define BLSP1_QUP5_SPI_APPS_CBCR (0x0844)
410#define BLSP1_QUP5_I2C_APPS_CBCR (0x0848)
411#define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C)
412#define BLSP1_UART5_APPS_CBCR (0x0884)
413#define BLSP1_UART5_APPS_CMD_RCGR (0x088C)
414#define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4)
415#define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8)
416#define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC)
417#define BLSP1_UART6_APPS_CBCR (0x0904)
418#define BLSP1_UART6_APPS_CMD_RCGR (0x090C)
419#define PDM_AHB_CBCR (0x0CC4)
420#define PDM_XO4_CBCR (0x0CC8)
421#define PDM2_CBCR (0x0CCC)
422#define PDM2_CMD_RCGR (0x0CD0)
423#define PRNG_AHB_CBCR (0x0D04)
424#define BAM_DMA_AHB_CBCR (0x0D44)
425#define BOOT_ROM_AHB_CBCR (0x0E04)
426#define CE1_CMD_RCGR (0x1050)
427#define CE1_CBCR (0x1044)
428#define CE1_AXI_CBCR (0x1048)
429#define CE1_AHB_CBCR (0x104C)
430#define GCC_XO_DIV4_CBCR (0x10C8)
431#define LPASS_Q6_AXI_CBCR (0x11C0)
432#define APCS_GPLL_ENA_VOTE (0x1480)
433#define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484)
434#define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488)
435#define GCC_DEBUG_CLK_CTL (0x1880)
436#define CLOCK_FRQ_MEASURE_CTL (0x1884)
437#define CLOCK_FRQ_MEASURE_STATUS (0x1888)
438#define PLLTEST_PAD_CFG (0x188C)
439#define GP1_CBCR (0x1900)
440#define GP1_CMD_RCGR (0x1904)
441#define GP2_CBCR (0x1940)
442#define GP2_CMD_RCGR (0x1944)
443#define GP3_CBCR (0x1980)
444#define GP3_CMD_RCGR (0x1984)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]445#define Q6SS_BCR (0x6000)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]446#define Q6SS_AHB_LFABIF_CBCR (0x22000)
447#define Q6SS_AHBM_CBCR (0x22004)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]448#define Q6SS_XO_CBCR (0x26000)
449
450static unsigned int soft_vote_gpll0;
451
452static struct pll_vote_clk gpll0 = {
453 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
454 .en_mask = BIT(0),
455 .status_reg = (void __iomem *)GPLL0_STATUS,
456 .status_mask = BIT(17),
457 .soft_vote = &soft_vote_gpll0,
458 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
459 .base = &virt_bases[GCC_BASE],
460 .c = {
461 .rate = 600000000,
462 .parent = &xo.c,
463 .dbg_name = "gpll0",
464 .ops = &clk_ops_pll_acpu_vote,
465 CLK_INIT(gpll0.c),
466 },
467};
468
469/*Don't vote for xo if using this clock to allow xo shutdown*/
470static struct pll_vote_clk gpll0_ao = {
471 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
472 .en_mask = BIT(0),
473 .status_reg = (void __iomem *)GPLL0_STATUS,
474 .status_mask = BIT(17),
475 .soft_vote = &soft_vote_gpll0,
476 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
477 .base = &virt_bases[GCC_BASE],
478 .c = {
479 .rate = 600000000,
480 .dbg_name = "gpll0_ao",
481 .ops = &clk_ops_pll_acpu_vote,
482 CLK_INIT(gpll0_ao.c),
483 },
484};
485
486static struct pll_vote_clk gpll1 = {
487 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
488 .en_mask = BIT(1),
489 .status_reg = (void __iomem *)GPLL1_STATUS,
490 .status_mask = BIT(17),
491 .base = &virt_bases[GCC_BASE],
492 .c = {
493 .rate = 480000000,
494 .parent = &xo.c,
495 .dbg_name = "gpll1",
496 .ops = &clk_ops_pll_vote,
497 CLK_INIT(gpll1.c),
498 },
499};
500
501static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]502 F_GCC( 19200000, xo, 1, 0, 0),
503 F_GCC( 50000000, gpll0, 12, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]504 F_END
505};
506
507static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
508 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
509 .set_rate = set_rate_hid,
510 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
511 .current_freq = &rcg_dummy_freq,
512 .base = &virt_bases[GCC_BASE],
513 .c = {
514 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
515 .ops = &clk_ops_rcg,
516 VDD_DIG_FMAX_MAP1(LOW, 50000000),
517 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
518 },
519};
520
521static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
522 F_GCC( 960000, xo, 10, 1, 2),
523 F_GCC( 4800000, xo, 4, 0, 0),
524 F_GCC( 9600000, xo, 2, 0, 0),
525 F_GCC( 15000000, gpll0, 10, 1, 4),
526 F_GCC( 19200000, xo, 1, 0, 0),
527 F_GCC( 25000000, gpll0, 12, 1, 2),
528 F_GCC( 50000000, gpll0, 12, 0, 0),
529 F_END
530};
531
532static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
533 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
534 .set_rate = set_rate_mnd,
535 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
536 .current_freq = &rcg_dummy_freq,
537 .base = &virt_bases[GCC_BASE],
538 .c = {
539 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
540 .ops = &clk_ops_rcg_mnd,
541 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
542 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
543 },
544};
545
546static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
547 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
548 .set_rate = set_rate_hid,
549 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
550 .current_freq = &rcg_dummy_freq,
551 .base = &virt_bases[GCC_BASE],
552 .c = {
553 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
554 .ops = &clk_ops_rcg,
555 VDD_DIG_FMAX_MAP1(LOW, 50000000),
556 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
557 },
558};
559
560static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
561 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
562 .set_rate = set_rate_mnd,
563 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
564 .current_freq = &rcg_dummy_freq,
565 .base = &virt_bases[GCC_BASE],
566 .c = {
567 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
568 .ops = &clk_ops_rcg_mnd,
569 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
570 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
571 },
572};
573
574static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
575 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
576 .set_rate = set_rate_hid,
577 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
578 .current_freq = &rcg_dummy_freq,
579 .base = &virt_bases[GCC_BASE],
580 .c = {
581 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
582 .ops = &clk_ops_rcg,
583 VDD_DIG_FMAX_MAP1(LOW, 50000000),
584 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
585 },
586};
587
588static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
589 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
590 .set_rate = set_rate_mnd,
591 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
592 .current_freq = &rcg_dummy_freq,
593 .base = &virt_bases[GCC_BASE],
594 .c = {
595 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
596 .ops = &clk_ops_rcg_mnd,
597 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
598 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
599 },
600};
601
602static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
603 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
604 .set_rate = set_rate_hid,
605 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
606 .current_freq = &rcg_dummy_freq,
607 .base = &virt_bases[GCC_BASE],
608 .c = {
609 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
610 .ops = &clk_ops_rcg,
611 VDD_DIG_FMAX_MAP1(LOW, 50000000),
612 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
613 },
614};
615
616static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
617 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
618 .set_rate = set_rate_mnd,
619 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
620 .current_freq = &rcg_dummy_freq,
621 .base = &virt_bases[GCC_BASE],
622 .c = {
623 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
624 .ops = &clk_ops_rcg_mnd,
625 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
626 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
627 },
628};
629
630static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
631 .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR,
632 .set_rate = set_rate_hid,
633 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
634 .current_freq = &rcg_dummy_freq,
635 .base = &virt_bases[GCC_BASE],
636 .c = {
637 .dbg_name = "blsp1_qup5_i2c_apps_clk_src",
638 .ops = &clk_ops_rcg,
639 VDD_DIG_FMAX_MAP1(LOW, 50000000),
640 CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
641 },
642};
643
644static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
645 .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR,
646 .set_rate = set_rate_mnd,
647 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
648 .current_freq = &rcg_dummy_freq,
649 .base = &virt_bases[GCC_BASE],
650 .c = {
651 .dbg_name = "blsp1_qup5_spi_apps_clk_src",
652 .ops = &clk_ops_rcg_mnd,
653 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
654 CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
655 },
656};
657
658static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
659 .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR,
660 .set_rate = set_rate_hid,
661 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
662 .current_freq = &rcg_dummy_freq,
663 .base = &virt_bases[GCC_BASE],
664 .c = {
665 .dbg_name = "blsp1_qup6_i2c_apps_clk_src",
666 .ops = &clk_ops_rcg,
667 VDD_DIG_FMAX_MAP1(LOW, 50000000),
668 CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
669 },
670};
671
672static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
673 .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR,
674 .set_rate = set_rate_mnd,
675 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
676 .current_freq = &rcg_dummy_freq,
677 .base = &virt_bases[GCC_BASE],
678 .c = {
679 .dbg_name = "blsp1_qup6_spi_apps_clk_src",
680 .ops = &clk_ops_rcg_mnd,
681 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
682 CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
683 },
684};
685
686static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
687 F_GCC( 3686400, gpll0, 1, 96, 15625),
688 F_GCC( 7372800, gpll0, 1, 192, 15625),
689 F_GCC( 14745600, gpll0, 1, 384, 15625),
690 F_GCC( 16000000, gpll0, 5, 2, 15),
691 F_GCC( 19200000, xo, 1, 0, 0),
692 F_GCC( 24000000, gpll0, 5, 1, 5),
693 F_GCC( 32000000, gpll0, 1, 4, 75),
694 F_GCC( 40000000, gpll0, 15, 0, 0),
695 F_GCC( 46400000, gpll0, 1, 29, 375),
696 F_GCC( 48000000, gpll0, 12.5, 0, 0),
697 F_GCC( 51200000, gpll0, 1, 32, 375),
698 F_GCC( 56000000, gpll0, 1, 7, 75),
699 F_GCC( 58982400, gpll0, 1, 1536, 15625),
700 F_GCC( 60000000, gpll0, 10, 0, 0),
701 F_END
702};
703
704static struct rcg_clk blsp1_uart1_apps_clk_src = {
705 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
706 .set_rate = set_rate_mnd,
707 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
708 .current_freq = &rcg_dummy_freq,
709 .base = &virt_bases[GCC_BASE],
710 .c = {
711 .dbg_name = "blsp1_uart1_apps_clk_src",
712 .ops = &clk_ops_rcg_mnd,
713 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
714 CLK_INIT(blsp1_uart1_apps_clk_src.c),
715 },
716};
717
718static struct rcg_clk blsp1_uart2_apps_clk_src = {
719 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
720 .set_rate = set_rate_mnd,
721 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
722 .current_freq = &rcg_dummy_freq,
723 .base = &virt_bases[GCC_BASE],
724 .c = {
725 .dbg_name = "blsp1_uart2_apps_clk_src",
726 .ops = &clk_ops_rcg_mnd,
727 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
728 CLK_INIT(blsp1_uart2_apps_clk_src.c),
729 },
730};
731
732static struct rcg_clk blsp1_uart3_apps_clk_src = {
733 .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR,
734 .set_rate = set_rate_mnd,
735 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
736 .current_freq = &rcg_dummy_freq,
737 .base = &virt_bases[GCC_BASE],
738 .c = {
739 .dbg_name = "blsp1_uart3_apps_clk_src",
740 .ops = &clk_ops_rcg_mnd,
741 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
742 CLK_INIT(blsp1_uart3_apps_clk_src.c),
743 },
744};
745
746static struct rcg_clk blsp1_uart4_apps_clk_src = {
747 .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR,
748 .set_rate = set_rate_mnd,
749 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
750 .current_freq = &rcg_dummy_freq,
751 .base = &virt_bases[GCC_BASE],
752 .c = {
753 .dbg_name = "blsp1_uart4_apps_clk_src",
754 .ops = &clk_ops_rcg_mnd,
755 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
756 CLK_INIT(blsp1_uart4_apps_clk_src.c),
757 },
758};
759
760static struct rcg_clk blsp1_uart5_apps_clk_src = {
761 .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR,
762 .set_rate = set_rate_mnd,
763 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
764 .current_freq = &rcg_dummy_freq,
765 .base = &virt_bases[GCC_BASE],
766 .c = {
767 .dbg_name = "blsp1_uart5_apps_clk_src",
768 .ops = &clk_ops_rcg_mnd,
769 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
770 CLK_INIT(blsp1_uart5_apps_clk_src.c),
771 },
772};
773
774static struct rcg_clk blsp1_uart6_apps_clk_src = {
775 .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR,
776 .set_rate = set_rate_mnd,
777 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
778 .current_freq = &rcg_dummy_freq,
779 .base = &virt_bases[GCC_BASE],
780 .c = {
781 .dbg_name = "blsp1_uart6_apps_clk_src",
782 .ops = &clk_ops_rcg_mnd,
783 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
784 CLK_INIT(blsp1_uart6_apps_clk_src.c),
785 },
786};
787
788static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
789 F_GCC( 50000000, gpll0, 12, 0, 0),
790 F_GCC( 100000000, gpll0, 6, 0, 0),
791 F_END
792};
793
794static struct rcg_clk ce1_clk_src = {
795 .cmd_rcgr_reg = CE1_CMD_RCGR,
796 .set_rate = set_rate_hid,
797 .freq_tbl = ftbl_gcc_ce1_clk,
798 .current_freq = &rcg_dummy_freq,
799 .base = &virt_bases[GCC_BASE],
800 .c = {
801 .dbg_name = "ce1_clk_src",
802 .ops = &clk_ops_rcg,
803 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
804 CLK_INIT(ce1_clk_src.c),
805 },
806};
807
808static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
809 F_GCC( 19200000, xo, 1, 0, 0),
810 F_END
811};
812
813static struct rcg_clk gp1_clk_src = {
814 .cmd_rcgr_reg = GP1_CMD_RCGR,
815 .set_rate = set_rate_mnd,
816 .freq_tbl = ftbl_gcc_gp1_3_clk,
817 .current_freq = &rcg_dummy_freq,
818 .base = &virt_bases[GCC_BASE],
819 .c = {
820 .dbg_name = "gp1_clk_src",
821 .ops = &clk_ops_rcg_mnd,
822 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
823 CLK_INIT(gp1_clk_src.c),
824 },
825};
826
827static struct rcg_clk gp2_clk_src = {
828 .cmd_rcgr_reg = GP2_CMD_RCGR,
829 .set_rate = set_rate_mnd,
830 .freq_tbl = ftbl_gcc_gp1_3_clk,
831 .current_freq = &rcg_dummy_freq,
832 .base = &virt_bases[GCC_BASE],
833 .c = {
834 .dbg_name = "gp2_clk_src",
835 .ops = &clk_ops_rcg_mnd,
836 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
837 CLK_INIT(gp2_clk_src.c),
838 },
839};
840
841static struct rcg_clk gp3_clk_src = {
842 .cmd_rcgr_reg = GP3_CMD_RCGR,
843 .set_rate = set_rate_mnd,
844 .freq_tbl = ftbl_gcc_gp1_3_clk,
845 .current_freq = &rcg_dummy_freq,
846 .base = &virt_bases[GCC_BASE],
847 .c = {
848 .dbg_name = "gp3_clk_src",
849 .ops = &clk_ops_rcg_mnd,
850 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
851 CLK_INIT(gp3_clk_src.c),
852 },
853};
854
855static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
856 F_GCC( 60000000, gpll0, 10, 0, 0),
857 F_END
858};
859
860static struct rcg_clk pdm2_clk_src = {
861 .cmd_rcgr_reg = PDM2_CMD_RCGR,
862 .set_rate = set_rate_hid,
863 .freq_tbl = ftbl_gcc_pdm2_clk,
864 .current_freq = &rcg_dummy_freq,
865 .base = &virt_bases[GCC_BASE],
866 .c = {
867 .dbg_name = "pdm2_clk_src",
868 .ops = &clk_ops_rcg,
869 VDD_DIG_FMAX_MAP1(LOW, 60000000),
870 CLK_INIT(pdm2_clk_src.c),
871 },
872};
873
874static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = {
875 F_GCC( 144000, xo, 16, 3, 25),
876 F_GCC( 400000, xo, 12, 1, 4),
877 F_GCC( 20000000, gpll0, 15, 1, 2),
878 F_GCC( 25000000, gpll0, 12, 1, 2),
879 F_GCC( 50000000, gpll0, 12, 0, 0),
880 F_GCC( 100000000, gpll0, 6, 0, 0),
881 F_GCC( 200000000, gpll0, 3, 0, 0),
882 F_END
883};
884
885static struct rcg_clk sdcc1_apps_clk_src = {
886 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
887 .set_rate = set_rate_mnd,
888 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
889 .current_freq = &rcg_dummy_freq,
890 .base = &virt_bases[GCC_BASE],
891 .c = {
892 .dbg_name = "sdcc1_apps_clk_src",
893 .ops = &clk_ops_rcg_mnd,
894 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
895 CLK_INIT(sdcc1_apps_clk_src.c),
896 },
897};
898
899static struct rcg_clk sdcc2_apps_clk_src = {
900 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
901 .set_rate = set_rate_mnd,
902 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
903 .current_freq = &rcg_dummy_freq,
904 .base = &virt_bases[GCC_BASE],
905 .c = {
906 .dbg_name = "sdcc2_apps_clk_src",
907 .ops = &clk_ops_rcg_mnd,
908 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
909 CLK_INIT(sdcc2_apps_clk_src.c),
910 },
911};
912
913static struct rcg_clk sdcc3_apps_clk_src = {
914 .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,
915 .set_rate = set_rate_mnd,
916 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
917 .current_freq = &rcg_dummy_freq,
918 .base = &virt_bases[GCC_BASE],
919 .c = {
920 .dbg_name = "sdcc3_apps_clk_src",
921 .ops = &clk_ops_rcg_mnd,
922 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
923 CLK_INIT(sdcc3_apps_clk_src.c),
924 },
925};
926
927static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
928 F_GCC( 75000000, gpll0, 8, 0, 0),
929 F_END
930};
931
932static struct rcg_clk usb_hs_system_clk_src = {
933 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
934 .set_rate = set_rate_hid,
935 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
936 .current_freq = &rcg_dummy_freq,
937 .base = &virt_bases[GCC_BASE],
938 .c = {
939 .dbg_name = "usb_hs_system_clk_src",
940 .ops = &clk_ops_rcg,
941 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
942 CLK_INIT(usb_hs_system_clk_src.c),
943 },
944};
945
946static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = {
947 F_HSIC( 480000000, gpll1, 0, 0, 0),
948 F_END
949};
950
951static struct rcg_clk usb_hsic_clk_src = {
952 .cmd_rcgr_reg = USB_HSIC_CMD_RCGR,
953 .set_rate = set_rate_hid,
954 .freq_tbl = ftbl_gcc_usb_hsic_clk,
955 .current_freq = &rcg_dummy_freq,
956 .base = &virt_bases[GCC_BASE],
957 .c = {
958 .dbg_name = "usb_hsic_clk_src",
959 .ops = &clk_ops_rcg,
960 VDD_DIG_FMAX_MAP1(LOW, 480000000),
961 CLK_INIT(usb_hsic_clk_src.c),
962 },
963};
964
965static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
966 F_GCC( 9600000, xo, 2, 0, 0),
967 F_END
968};
969
970static struct rcg_clk usb_hsic_io_cal_clk_src = {
971 .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR,
972 .set_rate = set_rate_hid,
973 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
974 .current_freq = &rcg_dummy_freq,
975 .base = &virt_bases[GCC_BASE],
976 .c = {
977 .dbg_name = "usb_hsic_io_cal_clk_src",
978 .ops = &clk_ops_rcg,
979 VDD_DIG_FMAX_MAP1(LOW, 9600000),
980 CLK_INIT(usb_hsic_io_cal_clk_src.c),
981 },
982};
983
984static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
985 F_GCC( 75000000, gpll0, 8, 0, 0),
986 F_END
987};
988
989static struct rcg_clk usb_hsic_system_clk_src = {
990 .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR,
991 .set_rate = set_rate_hid,
992 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
993 .current_freq = &rcg_dummy_freq,
994 .base = &virt_bases[GCC_BASE],
995 .c = {
996 .dbg_name = "usb_hsic_system_clk_src",
997 .ops = &clk_ops_rcg,
998 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
999 CLK_INIT(usb_hsic_system_clk_src.c),
1000 },
1001};
1002
1003static struct local_vote_clk gcc_bam_dma_ahb_clk = {
1004 .cbcr_reg = BAM_DMA_AHB_CBCR,
1005 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1006 .en_mask = BIT(12),
1007 .base = &virt_bases[GCC_BASE],
1008 .c = {
1009 .dbg_name = "gcc_bam_dma_ahb_clk",
1010 .ops = &clk_ops_vote,
1011 CLK_INIT(gcc_bam_dma_ahb_clk.c),
1012 },
1013};
1014
1015static struct local_vote_clk gcc_blsp1_ahb_clk = {
1016 .cbcr_reg = BLSP1_AHB_CBCR,
1017 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1018 .en_mask = BIT(17),
1019 .base = &virt_bases[GCC_BASE],
1020 .c = {
1021 .dbg_name = "gcc_blsp1_ahb_clk",
1022 .ops = &clk_ops_vote,
1023 CLK_INIT(gcc_blsp1_ahb_clk.c),
1024 },
1025};
1026
1027static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1028 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1029 .has_sibling = 0,
1030 .base = &virt_bases[GCC_BASE],
1031 .c = {
1032 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1033 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1034 .ops = &clk_ops_branch,
1035 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1036 },
1037};
1038
1039static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1040 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1041 .has_sibling = 0,
1042 .base = &virt_bases[GCC_BASE],
1043 .c = {
1044 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1045 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1046 .ops = &clk_ops_branch,
1047 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1048 },
1049};
1050
1051static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1052 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1053 .has_sibling = 0,
1054 .base = &virt_bases[GCC_BASE],
1055 .c = {
1056 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1057 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1058 .ops = &clk_ops_branch,
1059 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1060 },
1061};
1062
1063static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1064 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1065 .has_sibling = 0,
1066 .base = &virt_bases[GCC_BASE],
1067 .c = {
1068 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1069 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1070 .ops = &clk_ops_branch,
1071 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1072 },
1073};
1074
1075static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1076 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1077 .has_sibling = 0,
1078 .base = &virt_bases[GCC_BASE],
1079 .c = {
1080 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1081 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1082 .ops = &clk_ops_branch,
1083 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1084 },
1085};
1086
1087static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1088 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1089 .has_sibling = 0,
1090 .base = &virt_bases[GCC_BASE],
1091 .c = {
1092 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1093 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1094 .ops = &clk_ops_branch,
1095 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1096 },
1097};
1098
1099static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
1100 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
1101 .has_sibling = 0,
1102 .base = &virt_bases[GCC_BASE],
1103 .c = {
1104 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
1105 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
1106 .ops = &clk_ops_branch,
1107 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
1108 },
1109};
1110
1111static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
1112 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
1113 .has_sibling = 0,
1114 .base = &virt_bases[GCC_BASE],
1115 .c = {
1116 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
1117 .parent = &blsp1_qup4_spi_apps_clk_src.c,
1118 .ops = &clk_ops_branch,
1119 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
1120 },
1121};
1122
1123static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
1124 .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
1125 .has_sibling = 0,
1126 .base = &virt_bases[GCC_BASE],
1127 .c = {
1128 .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
1129 .parent = &blsp1_qup5_i2c_apps_clk_src.c,
1130 .ops = &clk_ops_branch,
1131 CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
1132 },
1133};
1134
1135static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
1136 .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
1137 .has_sibling = 0,
1138 .base = &virt_bases[GCC_BASE],
1139 .c = {
1140 .dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
1141 .parent = &blsp1_qup5_spi_apps_clk_src.c,
1142 .ops = &clk_ops_branch,
1143 CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
1144 },
1145};
1146
1147static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
1148 .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
1149 .has_sibling = 0,
1150 .base = &virt_bases[GCC_BASE],
1151 .c = {
1152 .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
1153 .parent = &blsp1_qup6_i2c_apps_clk_src.c,
1154 .ops = &clk_ops_branch,
1155 CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
1156 },
1157};
1158
1159static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
1160 .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
1161 .has_sibling = 0,
1162 .base = &virt_bases[GCC_BASE],
1163 .c = {
1164 .dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
1165 .parent = &blsp1_qup6_spi_apps_clk_src.c,
1166 .ops = &clk_ops_branch,
1167 CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
1168 },
1169};
1170
1171static struct branch_clk gcc_blsp1_uart1_apps_clk = {
1172 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
1173 .has_sibling = 0,
1174 .base = &virt_bases[GCC_BASE],
1175 .c = {
1176 .dbg_name = "gcc_blsp1_uart1_apps_clk",
1177 .parent = &blsp1_uart1_apps_clk_src.c,
1178 .ops = &clk_ops_branch,
1179 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
1180 },
1181};
1182
1183static struct branch_clk gcc_blsp1_uart2_apps_clk = {
1184 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
1185 .has_sibling = 0,
1186 .base = &virt_bases[GCC_BASE],
1187 .c = {
1188 .dbg_name = "gcc_blsp1_uart2_apps_clk",
1189 .parent = &blsp1_uart2_apps_clk_src.c,
1190 .ops = &clk_ops_branch,
1191 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
1192 },
1193};
1194
1195static struct branch_clk gcc_blsp1_uart3_apps_clk = {
1196 .cbcr_reg = BLSP1_UART3_APPS_CBCR,
1197 .has_sibling = 0,
1198 .base = &virt_bases[GCC_BASE],
1199 .c = {
1200 .dbg_name = "gcc_blsp1_uart3_apps_clk",
1201 .parent = &blsp1_uart3_apps_clk_src.c,
1202 .ops = &clk_ops_branch,
1203 CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
1204 },
1205};
1206
1207static struct branch_clk gcc_blsp1_uart4_apps_clk = {
1208 .cbcr_reg = BLSP1_UART4_APPS_CBCR,
1209 .has_sibling = 0,
1210 .base = &virt_bases[GCC_BASE],
1211 .c = {
1212 .dbg_name = "gcc_blsp1_uart4_apps_clk",
1213 .parent = &blsp1_uart4_apps_clk_src.c,
1214 .ops = &clk_ops_branch,
1215 CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
1216 },
1217};
1218
1219static struct branch_clk gcc_blsp1_uart5_apps_clk = {
1220 .cbcr_reg = BLSP1_UART5_APPS_CBCR,
1221 .has_sibling = 0,
1222 .base = &virt_bases[GCC_BASE],
1223 .c = {
1224 .dbg_name = "gcc_blsp1_uart5_apps_clk",
1225 .parent = &blsp1_uart5_apps_clk_src.c,
1226 .ops = &clk_ops_branch,
1227 CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
1228 },
1229};
1230
1231static struct branch_clk gcc_blsp1_uart6_apps_clk = {
1232 .cbcr_reg = BLSP1_UART6_APPS_CBCR,
1233 .has_sibling = 0,
1234 .base = &virt_bases[GCC_BASE],
1235 .c = {
1236 .dbg_name = "gcc_blsp1_uart6_apps_clk",
1237 .parent = &blsp1_uart6_apps_clk_src.c,
1238 .ops = &clk_ops_branch,
1239 CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
1240 },
1241};
1242
1243static struct local_vote_clk gcc_boot_rom_ahb_clk = {
1244 .cbcr_reg = BOOT_ROM_AHB_CBCR,
1245 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1246 .en_mask = BIT(10),
1247 .base = &virt_bases[GCC_BASE],
1248 .c = {
1249 .dbg_name = "gcc_boot_rom_ahb_clk",
1250 .ops = &clk_ops_vote,
1251 CLK_INIT(gcc_boot_rom_ahb_clk.c),
1252 },
1253};
1254
1255static struct local_vote_clk gcc_ce1_ahb_clk = {
1256 .cbcr_reg = CE1_AHB_CBCR,
1257 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1258 .en_mask = BIT(3),
1259 .base = &virt_bases[GCC_BASE],
1260 .c = {
1261 .dbg_name = "gcc_ce1_ahb_clk",
1262 .ops = &clk_ops_vote,
1263 CLK_INIT(gcc_ce1_ahb_clk.c),
1264 },
1265};
1266
1267static struct local_vote_clk gcc_ce1_axi_clk = {
1268 .cbcr_reg = CE1_AXI_CBCR,
1269 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1270 .en_mask = BIT(4),
1271 .base = &virt_bases[GCC_BASE],
1272 .c = {
1273 .dbg_name = "gcc_ce1_axi_clk",
1274 .ops = &clk_ops_vote,
1275 CLK_INIT(gcc_ce1_axi_clk.c),
1276 },
1277};
1278
1279static struct local_vote_clk gcc_ce1_clk = {
1280 .cbcr_reg = CE1_CBCR,
1281 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1282 .en_mask = BIT(5),
1283 .base = &virt_bases[GCC_BASE],
1284 .c = {
1285 .dbg_name = "gcc_ce1_clk",
1286 .ops = &clk_ops_vote,
1287 CLK_INIT(gcc_ce1_clk.c),
1288 },
1289};
1290
1291static struct branch_clk gcc_gp1_clk = {
1292 .cbcr_reg = GP1_CBCR,
1293 .has_sibling = 0,
1294 .base = &virt_bases[GCC_BASE],
1295 .c = {
1296 .dbg_name = "gcc_gp1_clk",
1297 .parent = &gp1_clk_src.c,
1298 .ops = &clk_ops_branch,
1299 CLK_INIT(gcc_gp1_clk.c),
1300 },
1301};
1302
1303static struct branch_clk gcc_gp2_clk = {
1304 .cbcr_reg = GP2_CBCR,
1305 .has_sibling = 0,
1306 .base = &virt_bases[GCC_BASE],
1307 .c = {
1308 .dbg_name = "gcc_gp2_clk",
1309 .parent = &gp2_clk_src.c,
1310 .ops = &clk_ops_branch,
1311 CLK_INIT(gcc_gp2_clk.c),
1312 },
1313};
1314
1315static struct branch_clk gcc_gp3_clk = {
1316 .cbcr_reg = GP3_CBCR,
1317 .has_sibling = 0,
1318 .base = &virt_bases[GCC_BASE],
1319 .c = {
1320 .dbg_name = "gcc_gp3_clk",
1321 .parent = &gp3_clk_src.c,
1322 .ops = &clk_ops_branch,
1323 CLK_INIT(gcc_gp3_clk.c),
1324 },
1325};
1326
1327static struct branch_clk gcc_lpass_q6_axi_clk = {
1328 .cbcr_reg = LPASS_Q6_AXI_CBCR,
1329 .has_sibling = 1,
1330 .base = &virt_bases[GCC_BASE],
1331 .c = {
1332 .dbg_name = "gcc_lpass_q6_axi_clk",
1333 .ops = &clk_ops_branch,
1334 CLK_INIT(gcc_lpass_q6_axi_clk.c),
1335 },
1336};
1337
1338static struct branch_clk gcc_mmss_noc_cfg_ahb_clk = {
1339 .cbcr_reg = MMSS_NOC_CFG_AHB_CBCR,
1340 .has_sibling = 1,
1341 .base = &virt_bases[GCC_BASE],
1342 .c = {
1343 .dbg_name = "gcc_mmss_noc_cfg_ahb_clk",
1344 .ops = &clk_ops_branch,
1345 CLK_INIT(gcc_mmss_noc_cfg_ahb_clk.c),
1346 },
1347};
1348
1349static struct branch_clk gcc_mss_cfg_ahb_clk = {
1350 .cbcr_reg = MSS_CFG_AHB_CBCR,
1351 .has_sibling = 1,
1352 .base = &virt_bases[GCC_BASE],
1353 .c = {
1354 .dbg_name = "gcc_mss_cfg_ahb_clk",
1355 .ops = &clk_ops_branch,
1356 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
1357 },
1358};
1359
1360static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
1361 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
1362 .has_sibling = 1,
1363 .base = &virt_bases[GCC_BASE],
1364 .c = {
1365 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
1366 .ops = &clk_ops_branch,
1367 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
1368 },
1369};
1370
1371static struct branch_clk gcc_noc_conf_xpu_ahb_clk = {
1372 .cbcr_reg = NOC_CONF_XPU_AHB_CBCR,
1373 .has_sibling = 1,
1374 .base = &virt_bases[GCC_BASE],
1375 .c = {
1376 .dbg_name = "gcc_noc_conf_xpu_ahb_clk",
1377 .ops = &clk_ops_branch,
1378 CLK_INIT(gcc_noc_conf_xpu_ahb_clk.c),
1379 },
1380};
1381
1382static struct branch_clk gcc_pdm2_clk = {
1383 .cbcr_reg = PDM2_CBCR,
1384 .has_sibling = 0,
1385 .base = &virt_bases[GCC_BASE],
1386 .c = {
1387 .dbg_name = "gcc_pdm2_clk",
1388 .parent = &pdm2_clk_src.c,
1389 .ops = &clk_ops_branch,
1390 CLK_INIT(gcc_pdm2_clk.c),
1391 },
1392};
1393
1394static struct branch_clk gcc_pdm_ahb_clk = {
1395 .cbcr_reg = PDM_AHB_CBCR,
1396 .has_sibling = 1,
1397 .base = &virt_bases[GCC_BASE],
1398 .c = {
1399 .dbg_name = "gcc_pdm_ahb_clk",
1400 .ops = &clk_ops_branch,
1401 CLK_INIT(gcc_pdm_ahb_clk.c),
1402 },
1403};
1404
1405static struct branch_clk gcc_pdm_xo4_clk = {
1406 .cbcr_reg = PDM_XO4_CBCR,
1407 .has_sibling = 1,
1408 .base = &virt_bases[GCC_BASE],
1409 .c = {
1410 .dbg_name = "gcc_pdm_xo4_clk",
1411 .parent = &xo.c,
1412 .ops = &clk_ops_branch,
1413 CLK_INIT(gcc_pdm_xo4_clk.c),
1414 },
1415};
1416
1417static struct branch_clk gcc_periph_noc_ahb_clk = {
1418 .cbcr_reg = PERIPH_NOC_AHB_CBCR,
1419 .has_sibling = 1,
1420 .base = &virt_bases[GCC_BASE],
1421 .c = {
1422 .dbg_name = "gcc_periph_noc_ahb_clk",
1423 .ops = &clk_ops_branch,
1424 CLK_INIT(gcc_periph_noc_ahb_clk.c),
1425 },
1426};
1427
1428static struct local_vote_clk gcc_prng_ahb_clk = {
1429 .cbcr_reg = PRNG_AHB_CBCR,
1430 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1431 .en_mask = BIT(13),
1432 .base = &virt_bases[GCC_BASE],
1433 .c = {
1434 .dbg_name = "gcc_prng_ahb_clk",
1435 .ops = &clk_ops_vote,
1436 CLK_INIT(gcc_prng_ahb_clk.c),
1437 },
1438};
1439
1440static struct branch_clk gcc_sdcc1_ahb_clk = {
1441 .cbcr_reg = SDCC1_AHB_CBCR,
1442 .has_sibling = 1,
1443 .base = &virt_bases[GCC_BASE],
1444 .c = {
1445 .dbg_name = "gcc_sdcc1_ahb_clk",
1446 .ops = &clk_ops_branch,
1447 CLK_INIT(gcc_sdcc1_ahb_clk.c),
1448 },
1449};
1450
1451static struct branch_clk gcc_sdcc1_apps_clk = {
1452 .cbcr_reg = SDCC1_APPS_CBCR,
1453 .has_sibling = 0,
1454 .base = &virt_bases[GCC_BASE],
1455 .c = {
1456 .dbg_name = "gcc_sdcc1_apps_clk",
1457 .parent = &sdcc1_apps_clk_src.c,
1458 .ops = &clk_ops_branch,
1459 CLK_INIT(gcc_sdcc1_apps_clk.c),
1460 },
1461};
1462
1463static struct branch_clk gcc_sdcc2_ahb_clk = {
1464 .cbcr_reg = SDCC2_AHB_CBCR,
1465 .has_sibling = 1,
1466 .base = &virt_bases[GCC_BASE],
1467 .c = {
1468 .dbg_name = "gcc_sdcc2_ahb_clk",
1469 .ops = &clk_ops_branch,
1470 CLK_INIT(gcc_sdcc2_ahb_clk.c),
1471 },
1472};
1473
1474static struct branch_clk gcc_sdcc2_apps_clk = {
1475 .cbcr_reg = SDCC2_APPS_CBCR,
1476 .has_sibling = 0,
1477 .base = &virt_bases[GCC_BASE],
1478 .c = {
1479 .dbg_name = "gcc_sdcc2_apps_clk",
1480 .parent = &sdcc2_apps_clk_src.c,
1481 .ops = &clk_ops_branch,
1482 CLK_INIT(gcc_sdcc2_apps_clk.c),
1483 },
1484};
1485
1486static struct branch_clk gcc_sdcc3_ahb_clk = {
1487 .cbcr_reg = SDCC3_AHB_CBCR,
1488 .has_sibling = 1,
1489 .base = &virt_bases[GCC_BASE],
1490 .c = {
1491 .dbg_name = "gcc_sdcc3_ahb_clk",
1492 .ops = &clk_ops_branch,
1493 CLK_INIT(gcc_sdcc3_ahb_clk.c),
1494 },
1495};
1496
1497static struct branch_clk gcc_sdcc3_apps_clk = {
1498 .cbcr_reg = SDCC3_APPS_CBCR,
1499 .has_sibling = 0,
1500 .base = &virt_bases[GCC_BASE],
1501 .c = {
1502 .dbg_name = "gcc_sdcc3_apps_clk",
1503 .parent = &sdcc3_apps_clk_src.c,
1504 .ops = &clk_ops_branch,
1505 CLK_INIT(gcc_sdcc3_apps_clk.c),
1506 },
1507};
1508
1509static struct branch_clk gcc_usb2a_phy_sleep_clk = {
1510 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
1511 .has_sibling = 1,
1512 .base = &virt_bases[GCC_BASE],
1513 .c = {
1514 .dbg_name = "gcc_usb2a_phy_sleep_clk",
1515 .ops = &clk_ops_branch,
1516 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
1517 },
1518};
1519
1520static struct branch_clk gcc_usb_hs_ahb_clk = {
1521 .cbcr_reg = USB_HS_AHB_CBCR,
1522 .has_sibling = 1,
1523 .base = &virt_bases[GCC_BASE],
1524 .c = {
1525 .dbg_name = "gcc_usb_hs_ahb_clk",
1526 .ops = &clk_ops_branch,
1527 CLK_INIT(gcc_usb_hs_ahb_clk.c),
1528 },
1529};
1530
1531static struct branch_clk gcc_usb_hs_system_clk = {
1532 .cbcr_reg = USB_HS_SYSTEM_CBCR,
1533 .has_sibling = 0,
1534 .bcr_reg = USB_HS_BCR,
1535 .base = &virt_bases[GCC_BASE],
1536 .c = {
1537 .dbg_name = "gcc_usb_hs_system_clk",
1538 .parent = &usb_hs_system_clk_src.c,
1539 .ops = &clk_ops_branch,
1540 CLK_INIT(gcc_usb_hs_system_clk.c),
1541 },
1542};
1543
1544static struct branch_clk gcc_usb_hsic_ahb_clk = {
1545 .cbcr_reg = USB_HSIC_AHB_CBCR,
1546 .has_sibling = 1,
1547 .base = &virt_bases[GCC_BASE],
1548 .c = {
1549 .dbg_name = "gcc_usb_hsic_ahb_clk",
1550 .ops = &clk_ops_branch,
1551 CLK_INIT(gcc_usb_hsic_ahb_clk.c),
1552 },
1553};
1554
1555static struct branch_clk gcc_usb_hsic_clk = {
1556 .cbcr_reg = USB_HSIC_CBCR,
1557 .has_sibling = 0,
1558 .bcr_reg = USB_HS_HSIC_BCR,
1559 .base = &virt_bases[GCC_BASE],
1560 .c = {
1561 .dbg_name = "gcc_usb_hsic_clk",
1562 .parent = &usb_hsic_clk_src.c,
1563 .ops = &clk_ops_branch,
1564 CLK_INIT(gcc_usb_hsic_clk.c),
1565 },
1566};
1567
1568static struct branch_clk gcc_usb_hsic_io_cal_clk = {
1569 .cbcr_reg = USB_HSIC_IO_CAL_CBCR,
1570 .has_sibling = 0,
1571 .base = &virt_bases[GCC_BASE],
1572 .c = {
1573 .dbg_name = "gcc_usb_hsic_io_cal_clk",
1574 .parent = &usb_hsic_io_cal_clk_src.c,
1575 .ops = &clk_ops_branch,
1576 CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
1577 },
1578};
1579
1580static struct branch_clk gcc_usb_hsic_system_clk = {
1581 .cbcr_reg = USB_HSIC_SYSTEM_CBCR,
1582 .has_sibling = 0,
1583 .bcr_reg = USB_HS_HSIC_BCR,
1584 .base = &virt_bases[GCC_BASE],
1585 .c = {
1586 .dbg_name = "gcc_usb_hsic_system_clk",
1587 .parent = &usb_hsic_system_clk_src.c,
1588 .ops = &clk_ops_branch,
1589 CLK_INIT(gcc_usb_hsic_system_clk.c),
1590 },
1591};
1592
1593static struct measure_mux_entry measure_mux_GCC[] = {
1594 { &gcc_periph_noc_ahb_clk.c, GCC_BASE, 0x0010 },
1595 { &gcc_noc_conf_xpu_ahb_clk.c, GCC_BASE, 0x0018 },
1596 { &gcc_mmss_noc_cfg_ahb_clk.c, GCC_BASE, 0x002a },
1597 { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 },
1598 { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 },
1599 { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 },
1600 { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 },
1601 { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a },
1602 { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b },
1603 { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 },
1604 { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 },
1605 { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 },
1606 { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 },
1607 { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 },
1608 { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 },
1609 { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 },
1610 { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 },
1611 { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 },
1612 { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 },
1613 { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a },
1614 { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b },
1615 { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c },
1616 { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e },
1617 { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 },
1618 { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 },
1619 { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 },
1620 { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 },
1621 { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 },
1622 { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 },
1623 { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 },
1624 { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a },
1625 { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c },
1626 { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d },
1627 { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e },
1628 { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 },
1629 { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 },
1630 { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 },
1631 { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 },
1632 { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 },
1633 { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 },
1634 { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 },
1635 { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 },
1636 { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 },
1637 { &gcc_ce1_clk.c, GCC_BASE, 0x0138 },
1638 { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 },
1639 { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a },
1640 { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 },
1641 {&dummy_clk, N_BASES, 0x0000},
1642};
1643
1644static struct pll_vote_clk mmpll0_pll = {
1645 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1646 .en_mask = BIT(0),
1647 .status_reg = (void __iomem *)MMPLL0_PLL_STATUS,
1648 .status_mask = BIT(17),
1649 .base = &virt_bases[MMSS_BASE],
1650 .c = {
1651 .rate = 800000000,
1652 .parent = &xo.c,
1653 .dbg_name = "mmpll0_pll",
1654 .ops = &clk_ops_pll_vote,
1655 CLK_INIT(mmpll0_pll.c),
1656 },
1657};
1658
1659static struct pll_vote_clk mmpll1_pll = {
1660 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1661 .en_mask = BIT(1),
1662 .status_reg = (void __iomem *)MMPLL1_PLL_STATUS,
1663 .status_mask = BIT(17),
1664 .base = &virt_bases[MMSS_BASE],
1665 .c = {
1666 .rate = 1000000000,
1667 .parent = &xo.c,
1668 .dbg_name = "mmpll1_pll",
1669 .ops = &clk_ops_pll_vote,
1670 CLK_INIT(mmpll1_pll.c),
1671 },
1672};
1673
1674static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = {
1675 F_MMSS( 19200000, xo, 1, 0, 0),
1676 F_MMSS( 37500000, gpll0, 16, 0, 0),
1677 F_MMSS( 50000000, gpll0, 12, 0, 0),
1678 F_MMSS( 75000000, gpll0, 8, 0, 0),
1679 F_MMSS( 100000000, gpll0, 6, 0, 0),
1680 F_MMSS( 150000000, gpll0, 4, 0, 0),
1681 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1682 F_MMSS( 266000000, mmpll0_pll, 3, 0, 0),
1683 F_END
1684};
1685
1686static struct rcg_clk axi_clk_src = {
1687 .cmd_rcgr_reg = AXI_CMD_RCGR,
1688 .set_rate = set_rate_hid,
1689 .freq_tbl = ftbl_mmss_mmssnoc_axi_clk,
1690 .current_freq = &rcg_dummy_freq,
1691 .base = &virt_bases[MMSS_BASE],
1692 .c = {
1693 .dbg_name = "axi_clk_src",
1694 .ops = &clk_ops_rcg,
1695 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1696 266670000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1697 CLK_INIT(axi_clk_src.c),
1698 },
1699};
1700
1701static struct pll_clk mmpll2_pll = {
1702 .mode_reg = (void __iomem *)MMPLL2_PLL_MODE,
1703 .status_reg = (void __iomem *)MMPLL2_PLL_STATUS,
1704 .base = &virt_bases[MMSS_BASE],
1705 .c = {
1706 .dbg_name = "mmpll2_pll",
1707 .parent = &xo.c,
1708 .rate = 900000000,
1709 .ops = &clk_ops_local_pll,
1710 CLK_INIT(mmpll2_pll.c),
1711 },
1712};
1713
1714static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = {
1715 F_MMSS( 100000000, gpll0, 6, 0, 0),
1716 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1717 F_END
1718};
1719
1720static struct rcg_clk csi0_clk_src = {
1721 .cmd_rcgr_reg = CSI0_CMD_RCGR,
1722 .set_rate = set_rate_hid,
1723 .freq_tbl = ftbl_camss_csi0_1_clk,
1724 .current_freq = &rcg_dummy_freq,
1725 .base = &virt_bases[MMSS_BASE],
1726 .c = {
1727 .dbg_name = "csi0_clk_src",
1728 .ops = &clk_ops_rcg,
1729 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1730 CLK_INIT(csi0_clk_src.c),
1731 },
1732};
1733
1734static struct rcg_clk csi1_clk_src = {
1735 .cmd_rcgr_reg = CSI1_CMD_RCGR,
1736 .set_rate = set_rate_hid,
1737 .freq_tbl = ftbl_camss_csi0_1_clk,
1738 .current_freq = &rcg_dummy_freq,
1739 .base = &virt_bases[MMSS_BASE],
1740 .c = {
1741 .dbg_name = "csi1_clk_src",
1742 .ops = &clk_ops_rcg,
1743 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1744 CLK_INIT(csi1_clk_src.c),
1745 },
1746};
1747
1748static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = {
1749 F_MMSS( 37500000, gpll0, 16, 0, 0),
1750 F_MMSS( 50000000, gpll0, 12, 0, 0),
1751 F_MMSS( 60000000, gpll0, 10, 0, 0),
1752 F_MMSS( 80000000, gpll0, 7.5, 0, 0),
1753 F_MMSS( 100000000, gpll0, 6, 0, 0),
1754 F_MMSS( 109090000, gpll0, 5.5, 0, 0),
1755 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1756 F_MMSS( 200000000, gpll0, 3, 0, 0),
1757 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1758 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1759 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1760 F_END
1761};
1762
1763static struct rcg_clk vfe0_clk_src = {
1764 .cmd_rcgr_reg = VFE0_CMD_RCGR,
1765 .set_rate = set_rate_hid,
1766 .freq_tbl = ftbl_camss_vfe_vfe0_clk,
1767 .current_freq = &rcg_dummy_freq,
1768 .base = &virt_bases[MMSS_BASE],
1769 .c = {
1770 .dbg_name = "vfe0_clk_src",
1771 .ops = &clk_ops_rcg,
1772 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1773 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1774 CLK_INIT(vfe0_clk_src.c),
1775 },
1776};
1777
1778static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = {
1779 F_MMSS( 37500000, gpll0, 16, 0, 0),
1780 F_MMSS( 60000000, gpll0, 10, 0, 0),
1781 F_MMSS( 75000000, gpll0, 8, 0, 0),
1782 F_MMSS( 92310000, gpll0, 6.5, 0, 0),
1783 F_MMSS( 100000000, gpll0, 6, 0, 0),
1784 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
1785 F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0),
1786 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1787 F_END
1788};
1789
1790static struct rcg_clk mdp_clk_src = {
1791 .cmd_rcgr_reg = MDP_CMD_RCGR,
1792 .set_rate = set_rate_hid,
1793 .freq_tbl = ftbl_mdss_mdp_clk,
1794 .current_freq = &rcg_dummy_freq,
1795 .base = &virt_bases[MMSS_BASE],
1796 .c = {
1797 .dbg_name = "mdp_clk_src",
1798 .ops = &clk_ops_rcg,
1799 VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1800 200000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1801 CLK_INIT(mdp_clk_src.c),
1802 },
1803};
1804
1805static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = {
1806 F_MMSS( 75000000, gpll0, 8, 0, 0),
1807 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1808 F_MMSS( 200000000, gpll0, 3, 0, 0),
1809 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1810 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1811 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1812 F_END
1813};
1814
1815static struct rcg_clk jpeg0_clk_src = {
1816 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1817 .set_rate = set_rate_hid,
1818 .freq_tbl = ftbl_camss_jpeg_jpeg0_clk,
1819 .current_freq = &rcg_dummy_freq,
1820 .base = &virt_bases[MMSS_BASE],
1821 .c = {
1822 .dbg_name = "jpeg0_clk_src",
1823 .ops = &clk_ops_rcg,
1824 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1825 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1826 CLK_INIT(jpeg0_clk_src.c),
1827 },
1828};
1829
1830static struct clk_freq_tbl ftbl_mdss_pclk0_clk[] = {
1831 F_MDSS( 83000000, dsipll_667, 8, 0, 0),
1832 F_MDSS( 166000000, dsipll_667, 4, 0, 0),
1833 F_END
1834};
1835
1836static struct rcg_clk pclk0_clk_src = {
1837 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
1838 .set_rate = set_rate_mnd,
1839 .freq_tbl = ftbl_mdss_pclk0_clk,
1840 .current_freq = &rcg_dummy_freq,
1841 .base = &virt_bases[MMSS_BASE],
1842 .c = {
1843 .dbg_name = "pclk0_clk_src",
1844 .ops = &clk_ops_rcg_mnd,
1845 VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000),
1846 CLK_INIT(pclk0_clk_src.c),
1847 },
1848};
1849
1850static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = {
1851 F_MMSS( 66700000, gpll0, 9, 0, 0),
1852 F_MMSS( 100000000, gpll0, 6, 0, 0),
1853 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]1854 F_MMSS( 160000000, mmpll0_pll, 5, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1855 F_END
1856};
1857
1858static struct rcg_clk vcodec0_clk_src = {
1859 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
1860 .set_rate = set_rate_mnd,
1861 .freq_tbl = ftbl_venus0_vcodec0_clk,
1862 .current_freq = &rcg_dummy_freq,
1863 .base = &virt_bases[MMSS_BASE],
1864 .c = {
1865 .dbg_name = "vcodec0_clk_src",
1866 .ops = &clk_ops_rcg_mnd,
1867 VDD_DIG_FMAX_MAP3(LOW, 66670000, NOMINAL, 133330000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1868 160000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1869 CLK_INIT(vcodec0_clk_src.c),
1870 },
1871};
1872
1873static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = {
1874 F_MMSS( 19200000, xo, 1, 0, 0),
1875 F_END
1876};
1877
1878static struct rcg_clk cci_clk_src = {
1879 .cmd_rcgr_reg = CCI_CMD_RCGR,
1880 .set_rate = set_rate_mnd,
1881 .freq_tbl = ftbl_camss_cci_cci_clk,
1882 .current_freq = &rcg_dummy_freq,
1883 .base = &virt_bases[MMSS_BASE],
1884 .c = {
1885 .dbg_name = "cci_clk_src",
1886 .ops = &clk_ops_rcg_mnd,
1887 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
1888 CLK_INIT(cci_clk_src.c),
1889 },
1890};
1891
1892static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = {
1893 F_MMSS( 10000, xo, 16, 1, 120),
1894 F_MMSS( 24000, xo, 16, 1, 50),
1895 F_MMSS( 6000000, gpll0, 10, 1, 10),
1896 F_MMSS( 12000000, gpll0, 10, 1, 5),
1897 F_MMSS( 13000000, gpll0, 4, 13, 150),
1898 F_MMSS( 24000000, gpll0, 5, 1, 5),
1899 F_END
1900};
1901
1902static struct rcg_clk mmss_gp0_clk_src = {
1903 .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR,
1904 .set_rate = set_rate_mnd,
1905 .freq_tbl = ftbl_camss_gp0_1_clk,
1906 .current_freq = &rcg_dummy_freq,
1907 .base = &virt_bases[MMSS_BASE],
1908 .c = {
1909 .dbg_name = "mmss_gp0_clk_src",
1910 .ops = &clk_ops_rcg_mnd,
1911 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1912 CLK_INIT(mmss_gp0_clk_src.c),
1913 },
1914};
1915
1916static struct rcg_clk mmss_gp1_clk_src = {
1917 .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR,
1918 .set_rate = set_rate_mnd,
1919 .freq_tbl = ftbl_camss_gp0_1_clk,
1920 .current_freq = &rcg_dummy_freq,
1921 .base = &virt_bases[MMSS_BASE],
1922 .c = {
1923 .dbg_name = "mmss_gp1_clk_src",
1924 .ops = &clk_ops_rcg_mnd,
1925 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1926 CLK_INIT(mmss_gp1_clk_src.c),
1927 },
1928};
1929
1930static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = {
1931 F_MMSS( 66670000, gpll0, 9, 0, 0),
1932 F_END
1933};
1934
1935static struct rcg_clk mclk0_clk_src = {
1936 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1937 .set_rate = set_rate_mnd,
1938 .freq_tbl = ftbl_camss_mclk0_1_clk,
1939 .current_freq = &rcg_dummy_freq,
1940 .base = &virt_bases[MMSS_BASE],
1941 .c = {
1942 .dbg_name = "mclk0_clk_src",
1943 .ops = &clk_ops_rcg_mnd,
1944 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1945 CLK_INIT(mclk0_clk_src.c),
1946 },
1947};
1948
1949static struct rcg_clk mclk1_clk_src = {
1950 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1951 .set_rate = set_rate_mnd,
1952 .freq_tbl = ftbl_camss_mclk0_1_clk,
1953 .current_freq = &rcg_dummy_freq,
1954 .base = &virt_bases[MMSS_BASE],
1955 .c = {
1956 .dbg_name = "mclk1_clk_src",
1957 .ops = &clk_ops_rcg_mnd,
1958 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1959 CLK_INIT(mclk1_clk_src.c),
1960 },
1961};
1962
1963static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = {
1964 F_MMSS( 100000000, gpll0, 6, 0, 0),
1965 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1966 F_END
1967};
1968
1969static struct rcg_clk csi0phytimer_clk_src = {
1970 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1971 .set_rate = set_rate_hid,
1972 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
1973 .current_freq = &rcg_dummy_freq,
1974 .base = &virt_bases[MMSS_BASE],
1975 .c = {
1976 .dbg_name = "csi0phytimer_clk_src",
1977 .ops = &clk_ops_rcg,
1978 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1979 CLK_INIT(csi0phytimer_clk_src.c),
1980 },
1981};
1982
1983static struct rcg_clk csi1phytimer_clk_src = {
1984 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1985 .set_rate = set_rate_hid,
1986 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
1987 .current_freq = &rcg_dummy_freq,
1988 .base = &virt_bases[MMSS_BASE],
1989 .c = {
1990 .dbg_name = "csi1phytimer_clk_src",
1991 .ops = &clk_ops_rcg,
1992 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1993 CLK_INIT(csi1phytimer_clk_src.c),
1994 },
1995};
1996
1997static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = {
1998 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1999 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
2000 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
2001 F_END
2002};
2003
2004static struct rcg_clk cpp_clk_src = {
2005 .cmd_rcgr_reg = CPP_CMD_RCGR,
2006 .set_rate = set_rate_hid,
2007 .freq_tbl = ftbl_camss_vfe_cpp_clk,
2008 .current_freq = &rcg_dummy_freq,
2009 .base = &virt_bases[MMSS_BASE],
2010 .c = {
2011 .dbg_name = "cpp_clk_src",
2012 .ops = &clk_ops_rcg,
2013 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]2014 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2015 CLK_INIT(cpp_clk_src.c),
2016 },
2017};
2018
2019static struct clk_freq_tbl ftbl_mdss_byte0_clk[] = {
2020 F_MDSS( 62500000, dsipll_750, 12, 0, 0),
2021 F_MDSS( 125000000, dsipll_750, 6, 0, 0),
2022 F_END
2023};
2024
2025static struct rcg_clk byte0_clk_src = {
2026 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
2027 .set_rate = set_rate_hid,
2028 .freq_tbl = ftbl_mdss_byte0_clk,
2029 .current_freq = &rcg_dummy_freq,
2030 .base = &virt_bases[MMSS_BASE],
2031 .c = {
2032 .dbg_name = "byte0_clk_src",
2033 .ops = &clk_ops_rcg,
2034 VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000),
2035 CLK_INIT(byte0_clk_src.c),
2036 },
2037};
2038
2039static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = {
2040 F_MDSS( 19200000, xo, 1, 0, 0),
2041 F_END
2042};
2043
2044static struct rcg_clk esc0_clk_src = {
2045 .cmd_rcgr_reg = ESC0_CMD_RCGR,
2046 .set_rate = set_rate_hid,
2047 .freq_tbl = ftbl_mdss_esc0_clk,
2048 .current_freq = &rcg_dummy_freq,
2049 .base = &virt_bases[MMSS_BASE],
2050 .c = {
2051 .dbg_name = "esc0_clk_src",
2052 .ops = &clk_ops_rcg,
2053 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2054 CLK_INIT(esc0_clk_src.c),
2055 },
2056};
2057
2058static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
2059 F_MDSS( 19200000, xo, 1, 0, 0),
2060 F_END
2061};
2062
2063static struct rcg_clk vsync_clk_src = {
2064 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
2065 .set_rate = set_rate_hid,
2066 .freq_tbl = ftbl_mdss_vsync_clk,
2067 .current_freq = &rcg_dummy_freq,
2068 .base = &virt_bases[MMSS_BASE],
2069 .c = {
2070 .dbg_name = "vsync_clk_src",
2071 .ops = &clk_ops_rcg,
2072 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2073 CLK_INIT(vsync_clk_src.c),
2074 },
2075};
2076
2077static struct branch_clk camss_cci_cci_ahb_clk = {
2078 .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
2079 .has_sibling = 1,
2080 .base = &virt_bases[MMSS_BASE],
2081 .c = {
2082 .dbg_name = "camss_cci_cci_ahb_clk",
2083 .ops = &clk_ops_branch,
2084 CLK_INIT(camss_cci_cci_ahb_clk.c),
2085 },
2086};
2087
2088static struct branch_clk camss_cci_cci_clk = {
2089 .cbcr_reg = CAMSS_CCI_CCI_CBCR,
2090 .has_sibling = 0,
2091 .base = &virt_bases[MMSS_BASE],
2092 .c = {
2093 .dbg_name = "camss_cci_cci_clk",
2094 .parent = &cci_clk_src.c,
2095 .ops = &clk_ops_branch,
2096 CLK_INIT(camss_cci_cci_clk.c),
2097 },
2098};
2099
2100static struct branch_clk camss_csi0_ahb_clk = {
2101 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2102 .has_sibling = 1,
2103 .base = &virt_bases[MMSS_BASE],
2104 .c = {
2105 .dbg_name = "camss_csi0_ahb_clk",
2106 .ops = &clk_ops_branch,
2107 CLK_INIT(camss_csi0_ahb_clk.c),
2108 },
2109};
2110
2111static struct branch_clk camss_csi0_clk = {
2112 .cbcr_reg = CAMSS_CSI0_CBCR,
2113 .has_sibling = 1,
2114 .base = &virt_bases[MMSS_BASE],
2115 .c = {
2116 .dbg_name = "camss_csi0_clk",
2117 .parent = &csi0_clk_src.c,
2118 .ops = &clk_ops_branch,
2119 CLK_INIT(camss_csi0_clk.c),
2120 },
2121};
2122
2123static struct branch_clk camss_csi0phy_clk = {
2124 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2125 .has_sibling = 1,
2126 .base = &virt_bases[MMSS_BASE],
2127 .c = {
2128 .dbg_name = "camss_csi0phy_clk",
2129 .parent = &csi0_clk_src.c,
2130 .ops = &clk_ops_branch,
2131 CLK_INIT(camss_csi0phy_clk.c),
2132 },
2133};
2134
2135static struct branch_clk camss_csi0pix_clk = {
2136 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2137 .has_sibling = 1,
2138 .base = &virt_bases[MMSS_BASE],
2139 .c = {
2140 .dbg_name = "camss_csi0pix_clk",
2141 .parent = &csi0_clk_src.c,
2142 .ops = &clk_ops_branch,
2143 CLK_INIT(camss_csi0pix_clk.c),
2144 },
2145};
2146
2147static struct branch_clk camss_csi0rdi_clk = {
2148 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2149 .has_sibling = 1,
2150 .base = &virt_bases[MMSS_BASE],
2151 .c = {
2152 .dbg_name = "camss_csi0rdi_clk",
2153 .parent = &csi0_clk_src.c,
2154 .ops = &clk_ops_branch,
2155 CLK_INIT(camss_csi0rdi_clk.c),
2156 },
2157};
2158
2159static struct branch_clk camss_csi1_ahb_clk = {
2160 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2161 .has_sibling = 1,
2162 .base = &virt_bases[MMSS_BASE],
2163 .c = {
2164 .dbg_name = "camss_csi1_ahb_clk",
2165 .ops = &clk_ops_branch,
2166 CLK_INIT(camss_csi1_ahb_clk.c),
2167 },
2168};
2169
2170static struct branch_clk camss_csi1_clk = {
2171 .cbcr_reg = CAMSS_CSI1_CBCR,
2172 .has_sibling = 1,
2173 .base = &virt_bases[MMSS_BASE],
2174 .c = {
2175 .dbg_name = "camss_csi1_clk",
2176 .parent = &csi1_clk_src.c,
2177 .ops = &clk_ops_branch,
2178 CLK_INIT(camss_csi1_clk.c),
2179 },
2180};
2181
2182static struct branch_clk camss_csi1phy_clk = {
2183 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2184 .has_sibling = 1,
2185 .base = &virt_bases[MMSS_BASE],
2186 .c = {
2187 .dbg_name = "camss_csi1phy_clk",
2188 .parent = &csi1_clk_src.c,
2189 .ops = &clk_ops_branch,
2190 CLK_INIT(camss_csi1phy_clk.c),
2191 },
2192};
2193
2194static struct branch_clk camss_csi1pix_clk = {
2195 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2196 .has_sibling = 1,
2197 .base = &virt_bases[MMSS_BASE],
2198 .c = {
2199 .dbg_name = "camss_csi1pix_clk",
2200 .parent = &csi1_clk_src.c,
2201 .ops = &clk_ops_branch,
2202 CLK_INIT(camss_csi1pix_clk.c),
2203 },
2204};
2205
2206static struct branch_clk camss_csi1rdi_clk = {
2207 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2208 .has_sibling = 1,
2209 .base = &virt_bases[MMSS_BASE],
2210 .c = {
2211 .dbg_name = "camss_csi1rdi_clk",
2212 .parent = &csi1_clk_src.c,
2213 .ops = &clk_ops_branch,
2214 CLK_INIT(camss_csi1rdi_clk.c),
2215 },
2216};
2217
2218static struct branch_clk camss_csi_vfe0_clk = {
2219 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2220 .has_sibling = 1,
2221 .base = &virt_bases[MMSS_BASE],
2222 .c = {
2223 .dbg_name = "camss_csi_vfe0_clk",
2224 .parent = &vfe0_clk_src.c,
2225 .ops = &clk_ops_branch,
2226 CLK_INIT(camss_csi_vfe0_clk.c),
2227 },
2228};
2229
2230static struct branch_clk camss_gp0_clk = {
2231 .cbcr_reg = CAMSS_GP0_CBCR,
2232 .has_sibling = 0,
2233 .base = &virt_bases[MMSS_BASE],
2234 .c = {
2235 .dbg_name = "camss_gp0_clk",
2236 .parent = &mmss_gp0_clk_src.c,
2237 .ops = &clk_ops_branch,
2238 CLK_INIT(camss_gp0_clk.c),
2239 },
2240};
2241
2242static struct branch_clk camss_gp1_clk = {
2243 .cbcr_reg = CAMSS_GP1_CBCR,
2244 .has_sibling = 0,
2245 .base = &virt_bases[MMSS_BASE],
2246 .c = {
2247 .dbg_name = "camss_gp1_clk",
2248 .parent = &mmss_gp1_clk_src.c,
2249 .ops = &clk_ops_branch,
2250 CLK_INIT(camss_gp1_clk.c),
2251 },
2252};
2253
2254static struct branch_clk camss_ispif_ahb_clk = {
2255 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2256 .has_sibling = 1,
2257 .base = &virt_bases[MMSS_BASE],
2258 .c = {
2259 .dbg_name = "camss_ispif_ahb_clk",
2260 .ops = &clk_ops_branch,
2261 CLK_INIT(camss_ispif_ahb_clk.c),
2262 },
2263};
2264
2265static struct branch_clk camss_jpeg_jpeg0_clk = {
2266 .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
2267 .has_sibling = 0,
2268 .base = &virt_bases[MMSS_BASE],
2269 .c = {
2270 .dbg_name = "camss_jpeg_jpeg0_clk",
2271 .parent = &jpeg0_clk_src.c,
2272 .ops = &clk_ops_branch,
2273 CLK_INIT(camss_jpeg_jpeg0_clk.c),
2274 },
2275};
2276
2277static struct branch_clk camss_jpeg_jpeg_ahb_clk = {
2278 .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
2279 .has_sibling = 1,
2280 .base = &virt_bases[MMSS_BASE],
2281 .c = {
2282 .dbg_name = "camss_jpeg_jpeg_ahb_clk",
2283 .ops = &clk_ops_branch,
2284 CLK_INIT(camss_jpeg_jpeg_ahb_clk.c),
2285 },
2286};
2287
2288static struct branch_clk camss_jpeg_jpeg_axi_clk = {
2289 .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
2290 .has_sibling = 1,
2291 .base = &virt_bases[MMSS_BASE],
2292 .c = {
2293 .dbg_name = "camss_jpeg_jpeg_axi_clk",
2294 .parent = &axi_clk_src.c,
2295 .ops = &clk_ops_branch,
2296 CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
2297 },
2298};
2299
2300static struct branch_clk camss_mclk0_clk = {
2301 .cbcr_reg = CAMSS_MCLK0_CBCR,
2302 .has_sibling = 0,
2303 .base = &virt_bases[MMSS_BASE],
2304 .c = {
2305 .dbg_name = "camss_mclk0_clk",
2306 .parent = &mclk0_clk_src.c,
2307 .ops = &clk_ops_branch,
2308 CLK_INIT(camss_mclk0_clk.c),
2309 },
2310};
2311
2312static struct branch_clk camss_mclk1_clk = {
2313 .cbcr_reg = CAMSS_MCLK1_CBCR,
2314 .has_sibling = 0,
2315 .base = &virt_bases[MMSS_BASE],
2316 .c = {
2317 .dbg_name = "camss_mclk1_clk",
2318 .parent = &mclk1_clk_src.c,
2319 .ops = &clk_ops_branch,
2320 CLK_INIT(camss_mclk1_clk.c),
2321 },
2322};
2323
2324static struct branch_clk camss_micro_ahb_clk = {
2325 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2326 .has_sibling = 1,
2327 .base = &virt_bases[MMSS_BASE],
2328 .c = {
2329 .dbg_name = "camss_micro_ahb_clk",
2330 .ops = &clk_ops_branch,
2331 CLK_INIT(camss_micro_ahb_clk.c),
2332 },
2333};
2334
2335static struct branch_clk camss_phy0_csi0phytimer_clk = {
2336 .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
2337 .has_sibling = 0,
2338 .base = &virt_bases[MMSS_BASE],
2339 .c = {
2340 .dbg_name = "camss_phy0_csi0phytimer_clk",
2341 .parent = &csi0phytimer_clk_src.c,
2342 .ops = &clk_ops_branch,
2343 CLK_INIT(camss_phy0_csi0phytimer_clk.c),
2344 },
2345};
2346
2347static struct branch_clk camss_phy1_csi1phytimer_clk = {
2348 .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
2349 .has_sibling = 0,
2350 .base = &virt_bases[MMSS_BASE],
2351 .c = {
2352 .dbg_name = "camss_phy1_csi1phytimer_clk",
2353 .parent = &csi1phytimer_clk_src.c,
2354 .ops = &clk_ops_branch,
2355 CLK_INIT(camss_phy1_csi1phytimer_clk.c),
2356 },
2357};
2358
2359static struct branch_clk camss_top_ahb_clk = {
2360 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2361 .has_sibling = 1,
2362 .base = &virt_bases[MMSS_BASE],
2363 .c = {
2364 .dbg_name = "camss_top_ahb_clk",
2365 .ops = &clk_ops_branch,
2366 CLK_INIT(camss_top_ahb_clk.c),
2367 },
2368};
2369
2370static struct branch_clk camss_vfe_cpp_ahb_clk = {
2371 .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
2372 .has_sibling = 1,
2373 .base = &virt_bases[MMSS_BASE],
2374 .c = {
2375 .dbg_name = "camss_vfe_cpp_ahb_clk",
2376 .ops = &clk_ops_branch,
2377 CLK_INIT(camss_vfe_cpp_ahb_clk.c),
2378 },
2379};
2380
2381static struct branch_clk camss_vfe_cpp_clk = {
2382 .cbcr_reg = CAMSS_VFE_CPP_CBCR,
2383 .has_sibling = 0,
2384 .base = &virt_bases[MMSS_BASE],
2385 .c = {
2386 .dbg_name = "camss_vfe_cpp_clk",
2387 .parent = &cpp_clk_src.c,
2388 .ops = &clk_ops_branch,
2389 CLK_INIT(camss_vfe_cpp_clk.c),
2390 },
2391};
2392
2393static struct branch_clk camss_vfe_vfe0_clk = {
2394 .cbcr_reg = CAMSS_VFE_VFE0_CBCR,
2395 .has_sibling = 1,
2396 .base = &virt_bases[MMSS_BASE],
2397 .c = {
2398 .dbg_name = "camss_vfe_vfe0_clk",
2399 .parent = &vfe0_clk_src.c,
2400 .ops = &clk_ops_branch,
2401 CLK_INIT(camss_vfe_vfe0_clk.c),
2402 },
2403};
2404
2405static struct branch_clk camss_vfe_vfe_ahb_clk = {
2406 .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
2407 .has_sibling = 1,
2408 .base = &virt_bases[MMSS_BASE],
2409 .c = {
2410 .dbg_name = "camss_vfe_vfe_ahb_clk",
2411 .ops = &clk_ops_branch,
2412 CLK_INIT(camss_vfe_vfe_ahb_clk.c),
2413 },
2414};
2415
2416static struct branch_clk camss_vfe_vfe_axi_clk = {
2417 .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
2418 .has_sibling = 1,
2419 .base = &virt_bases[MMSS_BASE],
2420 .c = {
2421 .dbg_name = "camss_vfe_vfe_axi_clk",
2422 .parent = &axi_clk_src.c,
2423 .ops = &clk_ops_branch,
2424 CLK_INIT(camss_vfe_vfe_axi_clk.c),
2425 },
2426};
2427
2428static struct branch_clk mdss_ahb_clk = {
2429 .cbcr_reg = MDSS_AHB_CBCR,
2430 .has_sibling = 1,
2431 .base = &virt_bases[MMSS_BASE],
2432 .c = {
2433 .dbg_name = "mdss_ahb_clk",
2434 .ops = &clk_ops_branch,
2435 CLK_INIT(mdss_ahb_clk.c),
2436 },
2437};
2438
2439static struct branch_clk mdss_axi_clk = {
2440 .cbcr_reg = MDSS_AXI_CBCR,
2441 .has_sibling = 1,
2442 .base = &virt_bases[MMSS_BASE],
2443 .c = {
2444 .dbg_name = "mdss_axi_clk",
2445 .parent = &axi_clk_src.c,
2446 .ops = &clk_ops_branch,
2447 CLK_INIT(mdss_axi_clk.c),
2448 },
2449};
2450
2451static struct branch_clk mdss_byte0_clk = {
2452 .cbcr_reg = MDSS_BYTE0_CBCR,
2453 .has_sibling = 0,
2454 .base = &virt_bases[MMSS_BASE],
2455 .c = {
2456 .dbg_name = "mdss_byte0_clk",
2457 .parent = &byte0_clk_src.c,
2458 .ops = &clk_ops_branch,
2459 CLK_INIT(mdss_byte0_clk.c),
2460 },
2461};
2462
2463static struct branch_clk mdss_esc0_clk = {
2464 .cbcr_reg = MDSS_ESC0_CBCR,
2465 .has_sibling = 0,
2466 .base = &virt_bases[MMSS_BASE],
2467 .c = {
2468 .dbg_name = "mdss_esc0_clk",
2469 .parent = &esc0_clk_src.c,
2470 .ops = &clk_ops_branch,
2471 CLK_INIT(mdss_esc0_clk.c),
2472 },
2473};
2474
2475static struct branch_clk mdss_mdp_clk = {
2476 .cbcr_reg = MDSS_MDP_CBCR,
2477 .has_sibling = 1,
2478 .base = &virt_bases[MMSS_BASE],
2479 .c = {
2480 .dbg_name = "mdss_mdp_clk",
2481 .parent = &mdp_clk_src.c,
2482 .ops = &clk_ops_branch,
2483 CLK_INIT(mdss_mdp_clk.c),
2484 },
2485};
2486
2487static struct branch_clk mdss_mdp_lut_clk = {
2488 .cbcr_reg = MDSS_MDP_LUT_CBCR,
2489 .has_sibling = 1,
2490 .base = &virt_bases[MMSS_BASE],
2491 .c = {
2492 .dbg_name = "mdss_mdp_lut_clk",
2493 .parent = &mdp_clk_src.c,
2494 .ops = &clk_ops_branch,
2495 CLK_INIT(mdss_mdp_lut_clk.c),
2496 },
2497};
2498
2499static struct branch_clk mdss_pclk0_clk = {
2500 .cbcr_reg = MDSS_PCLK0_CBCR,
2501 .has_sibling = 0,
2502 .base = &virt_bases[MMSS_BASE],
2503 .c = {
2504 .dbg_name = "mdss_pclk0_clk",
2505 .parent = &pclk0_clk_src.c,
2506 .ops = &clk_ops_branch,
2507 CLK_INIT(mdss_pclk0_clk.c),
2508 },
2509};
2510
2511static struct branch_clk mdss_vsync_clk = {
2512 .cbcr_reg = MDSS_VSYNC_CBCR,
2513 .has_sibling = 0,
2514 .base = &virt_bases[MMSS_BASE],
2515 .c = {
2516 .dbg_name = "mdss_vsync_clk",
2517 .parent = &vsync_clk_src.c,
2518 .ops = &clk_ops_branch,
2519 CLK_INIT(mdss_vsync_clk.c),
2520 },
2521};
2522
2523static struct branch_clk mmss_misc_ahb_clk = {
2524 .cbcr_reg = MMSS_MISC_AHB_CBCR,
2525 .has_sibling = 1,
2526 .base = &virt_bases[MMSS_BASE],
2527 .c = {
2528 .dbg_name = "mmss_misc_ahb_clk",
2529 .ops = &clk_ops_branch,
2530 CLK_INIT(mmss_misc_ahb_clk.c),
2531 },
2532};
2533
2534static struct branch_clk mmss_mmssnoc_ahb_clk = {
2535 .cbcr_reg = MMSS_MMSSNOC_AHB_CBCR,
2536 .has_sibling = 1,
2537 .base = &virt_bases[MMSS_BASE],
2538 .c = {
2539 .dbg_name = "mmss_mmssnoc_ahb_clk",
2540 .ops = &clk_ops_branch,
2541 CLK_INIT(mmss_mmssnoc_ahb_clk.c),
2542 },
2543};
2544
2545static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
2546 .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
2547 .has_sibling = 1,
2548 .base = &virt_bases[MMSS_BASE],
2549 .c = {
2550 .dbg_name = "mmss_mmssnoc_bto_ahb_clk",
2551 .ops = &clk_ops_branch,
2552 CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c),
2553 },
2554};
2555
2556static struct branch_clk mmss_mmssnoc_axi_clk = {
2557 .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
2558 .has_sibling = 1,
2559 .base = &virt_bases[MMSS_BASE],
2560 .c = {
2561 .dbg_name = "mmss_mmssnoc_axi_clk",
2562 .parent = &axi_clk_src.c,
2563 .ops = &clk_ops_branch,
2564 CLK_INIT(mmss_mmssnoc_axi_clk.c),
2565 },
2566};
2567
2568static struct branch_clk mmss_s0_axi_clk = {
2569 .cbcr_reg = MMSS_S0_AXI_CBCR,
2570 .has_sibling = 0,
2571 .max_div = 0,
2572 .base = &virt_bases[MMSS_BASE],
2573 .c = {
2574 .dbg_name = "mmss_s0_axi_clk",
2575 .parent = &axi_clk_src.c,
2576 .ops = &clk_ops_branch,
2577 CLK_INIT(mmss_s0_axi_clk.c),
2578 .depends = &mmss_mmssnoc_axi_clk.c,
2579 },
2580};
2581
2582static struct branch_clk ocmemcx_ahb_clk = {
2583 .cbcr_reg = OCMEMCX_AHB_CBCR,
2584 .has_sibling = 1,
2585 .base = &virt_bases[MMSS_BASE],
2586 .c = {
2587 .dbg_name = "ocmemcx_ahb_clk",
2588 .ops = &clk_ops_branch,
2589 CLK_INIT(ocmemcx_ahb_clk.c),
2590 },
2591};
2592
2593static struct branch_clk oxili_gfx3d_clk = {
2594 .cbcr_reg = OXILI_GFX3D_CBCR,
2595 .has_sibling = 1,
2596 .max_div = 0,
2597 .base = &virt_bases[MMSS_BASE],
2598 .c = {
2599 .dbg_name = "oxili_gfx3d_clk",
2600 .parent = &gfx3d_clk_src.c,
2601 .ops = &clk_ops_branch,
2602 CLK_INIT(oxili_gfx3d_clk.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2603 },
2604};
2605
2606static struct branch_clk oxilicx_ahb_clk = {
2607 .cbcr_reg = OXILICX_AHB_CBCR,
2608 .has_sibling = 1,
2609 .base = &virt_bases[MMSS_BASE],
2610 .c = {
2611 .dbg_name = "oxilicx_ahb_clk",
2612 .ops = &clk_ops_branch,
2613 CLK_INIT(oxilicx_ahb_clk.c),
2614 },
2615};
2616
2617static struct branch_clk oxilicx_axi_clk = {
2618 .cbcr_reg = OXILICX_AXI_CBCR,
2619 .has_sibling = 1,
2620 .base = &virt_bases[MMSS_BASE],
2621 .c = {
2622 .dbg_name = "oxilicx_axi_clk",
2623 .parent = &axi_clk_src.c,
2624 .ops = &clk_ops_branch,
2625 CLK_INIT(oxilicx_axi_clk.c),
2626 },
2627};
2628
2629static struct branch_clk venus0_ahb_clk = {
2630 .cbcr_reg = VENUS0_AHB_CBCR,
2631 .has_sibling = 1,
2632 .base = &virt_bases[MMSS_BASE],
2633 .c = {
2634 .dbg_name = "venus0_ahb_clk",
2635 .ops = &clk_ops_branch,
2636 CLK_INIT(venus0_ahb_clk.c),
2637 },
2638};
2639
2640static struct branch_clk venus0_axi_clk = {
2641 .cbcr_reg = VENUS0_AXI_CBCR,
2642 .has_sibling = 1,
2643 .base = &virt_bases[MMSS_BASE],
2644 .c = {
2645 .dbg_name = "venus0_axi_clk",
2646 .parent = &axi_clk_src.c,
2647 .ops = &clk_ops_branch,
2648 CLK_INIT(venus0_axi_clk.c),
2649 },
2650};
2651
2652static struct branch_clk venus0_vcodec0_clk = {
2653 .cbcr_reg = VENUS0_VCODEC0_CBCR,
2654 .has_sibling = 0,
2655 .base = &virt_bases[MMSS_BASE],
2656 .c = {
2657 .dbg_name = "venus0_vcodec0_clk",
2658 .parent = &vcodec0_clk_src.c,
2659 .ops = &clk_ops_branch,
2660 CLK_INIT(venus0_vcodec0_clk.c),
2661 },
2662};
2663
2664static struct measure_mux_entry measure_mux_MMSS[] = {
2665 { &mmss_mmssnoc_ahb_clk.c, MMSS_BASE, 0x0001 },
2666 { &mmss_mmssnoc_bto_ahb_clk.c, MMSS_BASE, 0x0002 },
2667 { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 },
2668 { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 },
2669 { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 },
2670 { &ocmemcx_ahb_clk.c, MMSS_BASE, 0x000a },
2671 { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b },
2672 { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c },
2673 { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d },
2674 { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e },
2675 { &venus0_axi_clk.c, MMSS_BASE, 0x000f },
2676 { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 },
2677 { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 },
2678 { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 },
2679 { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 },
2680 { &mdss_vsync_clk.c, MMSS_BASE, 0x001c },
2681 { &mdss_byte0_clk.c, MMSS_BASE, 0x001e },
2682 { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 },
2683 { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 },
2684 { &mdss_axi_clk.c, MMSS_BASE, 0x0024 },
2685 { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 },
2686 { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 },
2687 { &camss_gp0_clk.c, MMSS_BASE, 0x0027 },
2688 { &camss_gp1_clk.c, MMSS_BASE, 0x0028 },
2689 { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 },
2690 { &camss_mclk1_clk.c, MMSS_BASE, 0x002a },
2691 { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d },
2692 { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e },
2693 { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f },
2694 { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 },
2695 { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 },
2696 { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 },
2697 { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 },
2698 { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 },
2699 { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a },
2700 { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b },
2701 { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c },
2702 { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d },
2703 { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f },
2704 { &camss_csi0_clk.c, MMSS_BASE, 0x0041 },
2705 { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 },
2706 { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 },
2707 { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 },
2708 { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 },
2709 { &camss_csi1_clk.c, MMSS_BASE, 0x0046 },
2710 { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 },
2711 { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 },
2712 { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 },
2713 { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a },
2714 { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 },
2715 {&dummy_clk, N_BASES, 0x0000},
2716};
2717
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2718static struct branch_clk q6ss_ahb_lfabif_clk = {
2719 .cbcr_reg = Q6SS_AHB_LFABIF_CBCR,
2720 .has_sibling = 1,
2721 .base = &virt_bases[LPASS_BASE],
2722 .c = {
2723 .dbg_name = "q6ss_ahb_lfabif_clk",
2724 .ops = &clk_ops_branch,
2725 CLK_INIT(q6ss_ahb_lfabif_clk.c),
2726 },
2727};
2728
2729static struct branch_clk q6ss_ahbm_clk = {
2730 .cbcr_reg = Q6SS_AHBM_CBCR,
2731 .has_sibling = 1,
2732 .base = &virt_bases[LPASS_BASE],
2733 .c = {
2734 .dbg_name = "q6ss_ahbm_clk",
2735 .ops = &clk_ops_branch,
2736 CLK_INIT(q6ss_ahbm_clk.c),
2737 },
2738};
2739
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2740static struct branch_clk q6ss_xo_clk = {
2741 .cbcr_reg = Q6SS_XO_CBCR,
2742 .has_sibling = 1,
2743 .bcr_reg = Q6SS_BCR,
2744 .base = &virt_bases[LPASS_BASE],
2745 .c = {
2746 .dbg_name = "q6ss_xo_clk",
2747 .parent = &xo.c,
2748 .ops = &clk_ops_branch,
2749 CLK_INIT(q6ss_xo_clk.c),
2750 },
2751};
2752
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2753static struct measure_mux_entry measure_mux_LPASS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2754 { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d },
2755 { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2756 { &q6ss_xo_clk.c, LPASS_BASE, 0x002b },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2757 {&dummy_clk, N_BASES, 0x0000},
2758};
2759
2760
2761static DEFINE_CLK_MEASURE(apc0_m_clk);
2762static DEFINE_CLK_MEASURE(apc1_m_clk);
2763static DEFINE_CLK_MEASURE(apc2_m_clk);
2764static DEFINE_CLK_MEASURE(apc3_m_clk);
2765static DEFINE_CLK_MEASURE(l2_m_clk);
2766
2767static struct measure_mux_entry measure_mux_APSS[] = {
2768 {&apc0_m_clk, APCS_BASE, 0x00010},
2769 {&apc1_m_clk, APCS_BASE, 0x00114},
2770 {&apc2_m_clk, APCS_BASE, 0x00220},
2771 {&apc3_m_clk, APCS_BASE, 0x00324},
2772 {&l2_m_clk, APCS_BASE, 0x01000},
2773 {&dummy_clk, N_BASES, 0x0000}
2774};
2775
2776#define APCS_SH_PLL_MODE (0x000)
2777#define APCS_SH_PLL_L_VAL (0x004)
2778#define APCS_SH_PLL_M_VAL (0x008)
2779#define APCS_SH_PLL_N_VAL (0x00C)
2780#define APCS_SH_PLL_USER_CTL (0x010)
2781#define APCS_SH_PLL_CONFIG_CTL (0x014)
2782#define APCS_SH_PLL_STATUS (0x01C)
2783
2784enum vdd_sr2_pll_levels {
2785 VDD_SR2_PLL_OFF,
2786 VDD_SR2_PLL_ON,
2787 VDD_SR2_PLL_NUM
2788};
2789
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2790static struct regulator *vdd_sr2_reg;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2791static int set_vdd_sr2_pll(struct clk_vdd_class *vdd_class, int level)
2792{
2793 if (level == VDD_SR2_PLL_ON) {
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2794 return regulator_set_voltage(vdd_sr2_reg, 1800000,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2795 1800000);
2796 } else {
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2797 return regulator_set_voltage(vdd_sr2_reg, 0, 1800000);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2798 }
2799}
2800
2801static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll,
2802 VDD_SR2_PLL_NUM);
2803
2804static struct pll_freq_tbl apcs_pll_freq[] = {
2805 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
2806 F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0),
2807 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
2808 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
2809 PLL_F_END
2810};
2811
2812static struct pll_clk a7sspll = {
2813 .mode_reg = (void __iomem *)APCS_SH_PLL_MODE,
2814 .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL,
2815 .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL,
2816 .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL,
2817 .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL,
2818 .status_reg = (void __iomem *)APCS_SH_PLL_STATUS,
2819 .freq_tbl = apcs_pll_freq,
2820 .masks = {
2821 .vco_mask = BM(29, 28),
2822 .pre_div_mask = BIT(12),
2823 .post_div_mask = BM(9, 8),
2824 .mn_en_mask = BIT(24),
2825 .main_output_mask = BIT(0),
2826 },
2827 .base = &virt_bases[APCS_PLL_BASE],
2828 .c = {
2829 .dbg_name = "a7sspll",
2830 .ops = &clk_ops_sr2_pll,
2831 .vdd_class = &vdd_sr2_pll,
2832 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
2833 [VDD_SR2_PLL_ON] = ULONG_MAX,
2834 },
2835 .num_fmax = VDD_SR2_PLL_NUM,
2836 CLK_INIT(a7sspll.c),
2837 /*
2838 * Need to skip handoff of the acpu pll to avoid
2839 * turning off the pll when the cpu is using it
2840 */
2841 .flags = CLKFLAG_SKIP_HANDOFF,
2842 },
2843};
2844
2845static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
2846static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
2847static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
2848static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
2849static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
2850static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX);
2851
2852static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
2853static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
2854static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX);
2855static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX);
2856static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX);
2857static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
2858static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
2859
2860static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX);
2861
2862#ifdef CONFIG_DEBUG_FS
2863static int measure_clk_set_parent(struct clk *c, struct clk *parent)
2864{
2865 struct measure_clk *clk = to_measure_clk(c);
2866 unsigned long flags;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2867 u32 regval, clk_sel, found = 0;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2868 int i;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2869 static const struct measure_mux_entry *array[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2870 measure_mux_GCC,
2871 measure_mux_MMSS,
2872 measure_mux_LPASS,
2873 measure_mux_APSS,
2874 NULL
2875 };
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2876 const struct measure_mux_entry *mux = array[0];
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2877
2878 if (!parent)
2879 return -EINVAL;
2880
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2881 for (i = 0; array[i] && !found; i++) {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2882 for (mux = array[i]; mux->c != &dummy_clk; mux++)
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2883 if (mux->c == parent) {
2884 found = 1;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2885 break;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2886 }
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2887 }
2888
2889 if (mux->c == &dummy_clk)
2890 return -EINVAL;
2891
2892 spin_lock_irqsave(&local_clock_reg_lock, flags);
2893 /*
2894 * Program the test vector, measurement period (sample_ticks)
2895 * and scaling multiplier.
2896 */
2897 clk->sample_ticks = 0x10000;
2898 clk->multiplier = 1;
2899
2900 switch (mux->base) {
2901
2902 case GCC_BASE:
2903 writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2904 clk_sel = mux->debug_mux;
2905 break;
2906
2907 case MMSS_BASE:
2908 writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2909 clk_sel = 0x02C;
2910 regval = BVAL(11, 0, mux->debug_mux);
2911 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2912
2913 /* Activate debug clock output */
2914 regval |= BIT(16);
2915 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2916 break;
2917
2918 case LPASS_BASE:
2919 writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2920 clk_sel = 0x161;
2921 regval = BVAL(11, 0, mux->debug_mux);
2922 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2923
2924 /* Activate debug clock output */
2925 regval |= BIT(20);
2926 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2927 break;
2928
2929 case APCS_BASE:
2930 clk->multiplier = 4;
2931 clk_sel = 362;
2932 regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG));
2933 regval &= ~0xC0037335;
2934 /* configure a divider of 4 */
2935 regval = BVAL(31, 30, 0x3) | mux->debug_mux;
2936 writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG));
2937 break;
2938
2939 default:
2940 return -EINVAL;
2941 }
2942
2943 /* Set debug mux clock index */
2944 regval = BVAL(8, 0, clk_sel);
2945 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2946
2947 /* Activate debug clock output */
2948 regval |= BIT(16);
2949 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2950
2951 /* Make sure test vector is set before starting measurements. */
2952 mb();
2953 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2954
2955 return 0;
2956}
2957
2958/* Sample clock for 'ticks' reference clock ticks. */
2959static u32 run_measurement(unsigned ticks)
2960{
2961 /* Stop counters and set the XO4 counter start value. */
2962 writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2963
2964 /* Wait for timer to become ready. */
2965 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2966 BIT(25)) != 0)
2967 cpu_relax();
2968
2969 /* Run measurement and wait for completion. */
2970 writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2971 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2972 BIT(25)) == 0)
2973 cpu_relax();
2974
2975 /* Return measured ticks. */
2976 return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2977 BM(24, 0);
2978}
2979
2980/*
2981 * Perform a hardware rate measurement for a given clock.
2982 * FOR DEBUG USE ONLY: Measurements take ~15 ms!
2983 */
2984static unsigned long measure_clk_get_rate(struct clk *c)
2985{
2986 unsigned long flags;
2987 u32 gcc_xo4_reg_backup;
2988 u64 raw_count_short, raw_count_full;
2989 struct measure_clk *clk = to_measure_clk(c);
2990 unsigned ret;
2991
2992 ret = clk_prepare_enable(&xo.c);
2993 if (ret) {
2994 pr_warn("CXO clock failed to enable. Can't measure\n");
2995 return 0;
2996 }
2997
2998 spin_lock_irqsave(&local_clock_reg_lock, flags);
2999
3000 /* Enable CXO/4 and RINGOSC branch. */
3001 gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3002 writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3003
3004 /*
3005 * The ring oscillator counter will not reset if the measured clock
3006 * is not running. To detect this, run a short measurement before
3007 * the full measurement. If the raw results of the two are the same
3008 * then the clock must be off.
3009 */
3010
3011 /* Run a short measurement. (~1 ms) */
3012 raw_count_short = run_measurement(0x1000);
3013 /* Run a full measurement. (~14 ms) */
3014 raw_count_full = run_measurement(clk->sample_ticks);
3015
3016 writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3017
3018 /* Return 0 if the clock is off. */
3019 if (raw_count_full == raw_count_short) {
3020 ret = 0;
3021 } else {
3022 /* Compute rate in Hz. */
3023 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
3024 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
3025 ret = (raw_count_full * clk->multiplier);
3026 }
3027
3028 writel_relaxed(0x51A00, GCC_REG_BASE(PLLTEST_PAD_CFG));
3029 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3030
3031 clk_disable_unprepare(&xo.c);
3032
3033 return ret;
3034}
3035
3036#else /* !CONFIG_DEBUG_FS */
3037static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
3038{
3039 return -EINVAL;
3040}
3041
3042static unsigned long measure_clk_get_rate(struct clk *clk)
3043{
3044 return 0;
3045}
3046#endif /* CONFIG_DEBUG_FS */
3047
3048static struct clk_ops clk_ops_measure = {
3049 .set_parent = measure_clk_set_parent,
3050 .get_rate = measure_clk_get_rate,
3051};
3052
3053static struct measure_clk measure_clk = {
3054 .c = {
3055 .dbg_name = "measure_clk",
3056 .ops = &clk_ops_measure,
3057 CLK_INIT(measure_clk.c),
3058 },
3059 .multiplier = 1,
3060};
3061
3062static struct clk_lookup msm_clocks_8226[] = {
3063 /* Debug Clocks */
3064 CLK_LOOKUP("measure", measure_clk.c, "debug"),
3065 CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""),
3066 CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""),
3067 CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""),
3068 CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""),
3069 CLK_LOOKUP("l2_m_clk", l2_m_clk, ""),
3070
3071 /* PIL-LPASS */
3072 CLK_LOOKUP("xo", xo.c, "fe200000.qcom,lpass"),
3073 CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"),
3074 CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"),
3075 CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"),
3076 CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"),
3077
3078 /* PIL-MODEM */
3079 CLK_LOOKUP("xo", xo.c, "fc880000.qcom,mss"),
3080 CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"),
3081 CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
3082 CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
3083
3084 /* PIL-PRONTO */
3085 CLK_LOOKUP("xo", xo.c, "fb21b000.qcom,pronto"),
3086
3087 /* PIL-VENUS */
3088 CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"),
3089 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"),
3090 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3091 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"),
3092 CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3093
3094 /* ACPUCLOCK */
3095 CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
3096 CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
3097 CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
3098
3099 /* WCNSS CLOCKS */
3100 CLK_LOOKUP("xo", xo.c, "fb000000.qcom,wcnss-wlan"),
3101
3102 /* BUS DRIVER */
3103 CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"),
3104 CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"),
3105 CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"),
3106 CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"),
3107 CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"),
3108 CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"),
3109 CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"),
3110 CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"),
3111 CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""),
3112 CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"),
3113 CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"),
3114 CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3115 CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3116 CLK_LOOKUP("iface_clk", gcc_mmss_noc_cfg_ahb_clk.c, ""),
3117
3118 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tmc-etr"),
3119 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tpiu"),
3120 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-replicator"),
3121 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tmc-etf"),
3122 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-merg"),
3123 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-in0"),
3124 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-in1"),
3125 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-kpss"),
3126 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-mmss"),
3127 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-stm"),
3128 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm0"),
3129 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm1"),
3130 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm2"),
3131 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm3"),
3132
3133 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tmc-etr"),
3134 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tpiu"),
3135 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-replicator"),
3136 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tmc-etf"),
3137 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-merg"),
3138 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-in0"),
3139 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-in1"),
3140 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-kpss"),
3141 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-mmss"),
3142 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-stm"),
3143 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm0"),
3144 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm1"),
3145 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm2"),
3146 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm3"),
3147
3148 /* HSUSB-OTG Clocks */
3149 CLK_LOOKUP("xo", xo.c, "f9a55000.usb"),
3150 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
3151 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
3152
3153 /* SPS CLOCKS */
3154 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"),
3155 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"),
3156 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
3157 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
3158
3159 /* I2C Clocks */
3160 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"),
3161 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"),
3162
3163 /* lsuart-v14 Clocks */
3164 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"),
3165 CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),
3166
3167 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"),
3168 CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"),
3169
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]3170 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"),
3171 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3172
3173 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"),
3174 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"),
3175 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"),
3176 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "qseecom"),
3177
3178 /* SDCC */
3179 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"),
3180 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"),
3181 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
3182 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
3183
3184 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
3185 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
3186 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
3187 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
3188
3189 CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
3190 CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
3191
3192 CLK_LOOKUP("sleep_a_clk", gcc_usb2a_phy_sleep_clk.c, "msm_dwc3"),
3193 CLK_LOOKUP("ref_clk", diff_clk.c, "msm_dwc3"),
3194
3195
3196 CLK_LOOKUP("bus_clk", pnoc_clk.c, ""),
3197 CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""),
3198 CLK_LOOKUP("bus_clk", snoc_clk.c, ""),
3199 CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""),
3200 CLK_LOOKUP("bus_clk", cnoc_clk.c, ""),
3201 CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""),
3202 CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""),
3203 CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""),
3204 CLK_LOOKUP("bus_clk", bimc_clk.c, ""),
3205 CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""),
3206 CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
3207
3208 CLK_LOOKUP("gpll0", gpll0.c, ""),
3209 CLK_LOOKUP("gpll1", gpll1.c, ""),
3210 CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""),
3211 CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""),
3212 CLK_LOOKUP("mmpll2", mmpll2_pll.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3213
3214 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
3215 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
3216 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
3217 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, ""),
3218 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
3219 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
3220 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
3221 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
3222 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
3223 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
3224 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
3225 CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
3226 CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""),
3227 CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""),
3228 CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""),
3229 CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
3230 CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
3231 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""),
3232 CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""),
3233 CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
3234 CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
3235
3236 CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"),
3237 CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"),
3238 CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"),
3239 CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"),
3240 CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"),
3241 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"),
3242 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"),
3243 CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"),
3244
3245 /* Multimedia clocks */
3246 CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"),
3247 CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"),
3248 CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
3249 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "mdss_dsi_clk_ctrl"),
3250
3251 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "mdp.0"),
3252 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "mdp.0"),
3253 CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "mdp.0"),
3254 CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "mdp.0"),
3255 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "mdp.0"),
3256 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "mdp.0"),
3257
3258 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"),
3259 CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"),
3260
3261 /* MM sensor clocks */
3262 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6e.qcom,camera"),
3263 CLK_LOOKUP("cam_src_clk", mclk1_clk_src.c, "90.qcom,camera"),
3264 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6e.qcom,camera"),
3265 CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, "90.qcom,camera"),
3266
3267 /* CCI clocks */
3268 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3269 "fda0c000.qcom,cci"),
3270 CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c,
3271 "fda0c000.qcom,cci"),
3272 CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"),
3273 CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"),
3274
3275 /* CSIPHY clocks */
3276 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3277 "fda0ac00.qcom,csiphy"),
3278 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3279 "fda0ac00.qcom,csiphy"),
3280 CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c,
3281 "fda0ac00.qcom,csiphy"),
3282 CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c,
3283 "fda0ac00.qcom,csiphy"),
3284 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3285 "fda0b000.qcom,csiphy"),
3286 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3287 "fda0b000.qcom,csiphy"),
3288 CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c,
3289 "fda0b000.qcom,csiphy"),
3290 CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c,
3291 "fda0b000.qcom,csiphy"),
3292
3293 /* CSID clocks */
3294 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3295 "fda08000.qcom,csid"),
3296 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3297 "fda08000.qcom,csid"),
3298 CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c, "fda08000.qcom,csid"),
3299 CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c, "fda08000.qcom,csid"),
3300 CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c, "fda08000.qcom,csid"),
3301 CLK_LOOKUP("csi0_clk", camss_csi0_clk.c, "fda08000.qcom,csid"),
3302 CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c, "fda08000.qcom,csid"),
3303 CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c, "fda08000.qcom,csid"),
3304
3305 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3306 "fda08400.qcom,csid"),
3307 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3308 "fda08400.qcom,csid"),
3309 CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c, "fda08400.qcom,csid"),
3310 CLK_LOOKUP("csi1_ahb_clk", camss_csi1_ahb_clk.c, "fda08400.qcom,csid"),
3311 CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c, "fda08400.qcom,csid"),
3312 CLK_LOOKUP("csi1_src_clk", csi1_clk_src.c, "fda08400.qcom,csid"),
3313 CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c, "fda08400.qcom,csid"),
3314 CLK_LOOKUP("csi1_phy_clk", camss_csi1phy_clk.c, "fda08400.qcom,csid"),
3315 CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c, "fda08400.qcom,csid"),
3316 CLK_LOOKUP("csi1_pix_clk", camss_csi1pix_clk.c, "fda08400.qcom,csid"),
3317 CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c, "fda08400.qcom,csid"),
3318 CLK_LOOKUP("csi1_rdi_clk", camss_csi1rdi_clk.c, "fda08400.qcom,csid"),
3319
3320 /* ISPIF clocks */
3321 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3322 "fda0a000.qcom,ispif"),
3323 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3324 "fda0a000.qcom,ispif"),
3325
3326 /* VFE clocks */
3327 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3328 "fda10000.qcom,vfe"),
3329 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"),
3330 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3331 "fda10000.qcom,vfe"),
3332 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3333 "fda10000.qcom,vfe"),
3334 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"),
3335 CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"),
3336
3337 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c,
3338 "fda44000.qcom,iommu"),
3339 CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"),
3340 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"),
3341
3342 /* Jpeg Clocks */
3343 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"),
3344 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3345 "fda1c000.qcom,jpeg"),
3346 CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c,
3347 "fda1c000.qcom,jpeg"),
3348 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3349 "fda1c000.qcom,jpeg"),
3350
3351 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"),
3352 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3353 "fda64000.qcom,iommu"),
3354 CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c,
3355 "fda64000.qcom,iommu"),
3356
3357 /* KGSL Clocks */
3358 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"),
3359 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"),
liu zhongc45eb8b2013-02-21 11:50:24 -0800[diff] [blame]3360 CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c,
3361 "fdb00000.qcom,kgsl-3d0"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3362
3363 CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"),
3364 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"),
3365 CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"),
3366
3367 CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3368
3369 /* Venus Clocks */
3370 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"),
3371 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"),
3372 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"),
3373
3374 CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c,
3375 "fdc84000.qcom,iommu"),
3376 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"),
3377 CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"),
3378
3379 CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""),
3380 CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""),
3381 CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""),
3382
3383 CLK_LOOKUP("", mmss_mmssnoc_ahb_clk.c, ""),
3384 CLK_LOOKUP("", mmss_mmssnoc_bto_ahb_clk.c, ""),
3385 CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""),
3386 CLK_LOOKUP("", mmss_s0_axi_clk.c, ""),
3387 CLK_LOOKUP("", ocmemcx_ahb_clk.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3388};
3389
3390static struct clk_lookup msm_clocks_8226_rumi[] = {
3391 CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3392 CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3393 CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
3394 CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
3395 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
3396 CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
3397 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
3398 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
3399 CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
3400 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
3401};
3402
3403struct clock_init_data msm8226_rumi_clock_init_data __initdata = {
3404 .table = msm_clocks_8226_rumi,
3405 .size = ARRAY_SIZE(msm_clocks_8226_rumi),
3406};
3407
3408static struct pll_config_regs gpll0_regs __initdata = {
3409 .l_reg = (void __iomem *)GPLL0_L_VAL,
3410 .m_reg = (void __iomem *)GPLL0_M_VAL,
3411 .n_reg = (void __iomem *)GPLL0_N_VAL,
3412 .config_reg = (void __iomem *)GPLL0_USER_CTL,
3413 .mode_reg = (void __iomem *)GPLL0_MODE,
3414 .base = &virt_bases[GCC_BASE],
3415};
3416
3417/* GPLL0 at 600 MHz, main output enabled. */
3418static struct pll_config gpll0_config __initdata = {
3419 .l = 0x1f,
3420 .m = 0x1,
3421 .n = 0x4,
3422 .vco_val = 0x0,
3423 .vco_mask = BM(21, 20),
3424 .pre_div_val = 0x0,
3425 .pre_div_mask = BM(14, 12),
3426 .post_div_val = 0x0,
3427 .post_div_mask = BM(9, 8),
3428 .mn_ena_val = BIT(24),
3429 .mn_ena_mask = BIT(24),
3430 .main_output_val = BIT(0),
3431 .main_output_mask = BIT(0),
3432};
3433
3434static struct pll_config_regs gpll1_regs __initdata = {
3435 .l_reg = (void __iomem *)GPLL1_L_VAL,
3436 .m_reg = (void __iomem *)GPLL1_M_VAL,
3437 .n_reg = (void __iomem *)GPLL1_N_VAL,
3438 .config_reg = (void __iomem *)GPLL1_USER_CTL,
3439 .mode_reg = (void __iomem *)GPLL1_MODE,
3440 .base = &virt_bases[GCC_BASE],
3441};
3442
3443/* GPLL1 at 480 MHz, main output enabled. */
3444static struct pll_config gpll1_config __initdata = {
3445 .l = 0x19,
3446 .m = 0x0,
3447 .n = 0x1,
3448 .vco_val = 0x0,
3449 .vco_mask = BM(21, 20),
3450 .pre_div_val = 0x0,
3451 .pre_div_mask = BM(14, 12),
3452 .post_div_val = 0x0,
3453 .post_div_mask = BM(9, 8),
3454 .main_output_val = BIT(0),
3455 .main_output_mask = BIT(0),
3456};
3457
3458static struct pll_config_regs mmpll0_regs __initdata = {
3459 .l_reg = (void __iomem *)MMPLL0_PLL_L_VAL,
3460 .m_reg = (void __iomem *)MMPLL0_PLL_M_VAL,
3461 .n_reg = (void __iomem *)MMPLL0_PLL_N_VAL,
3462 .config_reg = (void __iomem *)MMPLL0_PLL_USER_CTL,
3463 .mode_reg = (void __iomem *)MMPLL0_PLL_MODE,
3464 .base = &virt_bases[MMSS_BASE],
3465};
3466
3467/* MMPLL0 at 800 MHz, main output enabled. */
3468static struct pll_config mmpll0_config __initdata = {
3469 .l = 0x29,
3470 .m = 0x2,
3471 .n = 0x3,
3472 .vco_val = 0x0,
3473 .vco_mask = BM(21, 20),
3474 .pre_div_val = 0x0,
3475 .pre_div_mask = BM(14, 12),
3476 .post_div_val = 0x0,
3477 .post_div_mask = BM(9, 8),
3478 .mn_ena_val = BIT(24),
3479 .mn_ena_mask = BIT(24),
3480 .main_output_val = BIT(0),
3481 .main_output_mask = BIT(0),
3482};
3483
3484static struct pll_config_regs mmpll1_regs __initdata = {
3485 .l_reg = (void __iomem *)MMPLL1_PLL_L_VAL,
3486 .m_reg = (void __iomem *)MMPLL1_PLL_M_VAL,
3487 .n_reg = (void __iomem *)MMPLL1_PLL_N_VAL,
3488 .config_reg = (void __iomem *)MMPLL1_PLL_USER_CTL,
3489 .mode_reg = (void __iomem *)MMPLL1_PLL_MODE,
3490 .base = &virt_bases[MMSS_BASE],
3491};
3492
3493/* MMPLL1 at 1000 MHz, main output enabled. */
3494static struct pll_config mmpll1_config __initdata = {
3495 .l = 0x2C,
3496 .m = 0x1,
3497 .n = 0x10,
3498 .vco_val = 0x0,
3499 .vco_mask = BM(21, 20),
3500 .pre_div_val = 0x0,
3501 .pre_div_mask = BM(14, 12),
3502 .post_div_val = 0x0,
3503 .post_div_mask = BM(9, 8),
3504 .mn_ena_val = BIT(24),
3505 .mn_ena_mask = BIT(24),
3506 .main_output_val = BIT(0),
3507 .main_output_mask = BIT(0),
3508};
3509
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3510#define PLL_AUX_OUTPUT_BIT 1
3511#define PLL_AUX2_OUTPUT_BIT 2
3512
3513#define PWR_ON_MASK BIT(31)
3514#define EN_REST_WAIT_MASK (0xF << 20)
3515#define EN_FEW_WAIT_MASK (0xF << 16)
3516#define CLK_DIS_WAIT_MASK (0xF << 12)
3517#define SW_OVERRIDE_MASK BIT(2)
3518#define HW_CONTROL_MASK BIT(1)
3519#define SW_COLLAPSE_MASK BIT(0)
3520
3521/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
3522#define EN_REST_WAIT_VAL (0x2 << 20)
3523#define EN_FEW_WAIT_VAL (0x2 << 16)
3524#define CLK_DIS_WAIT_VAL (0x2 << 12)
3525#define GDSC_TIMEOUT_US 50000
3526
3527#define PLL_OUTCTRL BIT(0)
3528#define PLL_BYPASSNL BIT(1)
3529#define PLL_RESET_N BIT(2)
3530#define PLL_LOCKED_BIT BIT(16)
3531#define ENABLE_WAIT_MAX_LOOPS 200
3532
3533static void __init reg_init(void)
3534{
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3535 u32 regval;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3536
3537 if (!(readl_relaxed(GCC_REG_BASE(GPLL0_STATUS))
3538 & gpll0.status_mask))
3539 configure_sr_hpm_lp_pll(&gpll0_config, &gpll0_regs, 1);
3540
3541 if (!(readl_relaxed(GCC_REG_BASE(GPLL1_STATUS))
3542 & gpll1.status_mask))
3543 configure_sr_hpm_lp_pll(&gpll1_config, &gpll1_regs, 1);
3544
3545 configure_sr_hpm_lp_pll(&mmpll0_config, &mmpll0_regs, 1);
3546 configure_sr_hpm_lp_pll(&mmpll1_config, &mmpll1_regs, 1);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3547
3548 /* Enable GPLL0's aux outputs. */
3549 regval = readl_relaxed(GCC_REG_BASE(GPLL0_USER_CTL));
3550 regval |= BIT(PLL_AUX_OUTPUT_BIT) | BIT(PLL_AUX2_OUTPUT_BIT);
3551 writel_relaxed(regval, GCC_REG_BASE(GPLL0_USER_CTL));
3552
3553 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
3554 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3555 regval |= BIT(0);
3556 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3557
3558 /*
3559 * TODO: Confirm that no clocks need to be voted on in this sleep vote
3560 * register.
3561 */
3562 writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3563}
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3564
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3565static void __init msm8226_clock_post_init(void)
3566{
3567
3568 /* Set rates for single-rate clocks. */
3569 clk_set_rate(&usb_hs_system_clk_src.c,
3570 usb_hs_system_clk_src.freq_tbl[0].freq_hz);
3571 clk_set_rate(&usb_hsic_clk_src.c,
3572 usb_hsic_clk_src.freq_tbl[0].freq_hz);
3573 clk_set_rate(&usb_hsic_io_cal_clk_src.c,
3574 usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz);
3575 clk_set_rate(&usb_hsic_system_clk_src.c,
3576 usb_hsic_system_clk_src.freq_tbl[0].freq_hz);
3577 clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz);
3578 clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz);
3579 clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz);
3580 clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz);
3581 clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz);
3582 clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3583}
3584
3585#define GCC_CC_PHYS 0xFC400000
3586#define GCC_CC_SIZE SZ_16K
3587
3588#define MMSS_CC_PHYS 0xFD8C0000
3589#define MMSS_CC_SIZE SZ_256K
3590
3591#define LPASS_CC_PHYS 0xFE000000
3592#define LPASS_CC_SIZE SZ_256K
3593
3594#define APCS_KPSS_SH_PLL_PHYS 0xF9016000
3595#define APCS_KPSS_SH_PLL_SIZE SZ_64
3596
3597#define APCS_KPSS_GLB_PHYS 0xF9011000
3598#define APCS_KPSS_GLB_SIZE SZ_4K
3599
3600
3601static void __init msm8226_clock_pre_init(void)
3602{
3603 virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE);
3604 if (!virt_bases[GCC_BASE])
3605 panic("clock-8226: Unable to ioremap GCC memory!");
3606
3607 virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE);
3608 if (!virt_bases[MMSS_BASE])
3609 panic("clock-8226: Unable to ioremap MMSS_CC memory!");
3610
3611 virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE);
3612 if (!virt_bases[LPASS_BASE])
3613 panic("clock-8226: Unable to ioremap LPASS_CC memory!");
3614
3615 virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS,
3616 APCS_KPSS_GLB_SIZE);
3617 if (!virt_bases[APCS_BASE])
3618 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3619
3620 virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS,
3621 APCS_KPSS_SH_PLL_SIZE);
3622 if (!virt_bases[APCS_PLL_BASE])
3623 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3624
3625 clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
3626
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3627 vdd_dig_reg = regulator_get(NULL, "vdd_dig");
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3628 if (IS_ERR(vdd_dig_reg))
3629 panic("clock-8226: Unable to get the vdd_dig regulator!");
3630
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3631 vdd_sr2_reg = regulator_get(NULL, "vdd_sr2_pll");
3632 if (IS_ERR(vdd_dig_reg))
3633 panic("clock-8226: Unable to get the sr2_pll regulator!");
3634
3635 /*
3636 * The SR2 PLL is used at boot. Vote to prevent its regulator from
3637 * being turned off while the PLL is still in use.
3638 */
3639 regulator_set_voltage(vdd_sr2_reg, 1800000, 1800000);
3640 regulator_enable(vdd_sr2_reg);
3641
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3642 /*
3643 * TODO: Set a voltage and enable vdd_dig, leaving the voltage high
3644 * until late_init. This may not be necessary with clock handoff;
3645 * Investigate this code on a real non-simulator target to determine
3646 * its necessity.
3647 */
3648 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3649 regulator_enable(vdd_dig_reg);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3650
3651 /*
3652 * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB
3653 * source. Sleep set vote is 0.
3654 * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to
3655 * access mmss clock controller registers.
3656 */
3657 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
3658 clk_prepare_enable(&mmssnoc_ahb_a_clk.c);
3659
3660 /*
3661 * Hold an active set vote for CXO; this is because CXO is expected
3662 * to remain on whenever CPUs aren't power collapsed.
3663 */
3664 clk_prepare_enable(&xo_a_clk.c);
3665
3666 enable_rpm_scaling();
3667
3668 reg_init();
3669 /*
3670 * FIXME remove after bus driver is in place
3671 * Requires gpll0 to be configured
3672 */
3673 clk_set_rate(&axi_clk_src.c, 200000000);
3674 clk_prepare_enable(&mmss_s0_axi_clk.c);
3675
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3676 /*
3677 * TODO: Enable the gcc_bimc_clk smcbc, which is the parent of thhe
3678 * mss_gcc_q6_bimc_axi_clk
3679 */
3680 writel_relaxed(0x1, GCC_REG_BASE(0x1118));
3681}
3682
3683static int __init msm8226_clock_late_init(void)
3684{
3685 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
3686}
3687
3688struct clock_init_data msm8226_clock_init_data __initdata = {
3689 .table = msm_clocks_8226,
3690 .size = ARRAY_SIZE(msm_clocks_8226),
3691 .pre_init = msm8226_clock_pre_init,
3692 .post_init = msm8226_clock_post_init,
3693 .late_init = msm8226_clock_late_init,
3694};