| Kuirong Wang | 265f359 | 2012-12-05 16:17:41 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <msm8x10_wcd_registers.h> |
| 14 | #include "msm8x10-wcd.h" |
| 15 | |
| 16 | const u8 msm8x10_wcd_reg_readable[MSM8X10_WCD_CACHE_SIZE] = { |
| 17 | [MSM8X10_WCD_A_CHIP_CTL] = 1, |
| 18 | [MSM8X10_WCD_A_CHIP_STATUS] = 1, |
| 19 | [MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT] = 1, |
| 20 | [MSM8X10_WCD_A_MODE_LOCK] = 0, |
| 21 | [MSM8X10_WCD_A_CHIP_ID_BYTE_0] = 1, |
| 22 | [MSM8X10_WCD_A_CHIP_ID_BYTE_1] = 1, |
| 23 | [MSM8X10_WCD_A_CHIP_ID_BYTE_2] = 1, |
| 24 | [MSM8X10_WCD_A_CHIP_ID_BYTE_3] = 1, |
| 25 | [MSM8X10_WCD_A_CHIP_VERSION] = 1, |
| 26 | [MSM8X10_WCD_A_ANALOG_SLAVE_ID] = 1, |
| 27 | [MSM8X10_WCD_A_PIN_CTL_OE] = 1, |
| 28 | [MSM8X10_WCD_A_PIN_CTL_DATA] = 1, |
| 29 | [MSM8X10_WCD_A_PIN_STATUS] = 1, |
| 30 | [MSM8X10_WCD_A_HDRIVE_CTL] = 1, |
| 31 | [MSM8X10_WCD_A_HDRIVE_I2C_CTL] = 1, |
| 32 | [MSM8X10_WCD_A_CDC_RST_CTL] = 1, |
| 33 | [MSM8X10_WCD_A_CDC_TOP_CLK_CTL] = 1, |
| 34 | [MSM8X10_WCD_A_CDC_ANA_CLK_CTL] = 1, |
| 35 | [MSM8X10_WCD_A_CDC_DIG_CLK_CTL] = 1, |
| 36 | [MSM8X10_WCD_A_PROCESS_MONITOR_CTL0] = 1, |
| 37 | [MSM8X10_WCD_A_PROCESS_MONITOR_CTL1] = 1, |
| 38 | [MSM8X10_WCD_A_PROCESS_MONITOR_CTL2] = 1, |
| 39 | [MSM8X10_WCD_A_PROCESS_MONITOR_CTL3] = 1, |
| 40 | [MSM8X10_WCD_A_QFUSE_CTL] = 1, |
| 41 | [MSM8X10_WCD_A_QFUSE_STATUS] = 1, |
| 42 | [MSM8X10_WCD_A_QFUSE_DATA_OUT0] = 1, |
| 43 | [MSM8X10_WCD_A_QFUSE_DATA_OUT1] = 1, |
| 44 | [MSM8X10_WCD_A_QFUSE_DATA_OUT2] = 1, |
| 45 | [MSM8X10_WCD_A_QFUSE_DATA_OUT3] = 1, |
| 46 | [MSM8X10_WCD_A_CDC_CONN_TX1_CTL] = 1, |
| 47 | [MSM8X10_WCD_A_CDC_CONN_TX2_CTL] = 1, |
| 48 | [MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL] = 1, |
| 49 | [MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL] = 1, |
| 50 | [MSM8X10_WCD_A_CDC_CONN_RX1_CTL] = 1, |
| 51 | [MSM8X10_WCD_A_CDC_CONN_RX2_CTL] = 1, |
| 52 | [MSM8X10_WCD_A_CDC_CONN_RX3_CTL] = 1, |
| 53 | [MSM8X10_WCD_A_DIGITAL_DEBUG_CTL] = 1, |
| 54 | [MSM8X10_WCD_A_ANALOG_DEBUG_CTL] = 1, |
| 55 | [MSM8X10_WCD_A_CDC_RX1_CTL] = 1, |
| 56 | [MSM8X10_WCD_A_CDC_RX2_CTL] = 1, |
| 57 | [MSM8X10_WCD_A_CDC_RX3_CTL] = 1, |
| 58 | [MSM8X10_WCD_A_DEM_BYPASS_DATA0] = 1, |
| 59 | [MSM8X10_WCD_A_DEM_BYPASS_DATA1] = 1, |
| 60 | [MSM8X10_WCD_A_DEM_BYPASS_DATA2] = 1, |
| 61 | [MSM8X10_WCD_A_DEM_BYPASS_DATA3] = 1, |
| 62 | [MSM8X10_WCD_A_SPARE_0] = 1, |
| 63 | [MSM8X10_WCD_A_SPARE_1] = 1, |
| 64 | [MSM8X10_WCD_A_SPARE_2] = 1, |
| 65 | [MSM8X10_WCD_A_INTR_MODE] = 1, |
| 66 | [MSM8X10_WCD_A_INTR_MASK0] = 1, |
| 67 | [MSM8X10_WCD_A_INTR_MASK1] = 1, |
| 68 | [MSM8X10_WCD_A_INTR_MASK2] = 1, |
| 69 | [MSM8X10_WCD_A_INTR_STATUS0] = 1, |
| 70 | [MSM8X10_WCD_A_INTR_STATUS1] = 1, |
| 71 | [MSM8X10_WCD_A_INTR_STATUS2] = 1, |
| 72 | [MSM8X10_WCD_A_INTR_CLEAR0] = 0, |
| 73 | [MSM8X10_WCD_A_INTR_CLEAR1] = 0, |
| 74 | [MSM8X10_WCD_A_INTR_CLEAR2] = 0, |
| 75 | [MSM8X10_WCD_A_INTR_TEST0] = 1, |
| 76 | [MSM8X10_WCD_A_INTR_TEST1] = 1, |
| 77 | [MSM8X10_WCD_A_INTR_TEST2] = 1, |
| 78 | [MSM8X10_WCD_A_INTR_SET0] = 1, |
| 79 | [MSM8X10_WCD_A_INTR_SET1] = 1, |
| 80 | [MSM8X10_WCD_A_INTR_SET2] = 1, |
| 81 | [MSM8X10_WCD_A_CDC_MBHC_EN_CTL] = 1, |
| 82 | [MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG] = 1, |
| 83 | [MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG] = 1, |
| 84 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL] = 1, |
| 85 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL] = 1, |
| 86 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL] = 1, |
| 87 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL] = 1, |
| 88 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL] = 1, |
| 89 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL] = 1, |
| 90 | [MSM8X10_WCD_A_CDC_MBHC_B1_STATUS] = 1, |
| 91 | [MSM8X10_WCD_A_CDC_MBHC_B2_STATUS] = 1, |
| 92 | [MSM8X10_WCD_A_CDC_MBHC_B3_STATUS] = 1, |
| 93 | [MSM8X10_WCD_A_CDC_MBHC_B4_STATUS] = 1, |
| 94 | [MSM8X10_WCD_A_CDC_MBHC_B5_STATUS] = 1, |
| 95 | [MSM8X10_WCD_A_CDC_MBHC_B1_CTL] = 1, |
| 96 | [MSM8X10_WCD_A_CDC_MBHC_B2_CTL] = 1, |
| 97 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL] = 1, |
| 98 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL] = 1, |
| 99 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL] = 1, |
| 100 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL] = 1, |
| 101 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL] = 1, |
| 102 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL] = 1, |
| 103 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL] = 1, |
| 104 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL] = 1, |
| 105 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL] = 1, |
| 106 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL] = 1, |
| 107 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL] = 1, |
| 108 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL] = 1, |
| 109 | [MSM8X10_WCD_A_CDC_MBHC_CLK_CTL] = 1, |
| 110 | [MSM8X10_WCD_A_CDC_MBHC_INT_CTL] = 1, |
| 111 | [MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL] = 1, |
| 112 | [MSM8X10_WCD_A_CDC_MBHC_SPARE] = 1, |
| 113 | [MSM8X10_WCD_A_BIAS_REF_CTL] = 1, |
| 114 | [MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL] = 1, |
| 115 | [MSM8X10_WCD_A_BIAS_PRECHRG_CTL] = 1, |
| 116 | [MSM8X10_WCD_A_BIAS_CURR_CTL_1] = 1, |
| 117 | [MSM8X10_WCD_A_BIAS_CURR_CTL_2] = 1, |
| 118 | [MSM8X10_WCD_A_BIAS_OSC_BG_CTL] = 1, |
| 119 | [MSM8X10_WCD_A_MICB_CFILT_1_CTL] = 1, |
| 120 | [MSM8X10_WCD_A_MICB_CFILT_1_VAL] = 1, |
| 121 | [MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG] = 1, |
| 122 | [MSM8X10_WCD_A_MICB_1_CTL] = 1, |
| 123 | [MSM8X10_WCD_A_MICB_1_INT_RBIAS] = 1, |
| 124 | [MSM8X10_WCD_A_MICB_1_MBHC] = 1, |
| 125 | [MSM8X10_WCD_A_MBHC_INSERT_DETECT] = 1, |
| 126 | [MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS] = 1, |
| 127 | [MSM8X10_WCD_A_TX_COM_BIAS] = 1, |
| 128 | [MSM8X10_WCD_A_MBHC_SCALING_MUX_1] = 1, |
| 129 | [MSM8X10_WCD_A_MBHC_SCALING_MUX_2] = 1, |
| 130 | [MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL] = 1, |
| 131 | [MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1] = 1, |
| 132 | [MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2] = 1, |
| 133 | [MSM8X10_WCD_A_TX_1_EN] = 1, |
| 134 | [MSM8X10_WCD_A_TX_2_EN] = 1, |
| 135 | [MSM8X10_WCD_A_TX_1_2_ADC_CH1] = 1, |
| 136 | [MSM8X10_WCD_A_TX_1_2_ADC_CH2] = 1, |
| 137 | [MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL] = 1, |
| 138 | [MSM8X10_WCD_A_TX_1_2_TEST_CTL] = 1, |
| 139 | [MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN] = 1, |
| 140 | [MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV] = 1, |
| 141 | [MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1] = 1, |
| 142 | [MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2] = 1, |
| 143 | [MSM8X10_WCD_A_TX_3_EN] = 1, |
| 144 | [MSM8X10_WCD_A_TX_1_2_TEST_EN] = 1, |
| 145 | [MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL] = 1, |
| 146 | [MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR] = 1, |
| 147 | [MSM8X10_WCD_A_CP_EN] = 1, |
| 148 | [MSM8X10_WCD_A_CP_CLK] = 1, |
| 149 | [MSM8X10_WCD_A_CP_STATIC] = 1, |
| 150 | [MSM8X10_WCD_A_CP_DCC1] = 1, |
| 151 | [MSM8X10_WCD_A_CP_DCC3] = 1, |
| 152 | [MSM8X10_WCD_A_CP_ATEST] = 1, |
| 153 | [MSM8X10_WCD_A_CP_DTEST] = 1, |
| 154 | [MSM8X10_WCD_A_RX_AUX_SW_CTL] = 1, |
| 155 | [MSM8X10_WCD_A_RX_PA_AUX_IN_CONN] = 1, |
| 156 | [MSM8X10_WCD_A_RX_COM_TIMER_DIV] = 1, |
| 157 | [MSM8X10_WCD_A_RX_COM_OCP_CTL] = 1, |
| 158 | [MSM8X10_WCD_A_RX_COM_OCP_COUNT] = 1, |
| 159 | [MSM8X10_WCD_A_RX_COM_DAC_CTL] = 1, |
| 160 | [MSM8X10_WCD_A_RX_COM_BIAS] = 1, |
| 161 | [MSM8X10_WCD_A_RX_HPH_AUTO_CHOP] = 1, |
| 162 | [MSM8X10_WCD_A_RX_HPH_CHOP_CTL] = 1, |
| 163 | [MSM8X10_WCD_A_RX_HPH_BIAS_PA] = 1, |
| 164 | [MSM8X10_WCD_A_RX_HPH_BIAS_LDO] = 1, |
| 165 | [MSM8X10_WCD_A_RX_HPH_BIAS_CNP] = 1, |
| 166 | [MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP] = 1, |
| 167 | [MSM8X10_WCD_A_RX_HPH_OCP_CTL] = 1, |
| 168 | [MSM8X10_WCD_A_RX_HPH_CNP_EN] = 1, |
| 169 | [MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL] = 1, |
| 170 | [MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME] = 1, |
| 171 | [MSM8X10_WCD_A_RX_HPH_L_GAIN] = 1, |
| 172 | [MSM8X10_WCD_A_RX_HPH_L_TEST] = 1, |
| 173 | [MSM8X10_WCD_A_RX_HPH_L_PA_CTL] = 1, |
| 174 | [MSM8X10_WCD_A_RX_HPH_L_DAC_CTL] = 1, |
| 175 | [MSM8X10_WCD_A_RX_HPH_L_ATEST] = 1, |
| 176 | [MSM8X10_WCD_A_RX_HPH_L_STATUS] = 1, |
| 177 | [MSM8X10_WCD_A_RX_HPH_R_GAIN] = 1, |
| 178 | [MSM8X10_WCD_A_RX_HPH_R_TEST] = 1, |
| 179 | [MSM8X10_WCD_A_RX_HPH_R_PA_CTL] = 1, |
| 180 | [MSM8X10_WCD_A_RX_HPH_R_DAC_CTL] = 1, |
| 181 | [MSM8X10_WCD_A_RX_HPH_R_ATEST] = 1, |
| 182 | [MSM8X10_WCD_A_RX_HPH_R_STATUS] = 1, |
| 183 | [MSM8X10_WCD_A_RX_EAR_BIAS_PA] = 1, |
| 184 | [MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF] = 1, |
| 185 | [MSM8X10_WCD_A_RX_EAR_EN] = 1, |
| 186 | [MSM8X10_WCD_A_RX_EAR_GAIN] = 1, |
| 187 | [MSM8X10_WCD_A_RX_EAR_CMBUFF] = 1, |
| 188 | [MSM8X10_WCD_A_RX_EAR_ICTL] = 1, |
| 189 | [MSM8X10_WCD_A_RX_EAR_CCOMP] = 1, |
| 190 | [MSM8X10_WCD_A_RX_EAR_VCM] = 1, |
| 191 | [MSM8X10_WCD_A_RX_EAR_CNP] = 1, |
| 192 | [MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST] = 1, |
| 193 | [MSM8X10_WCD_A_RX_EAR_STATUS] = 1, |
| 194 | [MSM8X10_WCD_A_RX_LINE_BIAS_PA] = 1, |
| 195 | [MSM8X10_WCD_A_RX_BUCK_BIAS1] = 1, |
| 196 | [MSM8X10_WCD_A_RX_BUCK_BIAS2] = 1, |
| 197 | [MSM8X10_WCD_A_RX_LINE_COM] = 1, |
| 198 | [MSM8X10_WCD_A_RX_LINE_CNP_EN] = 1, |
| 199 | [MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL] = 1, |
| 200 | [MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME] = 1, |
| 201 | [MSM8X10_WCD_A_RX_LINE_1_GAIN] = 1, |
| 202 | [MSM8X10_WCD_A_RX_LINE_1_TEST] = 1, |
| 203 | [MSM8X10_WCD_A_RX_LINE_1_DAC_CTL] = 1, |
| 204 | [MSM8X10_WCD_A_RX_LINE_1_STATUS] = 1, |
| 205 | [MSM8X10_WCD_A_RX_LINE_CNP_DBG] = 1, |
| 206 | [MSM8X10_WCD_A_SPKR_DRV_EN] = 1, |
| 207 | [MSM8X10_WCD_A_SPKR_DRV_GAIN] = 1, |
| 208 | [MSM8X10_WCD_A_SPKR_DRV_DAC_CTL] = 1, |
| 209 | [MSM8X10_WCD_A_SPKR_DRV_OCP_CTL] = 1, |
| 210 | [MSM8X10_WCD_A_SPKR_DRV_CLIP_DET] = 1, |
| 211 | [MSM8X10_WCD_A_SPKR_DRV_IEC] = 1, |
| 212 | [MSM8X10_WCD_A_SPKR_DRV_DBG_DAC] = 1, |
| 213 | [MSM8X10_WCD_A_SPKR_DRV_DBG_PA] = 1, |
| 214 | [MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG] = 1, |
| 215 | [MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO] = 1, |
| 216 | [MSM8X10_WCD_A_SPKR_DRV_BIAS_INT] = 1, |
| 217 | [MSM8X10_WCD_A_SPKR_DRV_BIAS_PA] = 1, |
| 218 | [MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP] = 1, |
| 219 | [MSM8X10_WCD_A_SPKR_DRV_STATUS_PA] = 1, |
| 220 | [MSM8X10_WCD_A_RC_OSC_FREQ] = 1, |
| 221 | [MSM8X10_WCD_A_RC_OSC_TEST] = 1, |
| 222 | [MSM8X10_WCD_A_RC_OSC_STATUS] = 1, |
| 223 | [MSM8X10_WCD_A_RC_OSC_TUNER] = 1, |
| 224 | [MSM8X10_WCD_A_MBHC_HPH] = 1, |
| 225 | [MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL] = 1, |
| 226 | [MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL] = 1, |
| 227 | [MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL] = 1, |
| 228 | [MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL] = 1, |
| 229 | [MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL] = 1, |
| 230 | [MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL] = 1, |
| 231 | [MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL] = 1, |
| 232 | [MSM8X10_WCD_A_CDC_CLK_OTHR_CTL] = 1, |
| 233 | [MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL] = 1, |
| 234 | [MSM8X10_WCD_A_CDC_CLK_MCLK_CTL] = 1, |
| 235 | [MSM8X10_WCD_A_CDC_CLK_PDM_CTL] = 1, |
| 236 | [MSM8X10_WCD_A_CDC_CLK_SD_CTL] = 1, |
| 237 | [MSM8X10_WCD_A_CDC_RX1_B1_CTL] = 1, |
| 238 | [MSM8X10_WCD_A_CDC_RX2_B1_CTL] = 1, |
| 239 | [MSM8X10_WCD_A_CDC_RX3_B1_CTL] = 1, |
| 240 | [MSM8X10_WCD_A_CDC_RX1_B2_CTL] = 1, |
| 241 | [MSM8X10_WCD_A_CDC_RX2_B2_CTL] = 1, |
| 242 | [MSM8X10_WCD_A_CDC_RX3_B2_CTL] = 1, |
| 243 | [MSM8X10_WCD_A_CDC_RX1_B3_CTL] = 1, |
| 244 | [MSM8X10_WCD_A_CDC_RX2_B3_CTL] = 1, |
| 245 | [MSM8X10_WCD_A_CDC_RX3_B3_CTL] = 1, |
| 246 | [MSM8X10_WCD_A_CDC_RX1_B4_CTL] = 1, |
| 247 | [MSM8X10_WCD_A_CDC_RX2_B4_CTL] = 1, |
| 248 | [MSM8X10_WCD_A_CDC_RX3_B4_CTL] = 1, |
| 249 | [MSM8X10_WCD_A_CDC_RX1_B5_CTL] = 1, |
| 250 | [MSM8X10_WCD_A_CDC_RX2_B5_CTL] = 1, |
| 251 | [MSM8X10_WCD_A_CDC_RX3_B5_CTL] = 1, |
| 252 | [MSM8X10_WCD_A_CDC_RX1_B6_CTL] = 1, |
| 253 | [MSM8X10_WCD_A_CDC_RX2_B6_CTL] = 1, |
| 254 | [MSM8X10_WCD_A_CDC_RX3_B6_CTL] = 1, |
| 255 | [MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL] = 1, |
| 256 | [MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL] = 1, |
| 257 | [MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL] = 1, |
| 258 | [MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL] = 1, |
| 259 | [MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL] = 1, |
| 260 | [MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL] = 1, |
| 261 | [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL] = 1, |
| 262 | [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL] = 1, |
| 263 | [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL] = 1, |
| 264 | [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL] = 1, |
| 265 | [MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL] = 1, |
| 266 | [MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG] = 1, |
| 267 | [MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG] = 1, |
| 268 | [MSM8X10_WCD_A_CDC_CLSG_CTL] = 1, |
| 269 | [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER] = 1, |
| 270 | [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER] = 1, |
| 271 | [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN] = 1, |
| 272 | [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN] = 1, |
| 273 | [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG] = 1, |
| 274 | [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG] = 1, |
| 275 | [MSM8X10_WCD_A_CDC_TX1_MUX_CTL] = 1, |
| 276 | [MSM8X10_WCD_A_CDC_TX2_MUX_CTL] = 1, |
| 277 | [MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL] = 1, |
| 278 | [MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL] = 1, |
| 279 | [MSM8X10_WCD_A_CDC_TX1_DMIC_CTL] = 1, |
| 280 | [MSM8X10_WCD_A_CDC_TX2_DMIC_CTL] = 1, |
| 281 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL] = 1, |
| 282 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL] = 1, |
| 283 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL] = 1, |
| 284 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL] = 1, |
| 285 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL] = 1, |
| 286 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL] = 1, |
| 287 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL] = 1, |
| 288 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL] = 1, |
| 289 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL] = 1, |
| 290 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL] = 1, |
| 291 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL] = 1, |
| 292 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL] = 1, |
| 293 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL] = 1, |
| 294 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL] = 1, |
| 295 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL] = 1, |
| 296 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL] = 1, |
| 297 | [MSM8X10_WCD_A_CDC_IIR1_CTL] = 1, |
| 298 | [MSM8X10_WCD_A_CDC_IIR2_CTL] = 1, |
| 299 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL] = 1, |
| 300 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL] = 1, |
| 301 | [MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL] = 1, |
| 302 | [MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL] = 1, |
| 303 | [MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL] = 1, |
| 304 | [MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL] = 1, |
| 305 | [MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL] = 1, |
| 306 | [MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL] = 1, |
| 307 | [MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL] = 1, |
| 308 | [MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL] = 1, |
| 309 | [MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL] = 1, |
| 310 | [MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL] = 1, |
| 311 | [MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL] = 1, |
| 312 | [MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL] = 1, |
| 313 | [MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL] = 1, |
| 314 | [MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL] = 1, |
| 315 | [MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL] = 1, |
| 316 | [MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL] = 1, |
| 317 | [MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL] = 1, |
| 318 | [MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL] = 1, |
| 319 | [MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL] = 1, |
| 320 | [MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL] = 1, |
| 321 | [MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL] = 1, |
| 322 | [MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL] = 1, |
| 323 | [MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE] = 1, |
| 324 | [MSM8X10_WCD_A_CDC_TOP_CTL] = 1, |
| 325 | [MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL] = 1, |
| 326 | [MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL] = 1, |
| 327 | [MSM8X10_WCD_A_CDC_DEBUG_B1_CTL] = 1, |
| 328 | [MSM8X10_WCD_A_CDC_DEBUG_B2_CTL] = 1, |
| 329 | [MSM8X10_WCD_A_CDC_DEBUG_B3_CTL] = 1, |
| 330 | }; |
| 331 | |
| 332 | const u8 msm8x10_wcd_reset_reg_defaults[MSM8X10_WCD_CACHE_SIZE] = { |
| 333 | [MSM8X10_WCD_A_CHIP_CTL] = MSM8X10_WCD_A_CHIP_CTL__POR, |
| 334 | [MSM8X10_WCD_A_CHIP_STATUS] = MSM8X10_WCD_A_CHIP_STATUS__POR, |
| 335 | [MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT] = |
| 336 | MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT__POR, |
| 337 | [MSM8X10_WCD_A_MODE_LOCK] = MSM8X10_WCD_A_MODE_LOCK__POR, |
| 338 | [MSM8X10_WCD_A_CHIP_ID_BYTE_0] = MSM8X10_WCD_A_CHIP_ID_BYTE_0__POR, |
| 339 | [MSM8X10_WCD_A_CHIP_ID_BYTE_1] = MSM8X10_WCD_A_CHIP_ID_BYTE_1__POR, |
| 340 | [MSM8X10_WCD_A_CHIP_ID_BYTE_2] = MSM8X10_WCD_A_CHIP_ID_BYTE_2__POR, |
| 341 | [MSM8X10_WCD_A_CHIP_ID_BYTE_3] = MSM8X10_WCD_A_CHIP_ID_BYTE_3__POR, |
| 342 | [MSM8X10_WCD_A_CHIP_VERSION] = MSM8X10_WCD_A_CHIP_VERSION__POR, |
| 343 | [MSM8X10_WCD_A_ANALOG_SLAVE_ID] = MSM8X10_WCD_A_ANALOG_SLAVE_ID__POR, |
| 344 | [MSM8X10_WCD_A_PIN_CTL_OE] = MSM8X10_WCD_A_PIN_CTL_OE__POR, |
| 345 | [MSM8X10_WCD_A_PIN_CTL_DATA] = MSM8X10_WCD_A_PIN_CTL_DATA__POR, |
| 346 | [MSM8X10_WCD_A_PIN_STATUS] = MSM8X10_WCD_A_PIN_STATUS__POR, |
| 347 | [MSM8X10_WCD_A_HDRIVE_CTL] = MSM8X10_WCD_A_HDRIVE_CTL__POR, |
| 348 | [MSM8X10_WCD_A_HDRIVE_I2C_CTL] = MSM8X10_WCD_A_HDRIVE_I2C_CTL__POR, |
| 349 | [MSM8X10_WCD_A_CDC_RST_CTL] = MSM8X10_WCD_A_CDC_RST_CTL__POR, |
| 350 | [MSM8X10_WCD_A_CDC_TOP_CLK_CTL] = MSM8X10_WCD_A_CDC_TOP_CLK_CTL__POR, |
| 351 | [MSM8X10_WCD_A_CDC_ANA_CLK_CTL] = MSM8X10_WCD_A_CDC_ANA_CLK_CTL__POR, |
| 352 | [MSM8X10_WCD_A_CDC_DIG_CLK_CTL] = MSM8X10_WCD_A_CDC_DIG_CLK_CTL__POR, |
| 353 | [MSM8X10_WCD_A_PROCESS_MONITOR_CTL0] = |
| 354 | MSM8X10_WCD_A_PROCESS_MONITOR_CTL0__POR, |
| 355 | [MSM8X10_WCD_A_PROCESS_MONITOR_CTL1] = |
| 356 | MSM8X10_WCD_A_PROCESS_MONITOR_CTL1__POR, |
| 357 | [MSM8X10_WCD_A_PROCESS_MONITOR_CTL2] = |
| 358 | MSM8X10_WCD_A_PROCESS_MONITOR_CTL2__POR, |
| 359 | [MSM8X10_WCD_A_PROCESS_MONITOR_CTL3] = |
| 360 | MSM8X10_WCD_A_PROCESS_MONITOR_CTL3__POR, |
| 361 | [MSM8X10_WCD_A_QFUSE_CTL] = MSM8X10_WCD_A_QFUSE_CTL__POR, |
| 362 | [MSM8X10_WCD_A_QFUSE_STATUS] = MSM8X10_WCD_A_QFUSE_STATUS__POR, |
| 363 | [MSM8X10_WCD_A_QFUSE_DATA_OUT0] = MSM8X10_WCD_A_QFUSE_DATA_OUT0__POR, |
| 364 | [MSM8X10_WCD_A_QFUSE_DATA_OUT1] = MSM8X10_WCD_A_QFUSE_DATA_OUT1__POR, |
| 365 | [MSM8X10_WCD_A_QFUSE_DATA_OUT2] = MSM8X10_WCD_A_QFUSE_DATA_OUT2__POR, |
| 366 | [MSM8X10_WCD_A_QFUSE_DATA_OUT3] = MSM8X10_WCD_A_QFUSE_DATA_OUT3__POR, |
| 367 | [MSM8X10_WCD_A_CDC_CONN_TX1_CTL] = MSM8X10_WCD_A_CDC_CONN_TX1_CTL__POR, |
| 368 | [MSM8X10_WCD_A_CDC_CONN_TX2_CTL] = MSM8X10_WCD_A_CDC_CONN_TX2_CTL__POR, |
| 369 | [MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL] = |
| 370 | MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL__POR, |
| 371 | [MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL] = |
| 372 | MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL__POR, |
| 373 | [MSM8X10_WCD_A_CDC_CONN_RX1_CTL] = MSM8X10_WCD_A_CDC_CONN_RX1_CTL__POR, |
| 374 | [MSM8X10_WCD_A_CDC_CONN_RX2_CTL] = MSM8X10_WCD_A_CDC_CONN_RX2_CTL__POR, |
| 375 | [MSM8X10_WCD_A_CDC_CONN_RX3_CTL] = MSM8X10_WCD_A_CDC_CONN_RX3_CTL__POR, |
| 376 | [MSM8X10_WCD_A_DIGITAL_DEBUG_CTL] = |
| 377 | MSM8X10_WCD_A_DIGITAL_DEBUG_CTL__POR, |
| 378 | [MSM8X10_WCD_A_ANALOG_DEBUG_CTL] = MSM8X10_WCD_A_ANALOG_DEBUG_CTL__POR, |
| 379 | [MSM8X10_WCD_A_CDC_RX1_CTL] = MSM8X10_WCD_A_CDC_RX1_CTL__POR, |
| 380 | [MSM8X10_WCD_A_CDC_RX2_CTL] = MSM8X10_WCD_A_CDC_RX2_CTL__POR, |
| 381 | [MSM8X10_WCD_A_CDC_RX3_CTL] = MSM8X10_WCD_A_CDC_RX3_CTL__POR, |
| 382 | [MSM8X10_WCD_A_DEM_BYPASS_DATA0] = MSM8X10_WCD_A_DEM_BYPASS_DATA0__POR, |
| 383 | [MSM8X10_WCD_A_DEM_BYPASS_DATA1] = MSM8X10_WCD_A_DEM_BYPASS_DATA1__POR, |
| 384 | [MSM8X10_WCD_A_DEM_BYPASS_DATA2] = MSM8X10_WCD_A_DEM_BYPASS_DATA2__POR, |
| 385 | [MSM8X10_WCD_A_DEM_BYPASS_DATA3] = MSM8X10_WCD_A_DEM_BYPASS_DATA3__POR, |
| 386 | [MSM8X10_WCD_A_SPARE_0] = MSM8X10_WCD_A_SPARE_0__POR, |
| 387 | [MSM8X10_WCD_A_SPARE_1] = MSM8X10_WCD_A_SPARE_1__POR, |
| 388 | [MSM8X10_WCD_A_SPARE_2] = MSM8X10_WCD_A_SPARE_2__POR, |
| 389 | [MSM8X10_WCD_A_INTR_MODE] = MSM8X10_WCD_A_INTR_MODE__POR, |
| 390 | [MSM8X10_WCD_A_INTR_MASK0] = MSM8X10_WCD_A_INTR_MASK0__POR, |
| 391 | [MSM8X10_WCD_A_INTR_MASK1] = MSM8X10_WCD_A_INTR_MASK1__POR, |
| 392 | [MSM8X10_WCD_A_INTR_MASK2] = MSM8X10_WCD_A_INTR_MASK2__POR, |
| 393 | [MSM8X10_WCD_A_INTR_STATUS0] = MSM8X10_WCD_A_INTR_STATUS0__POR, |
| 394 | [MSM8X10_WCD_A_INTR_STATUS1] = MSM8X10_WCD_A_INTR_STATUS1__POR, |
| 395 | [MSM8X10_WCD_A_INTR_STATUS2] = MSM8X10_WCD_A_INTR_STATUS2__POR, |
| 396 | [MSM8X10_WCD_A_INTR_CLEAR0] = MSM8X10_WCD_A_INTR_CLEAR0__POR, |
| 397 | [MSM8X10_WCD_A_INTR_CLEAR1] = MSM8X10_WCD_A_INTR_CLEAR1__POR, |
| 398 | [MSM8X10_WCD_A_INTR_CLEAR2] = MSM8X10_WCD_A_INTR_CLEAR2__POR, |
| 399 | [MSM8X10_WCD_A_INTR_TEST0] = MSM8X10_WCD_A_INTR_TEST0__POR, |
| 400 | [MSM8X10_WCD_A_INTR_TEST1] = MSM8X10_WCD_A_INTR_TEST1__POR, |
| 401 | [MSM8X10_WCD_A_INTR_TEST2] = MSM8X10_WCD_A_INTR_TEST2__POR, |
| 402 | [MSM8X10_WCD_A_INTR_SET0] = MSM8X10_WCD_A_INTR_SET0__POR, |
| 403 | [MSM8X10_WCD_A_INTR_SET1] = MSM8X10_WCD_A_INTR_SET1__POR, |
| 404 | [MSM8X10_WCD_A_INTR_SET2] = MSM8X10_WCD_A_INTR_SET2__POR, |
| 405 | [MSM8X10_WCD_A_CDC_MBHC_EN_CTL] = MSM8X10_WCD_A_CDC_MBHC_EN_CTL__POR, |
| 406 | [MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG] = |
| 407 | MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG__POR, |
| 408 | [MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG] = |
| 409 | MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG__POR, |
| 410 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL] = |
| 411 | MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL__POR, |
| 412 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL] = |
| 413 | MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL__POR, |
| 414 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL] = |
| 415 | MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL__POR, |
| 416 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL] = |
| 417 | MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL__POR, |
| 418 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL] = |
| 419 | MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL__POR, |
| 420 | [MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL] = |
| 421 | MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL__POR, |
| 422 | [MSM8X10_WCD_A_CDC_MBHC_B1_STATUS] = |
| 423 | MSM8X10_WCD_A_CDC_MBHC_B1_STATUS__POR, |
| 424 | [MSM8X10_WCD_A_CDC_MBHC_B2_STATUS] = |
| 425 | MSM8X10_WCD_A_CDC_MBHC_B2_STATUS__POR, |
| 426 | [MSM8X10_WCD_A_CDC_MBHC_B3_STATUS] = |
| 427 | MSM8X10_WCD_A_CDC_MBHC_B3_STATUS__POR, |
| 428 | [MSM8X10_WCD_A_CDC_MBHC_B4_STATUS] = |
| 429 | MSM8X10_WCD_A_CDC_MBHC_B4_STATUS__POR, |
| 430 | [MSM8X10_WCD_A_CDC_MBHC_B5_STATUS] = |
| 431 | MSM8X10_WCD_A_CDC_MBHC_B5_STATUS__POR, |
| 432 | [MSM8X10_WCD_A_CDC_MBHC_B1_CTL] = MSM8X10_WCD_A_CDC_MBHC_B1_CTL__POR, |
| 433 | [MSM8X10_WCD_A_CDC_MBHC_B2_CTL] = MSM8X10_WCD_A_CDC_MBHC_B2_CTL__POR, |
| 434 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL] = |
| 435 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL__POR, |
| 436 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL] = |
| 437 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL__POR, |
| 438 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL] = |
| 439 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL__POR, |
| 440 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL] = |
| 441 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL__POR, |
| 442 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL] = |
| 443 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL__POR, |
| 444 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL] = |
| 445 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL__POR, |
| 446 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL] = |
| 447 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL__POR, |
| 448 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL] = |
| 449 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL__POR, |
| 450 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL] = |
| 451 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL__POR, |
| 452 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL] = |
| 453 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL__POR, |
| 454 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL] = |
| 455 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL__POR, |
| 456 | [MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL] = |
| 457 | MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL__POR, |
| 458 | [MSM8X10_WCD_A_CDC_MBHC_CLK_CTL] = MSM8X10_WCD_A_CDC_MBHC_CLK_CTL__POR, |
| 459 | [MSM8X10_WCD_A_CDC_MBHC_INT_CTL] = MSM8X10_WCD_A_CDC_MBHC_INT_CTL__POR, |
| 460 | [MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL] = |
| 461 | MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL__POR, |
| 462 | [MSM8X10_WCD_A_CDC_MBHC_SPARE] = MSM8X10_WCD_A_CDC_MBHC_SPARE__POR, |
| 463 | [MSM8X10_WCD_A_BIAS_REF_CTL] = MSM8X10_WCD_A_BIAS_REF_CTL__POR, |
| 464 | [MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL] = |
| 465 | MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL__POR, |
| 466 | [MSM8X10_WCD_A_BIAS_PRECHRG_CTL] = MSM8X10_WCD_A_BIAS_PRECHRG_CTL__POR, |
| 467 | [MSM8X10_WCD_A_BIAS_CURR_CTL_1] = MSM8X10_WCD_A_BIAS_CURR_CTL_1__POR, |
| 468 | [MSM8X10_WCD_A_BIAS_CURR_CTL_2] = MSM8X10_WCD_A_BIAS_CURR_CTL_2__POR, |
| 469 | [MSM8X10_WCD_A_BIAS_OSC_BG_CTL] = MSM8X10_WCD_A_BIAS_OSC_BG_CTL__POR, |
| 470 | [MSM8X10_WCD_A_MICB_CFILT_1_CTL] = MSM8X10_WCD_A_MICB_CFILT_1_CTL__POR, |
| 471 | [MSM8X10_WCD_A_MICB_CFILT_1_VAL] = MSM8X10_WCD_A_MICB_CFILT_1_VAL__POR, |
| 472 | [MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG] = |
| 473 | MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG__POR, |
| 474 | [MSM8X10_WCD_A_MICB_1_CTL] = MSM8X10_WCD_A_MICB_1_CTL__POR, |
| 475 | [MSM8X10_WCD_A_MICB_1_INT_RBIAS] = MSM8X10_WCD_A_MICB_1_INT_RBIAS__POR, |
| 476 | [MSM8X10_WCD_A_MICB_1_MBHC] = MSM8X10_WCD_A_MICB_1_MBHC__POR, |
| 477 | [MSM8X10_WCD_A_MBHC_INSERT_DETECT] = |
| 478 | MSM8X10_WCD_A_MBHC_INSERT_DETECT__POR, |
| 479 | [MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS] = |
| 480 | MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS__POR, |
| 481 | [MSM8X10_WCD_A_TX_COM_BIAS] = MSM8X10_WCD_A_TX_COM_BIAS__POR, |
| 482 | [MSM8X10_WCD_A_MBHC_SCALING_MUX_1] = |
| 483 | MSM8X10_WCD_A_MBHC_SCALING_MUX_1__POR, |
| 484 | [MSM8X10_WCD_A_MBHC_SCALING_MUX_2] = |
| 485 | MSM8X10_WCD_A_MBHC_SCALING_MUX_2__POR, |
| 486 | [MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL] = |
| 487 | MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL__POR, |
| 488 | [MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1] = |
| 489 | MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1__POR, |
| 490 | [MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2] = |
| 491 | MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2__POR, |
| 492 | [MSM8X10_WCD_A_TX_1_EN] = MSM8X10_WCD_A_TX_1_EN__POR, |
| 493 | [MSM8X10_WCD_A_TX_2_EN] = MSM8X10_WCD_A_TX_2_EN__POR, |
| 494 | [MSM8X10_WCD_A_TX_1_2_ADC_CH1] = MSM8X10_WCD_A_TX_1_2_ADC_CH1__POR, |
| 495 | [MSM8X10_WCD_A_TX_1_2_ADC_CH2] = MSM8X10_WCD_A_TX_1_2_ADC_CH2__POR, |
| 496 | [MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL] = |
| 497 | MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL__POR, |
| 498 | [MSM8X10_WCD_A_TX_1_2_TEST_CTL] = |
| 499 | MSM8X10_WCD_A_TX_1_2_TEST_CTL__POR, |
| 500 | [MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN] = |
| 501 | MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN__POR, |
| 502 | [MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV] = |
| 503 | MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV__POR, |
| 504 | [MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1] = |
| 505 | MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1__POR, |
| 506 | [MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2] = |
| 507 | MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2__POR, |
| 508 | [MSM8X10_WCD_A_TX_3_EN] = MSM8X10_WCD_A_TX_3_EN__POR, |
| 509 | [MSM8X10_WCD_A_TX_1_2_TEST_EN] = MSM8X10_WCD_A_TX_1_2_TEST_EN__POR, |
| 510 | [MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL] = |
| 511 | MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL__POR, |
| 512 | [MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR] = |
| 513 | MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR__POR, |
| 514 | [MSM8X10_WCD_A_CP_EN] = MSM8X10_WCD_A_CP_EN__POR, |
| 515 | [MSM8X10_WCD_A_CP_CLK] = MSM8X10_WCD_A_CP_CLK__POR, |
| 516 | [MSM8X10_WCD_A_CP_STATIC] = MSM8X10_WCD_A_CP_STATIC__POR, |
| 517 | [MSM8X10_WCD_A_CP_DCC1] = MSM8X10_WCD_A_CP_DCC1__POR, |
| 518 | [MSM8X10_WCD_A_CP_DCC3] = MSM8X10_WCD_A_CP_DCC3__POR, |
| 519 | [MSM8X10_WCD_A_CP_ATEST] = MSM8X10_WCD_A_CP_ATEST__POR, |
| 520 | [MSM8X10_WCD_A_CP_DTEST] = MSM8X10_WCD_A_CP_DTEST__POR, |
| 521 | [MSM8X10_WCD_A_RX_AUX_SW_CTL] = MSM8X10_WCD_A_RX_AUX_SW_CTL__POR, |
| 522 | [MSM8X10_WCD_A_RX_PA_AUX_IN_CONN] = |
| 523 | MSM8X10_WCD_A_RX_PA_AUX_IN_CONN__POR, |
| 524 | [MSM8X10_WCD_A_RX_COM_TIMER_DIV] = MSM8X10_WCD_A_RX_COM_TIMER_DIV__POR, |
| 525 | [MSM8X10_WCD_A_RX_COM_OCP_CTL] = MSM8X10_WCD_A_RX_COM_OCP_CTL__POR, |
| 526 | [MSM8X10_WCD_A_RX_COM_OCP_COUNT] = MSM8X10_WCD_A_RX_COM_OCP_COUNT__POR, |
| 527 | [MSM8X10_WCD_A_RX_COM_DAC_CTL] = MSM8X10_WCD_A_RX_COM_DAC_CTL__POR, |
| 528 | [MSM8X10_WCD_A_RX_COM_BIAS] = MSM8X10_WCD_A_RX_COM_BIAS__POR, |
| 529 | [MSM8X10_WCD_A_RX_HPH_AUTO_CHOP] = MSM8X10_WCD_A_RX_HPH_AUTO_CHOP__POR, |
| 530 | [MSM8X10_WCD_A_RX_HPH_CHOP_CTL] = MSM8X10_WCD_A_RX_HPH_CHOP_CTL__POR, |
| 531 | [MSM8X10_WCD_A_RX_HPH_BIAS_PA] = MSM8X10_WCD_A_RX_HPH_BIAS_PA__POR, |
| 532 | [MSM8X10_WCD_A_RX_HPH_BIAS_LDO] = MSM8X10_WCD_A_RX_HPH_BIAS_LDO__POR, |
| 533 | [MSM8X10_WCD_A_RX_HPH_BIAS_CNP] = MSM8X10_WCD_A_RX_HPH_BIAS_CNP__POR, |
| 534 | [MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP] = |
| 535 | MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP__POR, |
| 536 | [MSM8X10_WCD_A_RX_HPH_OCP_CTL] = MSM8X10_WCD_A_RX_HPH_OCP_CTL__POR, |
| 537 | [MSM8X10_WCD_A_RX_HPH_CNP_EN] = MSM8X10_WCD_A_RX_HPH_CNP_EN__POR, |
| 538 | [MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL] = |
| 539 | MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL__POR, |
| 540 | [MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME] = |
| 541 | MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME__POR, |
| 542 | [MSM8X10_WCD_A_RX_HPH_L_GAIN] = MSM8X10_WCD_A_RX_HPH_L_GAIN__POR, |
| 543 | [MSM8X10_WCD_A_RX_HPH_L_TEST] = MSM8X10_WCD_A_RX_HPH_L_TEST__POR, |
| 544 | [MSM8X10_WCD_A_RX_HPH_L_PA_CTL] = MSM8X10_WCD_A_RX_HPH_L_PA_CTL__POR, |
| 545 | [MSM8X10_WCD_A_RX_HPH_L_DAC_CTL] = |
| 546 | MSM8X10_WCD_A_RX_HPH_L_DAC_CTL__POR, |
| 547 | [MSM8X10_WCD_A_RX_HPH_L_ATEST] = MSM8X10_WCD_A_RX_HPH_L_ATEST__POR, |
| 548 | [MSM8X10_WCD_A_RX_HPH_L_STATUS] = MSM8X10_WCD_A_RX_HPH_L_STATUS__POR, |
| 549 | [MSM8X10_WCD_A_RX_HPH_R_GAIN] = MSM8X10_WCD_A_RX_HPH_R_GAIN__POR, |
| 550 | [MSM8X10_WCD_A_RX_HPH_R_TEST] = MSM8X10_WCD_A_RX_HPH_R_TEST__POR, |
| 551 | [MSM8X10_WCD_A_RX_HPH_R_PA_CTL] = MSM8X10_WCD_A_RX_HPH_R_PA_CTL__POR, |
| 552 | [MSM8X10_WCD_A_RX_HPH_R_DAC_CTL] = MSM8X10_WCD_A_RX_HPH_R_DAC_CTL__POR, |
| 553 | [MSM8X10_WCD_A_RX_HPH_R_ATEST] = MSM8X10_WCD_A_RX_HPH_R_ATEST__POR, |
| 554 | [MSM8X10_WCD_A_RX_HPH_R_STATUS] = MSM8X10_WCD_A_RX_HPH_R_STATUS__POR, |
| 555 | [MSM8X10_WCD_A_RX_EAR_BIAS_PA] = MSM8X10_WCD_A_RX_EAR_BIAS_PA__POR, |
| 556 | [MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF] = |
| 557 | MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF__POR, |
| 558 | [MSM8X10_WCD_A_RX_EAR_EN] = MSM8X10_WCD_A_RX_EAR_EN__POR, |
| 559 | [MSM8X10_WCD_A_RX_EAR_GAIN] = MSM8X10_WCD_A_RX_EAR_GAIN__POR, |
| 560 | [MSM8X10_WCD_A_RX_EAR_CMBUFF] = MSM8X10_WCD_A_RX_EAR_CMBUFF__POR, |
| 561 | [MSM8X10_WCD_A_RX_EAR_ICTL] = MSM8X10_WCD_A_RX_EAR_ICTL__POR, |
| 562 | [MSM8X10_WCD_A_RX_EAR_CCOMP] = MSM8X10_WCD_A_RX_EAR_CCOMP__POR, |
| 563 | [MSM8X10_WCD_A_RX_EAR_VCM] = MSM8X10_WCD_A_RX_EAR_VCM__POR, |
| 564 | [MSM8X10_WCD_A_RX_EAR_CNP] = MSM8X10_WCD_A_RX_EAR_CNP__POR, |
| 565 | [MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST] = |
| 566 | MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST__POR, |
| 567 | [MSM8X10_WCD_A_RX_EAR_STATUS] = MSM8X10_WCD_A_RX_EAR_STATUS__POR, |
| 568 | [MSM8X10_WCD_A_RX_LINE_BIAS_PA] = |
| 569 | MSM8X10_WCD_A_RX_LINE_BIAS_PA__POR, |
| 570 | [MSM8X10_WCD_A_RX_BUCK_BIAS1] = MSM8X10_WCD_A_RX_BUCK_BIAS1__POR, |
| 571 | [MSM8X10_WCD_A_RX_BUCK_BIAS2] = MSM8X10_WCD_A_RX_BUCK_BIAS2__POR, |
| 572 | [MSM8X10_WCD_A_RX_LINE_COM] = MSM8X10_WCD_A_RX_LINE_COM__POR, |
| 573 | [MSM8X10_WCD_A_RX_LINE_CNP_EN] = MSM8X10_WCD_A_RX_LINE_CNP_EN__POR, |
| 574 | [MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL] = |
| 575 | MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL__POR, |
| 576 | [MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME] = |
| 577 | MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME__POR, |
| 578 | [MSM8X10_WCD_A_RX_LINE_1_GAIN] = MSM8X10_WCD_A_RX_LINE_1_GAIN__POR, |
| 579 | [MSM8X10_WCD_A_RX_LINE_1_TEST] = MSM8X10_WCD_A_RX_LINE_1_TEST__POR, |
| 580 | [MSM8X10_WCD_A_RX_LINE_1_DAC_CTL] = |
| 581 | MSM8X10_WCD_A_RX_LINE_1_DAC_CTL__POR, |
| 582 | [MSM8X10_WCD_A_RX_LINE_1_STATUS] = |
| 583 | MSM8X10_WCD_A_RX_LINE_1_STATUS__POR, |
| 584 | [MSM8X10_WCD_A_RX_LINE_CNP_DBG] = MSM8X10_WCD_A_RX_LINE_CNP_DBG__POR, |
| 585 | [MSM8X10_WCD_A_SPKR_DRV_EN] = MSM8X10_WCD_A_SPKR_DRV_EN__POR, |
| 586 | [MSM8X10_WCD_A_SPKR_DRV_GAIN] = MSM8X10_WCD_A_SPKR_DRV_GAIN__POR, |
| 587 | [MSM8X10_WCD_A_SPKR_DRV_DAC_CTL] = MSM8X10_WCD_A_SPKR_DRV_DAC_CTL__POR, |
| 588 | [MSM8X10_WCD_A_SPKR_DRV_OCP_CTL] = MSM8X10_WCD_A_SPKR_DRV_OCP_CTL__POR, |
| 589 | [MSM8X10_WCD_A_SPKR_DRV_CLIP_DET] = |
| 590 | MSM8X10_WCD_A_SPKR_DRV_CLIP_DET__POR, |
| 591 | [MSM8X10_WCD_A_SPKR_DRV_IEC] = MSM8X10_WCD_A_SPKR_DRV_IEC__POR, |
| 592 | [MSM8X10_WCD_A_SPKR_DRV_DBG_DAC] = MSM8X10_WCD_A_SPKR_DRV_DBG_DAC__POR, |
| 593 | [MSM8X10_WCD_A_SPKR_DRV_DBG_PA] = MSM8X10_WCD_A_SPKR_DRV_DBG_PA__POR, |
| 594 | [MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG] = |
| 595 | MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG__POR, |
| 596 | [MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO] = |
| 597 | MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO__POR, |
| 598 | [MSM8X10_WCD_A_SPKR_DRV_BIAS_INT] = |
| 599 | MSM8X10_WCD_A_SPKR_DRV_BIAS_INT__POR, |
| 600 | [MSM8X10_WCD_A_SPKR_DRV_BIAS_PA] = MSM8X10_WCD_A_SPKR_DRV_BIAS_PA__POR, |
| 601 | [MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP] = |
| 602 | MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP__POR, |
| 603 | [MSM8X10_WCD_A_SPKR_DRV_STATUS_PA] = |
| 604 | MSM8X10_WCD_A_SPKR_DRV_STATUS_PA__POR, |
| 605 | [MSM8X10_WCD_A_RC_OSC_FREQ] = MSM8X10_WCD_A_RC_OSC_FREQ__POR, |
| 606 | [MSM8X10_WCD_A_RC_OSC_TEST] = MSM8X10_WCD_A_RC_OSC_TEST__POR, |
| 607 | [MSM8X10_WCD_A_RC_OSC_STATUS] = MSM8X10_WCD_A_RC_OSC_STATUS__POR, |
| 608 | [MSM8X10_WCD_A_RC_OSC_TUNER] = MSM8X10_WCD_A_RC_OSC_TUNER__POR, |
| 609 | [MSM8X10_WCD_A_MBHC_HPH] = MSM8X10_WCD_A_MBHC_HPH__POR, |
| 610 | [MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL] = |
| 611 | MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL__POR, |
| 612 | [MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL] = |
| 613 | MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL__POR, |
| 614 | [MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL] = |
| 615 | MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL__POR, |
| 616 | [MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL] = |
| 617 | MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL__POR, |
| 618 | [MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL] = |
| 619 | MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL__POR, |
| 620 | [MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL] = |
| 621 | MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL__POR, |
| 622 | [MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL] = |
| 623 | MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR, |
| 624 | [MSM8X10_WCD_A_CDC_CLK_OTHR_CTL] = MSM8X10_WCD_A_CDC_CLK_OTHR_CTL__POR, |
| 625 | [MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL] = |
| 626 | MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL__POR, |
| 627 | [MSM8X10_WCD_A_CDC_CLK_MCLK_CTL] = MSM8X10_WCD_A_CDC_CLK_MCLK_CTL__POR, |
| 628 | [MSM8X10_WCD_A_CDC_CLK_PDM_CTL] = MSM8X10_WCD_A_CDC_CLK_PDM_CTL__POR, |
| 629 | [MSM8X10_WCD_A_CDC_CLK_SD_CTL] = MSM8X10_WCD_A_CDC_CLK_SD_CTL__POR, |
| 630 | [MSM8X10_WCD_A_CDC_RX1_B1_CTL] = MSM8X10_WCD_A_CDC_RX1_B1_CTL__POR, |
| 631 | [MSM8X10_WCD_A_CDC_RX2_B1_CTL] = MSM8X10_WCD_A_CDC_RX2_B1_CTL__POR, |
| 632 | [MSM8X10_WCD_A_CDC_RX3_B1_CTL] = MSM8X10_WCD_A_CDC_RX3_B1_CTL__POR, |
| 633 | [MSM8X10_WCD_A_CDC_RX1_B2_CTL] = MSM8X10_WCD_A_CDC_RX1_B2_CTL__POR, |
| 634 | [MSM8X10_WCD_A_CDC_RX2_B2_CTL] = MSM8X10_WCD_A_CDC_RX2_B2_CTL__POR, |
| 635 | [MSM8X10_WCD_A_CDC_RX3_B2_CTL] = MSM8X10_WCD_A_CDC_RX3_B2_CTL__POR, |
| 636 | [MSM8X10_WCD_A_CDC_RX1_B3_CTL] = MSM8X10_WCD_A_CDC_RX1_B3_CTL__POR, |
| 637 | [MSM8X10_WCD_A_CDC_RX2_B3_CTL] = MSM8X10_WCD_A_CDC_RX2_B3_CTL__POR, |
| 638 | [MSM8X10_WCD_A_CDC_RX3_B3_CTL] = MSM8X10_WCD_A_CDC_RX3_B3_CTL__POR, |
| 639 | [MSM8X10_WCD_A_CDC_RX1_B4_CTL] = MSM8X10_WCD_A_CDC_RX1_B4_CTL__POR, |
| 640 | [MSM8X10_WCD_A_CDC_RX2_B4_CTL] = MSM8X10_WCD_A_CDC_RX2_B4_CTL__POR, |
| 641 | [MSM8X10_WCD_A_CDC_RX3_B4_CTL] = MSM8X10_WCD_A_CDC_RX3_B4_CTL__POR, |
| 642 | [MSM8X10_WCD_A_CDC_RX1_B5_CTL] = MSM8X10_WCD_A_CDC_RX1_B5_CTL__POR, |
| 643 | [MSM8X10_WCD_A_CDC_RX2_B5_CTL] = MSM8X10_WCD_A_CDC_RX2_B5_CTL__POR, |
| 644 | [MSM8X10_WCD_A_CDC_RX3_B5_CTL] = MSM8X10_WCD_A_CDC_RX3_B5_CTL__POR, |
| 645 | [MSM8X10_WCD_A_CDC_RX1_B6_CTL] = MSM8X10_WCD_A_CDC_RX1_B6_CTL__POR, |
| 646 | [MSM8X10_WCD_A_CDC_RX2_B6_CTL] = MSM8X10_WCD_A_CDC_RX2_B6_CTL__POR, |
| 647 | [MSM8X10_WCD_A_CDC_RX3_B6_CTL] = MSM8X10_WCD_A_CDC_RX3_B6_CTL__POR, |
| 648 | [MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL] = |
| 649 | MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL__POR, |
| 650 | [MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL] = |
| 651 | MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL__POR, |
| 652 | [MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL] = |
| 653 | MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL__POR, |
| 654 | [MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL] = |
| 655 | MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL__POR, |
| 656 | [MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL] = |
| 657 | MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL__POR, |
| 658 | [MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL] = |
| 659 | MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL__POR, |
| 660 | [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL] = |
| 661 | MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR, |
| 662 | [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL] = |
| 663 | MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR, |
| 664 | [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL] = |
| 665 | MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR, |
| 666 | [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL] = |
| 667 | MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR, |
| 668 | [MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL] = |
| 669 | MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL__POR, |
| 670 | [MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG] = |
| 671 | MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG__POR, |
| 672 | [MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG] = |
| 673 | MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG__POR, |
| 674 | [MSM8X10_WCD_A_CDC_CLSG_CTL] = MSM8X10_WCD_A_CDC_CLSG_CTL__POR, |
| 675 | [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER] = |
| 676 | MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER__POR, |
| 677 | [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER] = |
| 678 | MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER__POR, |
| 679 | [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN] = |
| 680 | MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN__POR, |
| 681 | [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN] = |
| 682 | MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN__POR, |
| 683 | [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG] = |
| 684 | MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG__POR, |
| 685 | [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG] = |
| 686 | MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG__POR, |
| 687 | [MSM8X10_WCD_A_CDC_TX1_MUX_CTL] = |
| 688 | MSM8X10_WCD_A_CDC_TX1_MUX_CTL__POR, |
| 689 | [MSM8X10_WCD_A_CDC_TX2_MUX_CTL] = |
| 690 | MSM8X10_WCD_A_CDC_TX2_MUX_CTL__POR, |
| 691 | [MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL] = |
| 692 | MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL__POR, |
| 693 | [MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL] = |
| 694 | MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL__POR, |
| 695 | [MSM8X10_WCD_A_CDC_TX1_DMIC_CTL] = |
| 696 | MSM8X10_WCD_A_CDC_TX1_DMIC_CTL__POR, |
| 697 | [MSM8X10_WCD_A_CDC_TX2_DMIC_CTL] = |
| 698 | MSM8X10_WCD_A_CDC_TX2_DMIC_CTL__POR, |
| 699 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL] = |
| 700 | MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL__POR, |
| 701 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL] = |
| 702 | MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL__POR, |
| 703 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL] = |
| 704 | MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL__POR, |
| 705 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL] = |
| 706 | MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL__POR, |
| 707 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL] = |
| 708 | MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL__POR, |
| 709 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL] = |
| 710 | MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL__POR, |
| 711 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL] = |
| 712 | MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL__POR, |
| 713 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL] = |
| 714 | MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL__POR, |
| 715 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL] = |
| 716 | MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL__POR, |
| 717 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL] = |
| 718 | MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL__POR, |
| 719 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL] = |
| 720 | MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL__POR, |
| 721 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL] = |
| 722 | MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL__POR, |
| 723 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL] = |
| 724 | MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL__POR, |
| 725 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL] = |
| 726 | MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL__POR, |
| 727 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL] = |
| 728 | MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL__POR, |
| 729 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL] = |
| 730 | MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL__POR, |
| 731 | [MSM8X10_WCD_A_CDC_IIR1_CTL] = MSM8X10_WCD_A_CDC_IIR1_CTL__POR, |
| 732 | [MSM8X10_WCD_A_CDC_IIR2_CTL] = MSM8X10_WCD_A_CDC_IIR2_CTL__POR, |
| 733 | [MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL] = |
| 734 | MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL__POR, |
| 735 | [MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL] = |
| 736 | MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL__POR, |
| 737 | [MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL] = |
| 738 | MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL__POR, |
| 739 | [MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL] = |
| 740 | MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL__POR, |
| 741 | [MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL] = |
| 742 | MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL__POR, |
| 743 | [MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL] = |
| 744 | MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL__POR, |
| 745 | [MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL] = |
| 746 | MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL__POR, |
| 747 | [MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL] = |
| 748 | MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL__POR, |
| 749 | [MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL] = |
| 750 | MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL__POR, |
| 751 | [MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL] = |
| 752 | MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL__POR, |
| 753 | [MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL] = |
| 754 | MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL__POR, |
| 755 | [MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL] = |
| 756 | MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL__POR, |
| 757 | [MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL] = |
| 758 | MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL__POR, |
| 759 | [MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL] = |
| 760 | MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL__POR, |
| 761 | [MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL] = |
| 762 | MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL__POR, |
| 763 | [MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL] = |
| 764 | MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL__POR, |
| 765 | [MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL] = |
| 766 | MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL__POR, |
| 767 | [MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL] = |
| 768 | MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL__POR, |
| 769 | [MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL] = |
| 770 | MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL__POR, |
| 771 | [MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL] = |
| 772 | MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL__POR, |
| 773 | [MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL] = |
| 774 | MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL__POR, |
| 775 | [MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL] = |
| 776 | MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL__POR, |
| 777 | [MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL] = |
| 778 | MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL__POR, |
| 779 | [MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL] = |
| 780 | MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL__POR, |
| 781 | [MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE] = |
| 782 | MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE__POR, |
| 783 | [MSM8X10_WCD_A_CDC_TOP_CTL] = MSM8X10_WCD_A_CDC_TOP_CTL__POR, |
| 784 | [MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL] = |
| 785 | MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL__POR, |
| 786 | [MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL] = |
| 787 | MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL__POR, |
| 788 | [MSM8X10_WCD_A_CDC_DEBUG_B1_CTL] = |
| 789 | MSM8X10_WCD_A_CDC_DEBUG_B1_CTL__POR, |
| 790 | [MSM8X10_WCD_A_CDC_DEBUG_B2_CTL] = |
| 791 | MSM8X10_WCD_A_CDC_DEBUG_B2_CTL__POR, |
| 792 | [MSM8X10_WCD_A_CDC_DEBUG_B3_CTL] = |
| 793 | MSM8X10_WCD_A_CDC_DEBUG_B3_CTL__POR, |
| 794 | }; |