Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. |
| 3 | * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2, or (at your option) |
| 8 | * any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; see the file COPYING. If not, write to |
| 17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | * |
| 19 | * An ATA driver for the legacy ATA ports. |
| 20 | * |
| 21 | * Data Sources: |
| 22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com |
| 23 | * HT6560 series: |
| 24 | * Promise 20230/20620: |
| 25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html |
| 26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html |
| 27 | * http://www.ryston.cz/petr/vlb/pdc20630.html |
| 28 | * |
| 29 | * Unsupported but docs exist: |
| 30 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 |
| 31 | * Winbond W83759A |
| 32 | * |
| 33 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found |
| 34 | * on PC class systems. There are three hybrid devices that are exceptions |
| 35 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and |
| 36 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". |
| 37 | * |
| 38 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ |
| 39 | * opti82c465mv/promise 20230c/20630 |
| 40 | * |
| 41 | * Use the autospeed and pio_mask options with: |
| 42 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. |
| 43 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with |
| 44 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, |
| 45 | * Winbond W83759A, Promise PDC20230-B |
| 46 | * |
| 47 | * For now use autospeed and pio_mask as above with the W83759A. This may |
| 48 | * change. |
| 49 | * |
| 50 | * TODO |
| 51 | * Merge existing pata_qdi driver |
| 52 | * |
| 53 | */ |
| 54 | |
| 55 | #include <linux/kernel.h> |
| 56 | #include <linux/module.h> |
| 57 | #include <linux/pci.h> |
| 58 | #include <linux/init.h> |
| 59 | #include <linux/blkdev.h> |
| 60 | #include <linux/delay.h> |
| 61 | #include <scsi/scsi_host.h> |
| 62 | #include <linux/ata.h> |
| 63 | #include <linux/libata.h> |
| 64 | #include <linux/platform_device.h> |
| 65 | |
| 66 | #define DRV_NAME "pata_legacy" |
| 67 | #define DRV_VERSION "0.5.3" |
| 68 | |
| 69 | #define NR_HOST 6 |
| 70 | |
| 71 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; |
| 72 | static int legacy_irq[NR_HOST] = { 15, 14, 11, 10, 8, 12 }; |
| 73 | |
| 74 | struct legacy_data { |
| 75 | unsigned long timing; |
| 76 | u8 clock[2]; |
| 77 | u8 last; |
| 78 | int fast; |
| 79 | struct platform_device *platform_dev; |
| 80 | |
| 81 | }; |
| 82 | |
| 83 | static struct legacy_data legacy_data[NR_HOST]; |
| 84 | static struct ata_host *legacy_host[NR_HOST]; |
| 85 | static int nr_legacy_host; |
| 86 | |
| 87 | |
| 88 | static int probe_all; /* Set to check all ISA port ranges */ |
| 89 | static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */ |
| 90 | static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */ |
| 91 | static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */ |
| 92 | static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */ |
| 93 | static int autospeed; /* Chip present which snoops speed changes */ |
| 94 | static int pio_mask = 0x1F; /* PIO range for autospeed devices */ |
| 95 | |
| 96 | /** |
| 97 | * legacy_set_mode - mode setting |
| 98 | * @ap: IDE interface |
Alan | b229a7b | 2007-01-24 11:47:07 +0000 | [diff] [blame] | 99 | * @unused: Device that failed when error is returned |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 100 | * |
| 101 | * Use a non standard set_mode function. We don't want to be tuned. |
| 102 | * |
| 103 | * The BIOS configured everything. Our job is not to fiddle. Just use |
| 104 | * whatever PIO the hardware is using and leave it at that. When we |
| 105 | * get some kind of nice user driven API for control then we can |
| 106 | * expand on this as per hdparm in the base kernel. |
| 107 | */ |
| 108 | |
Alan | b229a7b | 2007-01-24 11:47:07 +0000 | [diff] [blame] | 109 | static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 110 | { |
| 111 | int i; |
| 112 | |
| 113 | for (i = 0; i < ATA_MAX_DEVICES; i++) { |
| 114 | struct ata_device *dev = &ap->device[i]; |
| 115 | if (ata_dev_enabled(dev)) { |
| 116 | dev->pio_mode = XFER_PIO_0; |
| 117 | dev->xfer_mode = XFER_PIO_0; |
| 118 | dev->xfer_shift = ATA_SHIFT_PIO; |
| 119 | dev->flags |= ATA_DFLAG_PIO; |
| 120 | } |
| 121 | } |
Alan | b229a7b | 2007-01-24 11:47:07 +0000 | [diff] [blame] | 122 | return 0; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | static struct scsi_host_template legacy_sht = { |
| 126 | .module = THIS_MODULE, |
| 127 | .name = DRV_NAME, |
| 128 | .ioctl = ata_scsi_ioctl, |
| 129 | .queuecommand = ata_scsi_queuecmd, |
| 130 | .can_queue = ATA_DEF_QUEUE, |
| 131 | .this_id = ATA_SHT_THIS_ID, |
| 132 | .sg_tablesize = LIBATA_MAX_PRD, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 133 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 134 | .emulated = ATA_SHT_EMULATED, |
| 135 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 136 | .proc_name = DRV_NAME, |
| 137 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 138 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | afdfe89 | 2006-11-29 11:26:47 +0900 | [diff] [blame] | 139 | .slave_destroy = ata_scsi_slave_destroy, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 140 | .bios_param = ata_std_bios_param, |
| 141 | }; |
| 142 | |
| 143 | /* |
| 144 | * These ops are used if the user indicates the hardware |
| 145 | * snoops the commands to decide on the mode and handles the |
| 146 | * mode selection "magically" itself. Several legacy controllers |
| 147 | * do this. The mode range can be set if it is not 0x1F by setting |
| 148 | * pio_mask as well. |
| 149 | */ |
| 150 | |
| 151 | static struct ata_port_operations simple_port_ops = { |
| 152 | .port_disable = ata_port_disable, |
| 153 | .tf_load = ata_tf_load, |
| 154 | .tf_read = ata_tf_read, |
| 155 | .check_status = ata_check_status, |
| 156 | .exec_command = ata_exec_command, |
| 157 | .dev_select = ata_std_dev_select, |
| 158 | |
| 159 | .freeze = ata_bmdma_freeze, |
| 160 | .thaw = ata_bmdma_thaw, |
| 161 | .error_handler = ata_bmdma_error_handler, |
| 162 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
| 163 | |
| 164 | .qc_prep = ata_qc_prep, |
| 165 | .qc_issue = ata_qc_issue_prot, |
Jeff Garzik | bda3028 | 2006-09-27 05:41:13 -0400 | [diff] [blame] | 166 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 167 | .data_xfer = ata_pio_data_xfer_noirq, |
| 168 | |
| 169 | .irq_handler = ata_interrupt, |
| 170 | .irq_clear = ata_bmdma_irq_clear, |
| 171 | |
| 172 | .port_start = ata_port_start, |
| 173 | .port_stop = ata_port_stop, |
| 174 | .host_stop = ata_host_stop |
| 175 | }; |
| 176 | |
| 177 | static struct ata_port_operations legacy_port_ops = { |
| 178 | .set_mode = legacy_set_mode, |
| 179 | |
| 180 | .port_disable = ata_port_disable, |
| 181 | .tf_load = ata_tf_load, |
| 182 | .tf_read = ata_tf_read, |
| 183 | .check_status = ata_check_status, |
| 184 | .exec_command = ata_exec_command, |
| 185 | .dev_select = ata_std_dev_select, |
| 186 | |
| 187 | .error_handler = ata_bmdma_error_handler, |
| 188 | |
| 189 | .qc_prep = ata_qc_prep, |
| 190 | .qc_issue = ata_qc_issue_prot, |
Jeff Garzik | bda3028 | 2006-09-27 05:41:13 -0400 | [diff] [blame] | 191 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 192 | .data_xfer = ata_pio_data_xfer_noirq, |
| 193 | |
| 194 | .irq_handler = ata_interrupt, |
| 195 | .irq_clear = ata_bmdma_irq_clear, |
| 196 | |
| 197 | .port_start = ata_port_start, |
| 198 | .port_stop = ata_port_stop, |
| 199 | .host_stop = ata_host_stop |
| 200 | }; |
| 201 | |
| 202 | /* |
| 203 | * Promise 20230C and 20620 support |
| 204 | * |
| 205 | * This controller supports PIO0 to PIO2. We set PIO timings conservatively to |
| 206 | * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to |
| 207 | * controller and PIO'd to the host and not supported. |
| 208 | */ |
| 209 | |
| 210 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 211 | { |
| 212 | int tries = 5; |
| 213 | int pio = adev->pio_mode - XFER_PIO_0; |
| 214 | u8 rt; |
| 215 | unsigned long flags; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 216 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 217 | /* Safe as UP only. Force I/Os to occur together */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 218 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 219 | local_irq_save(flags); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 220 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 221 | /* Unlock the control interface */ |
| 222 | do |
| 223 | { |
| 224 | inb(0x1F5); |
| 225 | outb(inb(0x1F2) | 0x80, 0x1F2); |
| 226 | inb(0x1F2); |
| 227 | inb(0x3F6); |
| 228 | inb(0x3F6); |
| 229 | inb(0x1F2); |
| 230 | inb(0x1F2); |
| 231 | } |
| 232 | while((inb(0x1F2) & 0x80) && --tries); |
| 233 | |
| 234 | local_irq_restore(flags); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 235 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 236 | outb(inb(0x1F4) & 0x07, 0x1F4); |
| 237 | |
| 238 | rt = inb(0x1F3); |
| 239 | rt &= 0x07 << (3 * adev->devno); |
| 240 | if (pio) |
| 241 | rt |= (1 + 3 * pio) << (3 * adev->devno); |
| 242 | |
| 243 | udelay(100); |
| 244 | outb(inb(0x1F2) | 0x01, 0x1F2); |
| 245 | udelay(100); |
| 246 | inb(0x1F5); |
| 247 | |
| 248 | } |
| 249 | |
| 250 | static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data) |
| 251 | { |
| 252 | struct ata_port *ap = adev->ap; |
| 253 | int slop = buflen & 3; |
| 254 | unsigned long flags; |
| 255 | |
| 256 | if (ata_id_has_dword_io(adev->id)) { |
| 257 | local_irq_save(flags); |
| 258 | |
| 259 | /* Perform the 32bit I/O synchronization sequence */ |
| 260 | inb(ap->ioaddr.nsect_addr); |
| 261 | inb(ap->ioaddr.nsect_addr); |
| 262 | inb(ap->ioaddr.nsect_addr); |
| 263 | |
| 264 | /* Now the data */ |
| 265 | |
| 266 | if (write_data) |
| 267 | outsl(ap->ioaddr.data_addr, buf, buflen >> 2); |
| 268 | else |
| 269 | insl(ap->ioaddr.data_addr, buf, buflen >> 2); |
| 270 | |
| 271 | if (unlikely(slop)) { |
| 272 | u32 pad; |
| 273 | if (write_data) { |
| 274 | memcpy(&pad, buf + buflen - slop, slop); |
| 275 | outl(le32_to_cpu(pad), ap->ioaddr.data_addr); |
| 276 | } else { |
| 277 | pad = cpu_to_le16(inl(ap->ioaddr.data_addr)); |
| 278 | memcpy(buf + buflen - slop, &pad, slop); |
| 279 | } |
| 280 | } |
| 281 | local_irq_restore(flags); |
| 282 | } |
| 283 | else |
| 284 | ata_pio_data_xfer_noirq(adev, buf, buflen, write_data); |
| 285 | } |
| 286 | |
| 287 | static struct ata_port_operations pdc20230_port_ops = { |
| 288 | .set_piomode = pdc20230_set_piomode, |
| 289 | |
| 290 | .port_disable = ata_port_disable, |
| 291 | .tf_load = ata_tf_load, |
| 292 | .tf_read = ata_tf_read, |
| 293 | .check_status = ata_check_status, |
| 294 | .exec_command = ata_exec_command, |
| 295 | .dev_select = ata_std_dev_select, |
| 296 | |
| 297 | .error_handler = ata_bmdma_error_handler, |
| 298 | |
| 299 | .qc_prep = ata_qc_prep, |
| 300 | .qc_issue = ata_qc_issue_prot, |
Jeff Garzik | bda3028 | 2006-09-27 05:41:13 -0400 | [diff] [blame] | 301 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 302 | .data_xfer = pdc_data_xfer_vlb, |
| 303 | |
| 304 | .irq_handler = ata_interrupt, |
| 305 | .irq_clear = ata_bmdma_irq_clear, |
| 306 | |
| 307 | .port_start = ata_port_start, |
| 308 | .port_stop = ata_port_stop, |
| 309 | .host_stop = ata_host_stop |
| 310 | }; |
| 311 | |
| 312 | /* |
| 313 | * Holtek 6560A support |
| 314 | * |
| 315 | * This controller supports PIO0 to PIO2 (no IORDY even though higher timings |
| 316 | * can be loaded). |
| 317 | */ |
| 318 | |
| 319 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 320 | { |
| 321 | u8 active, recover; |
| 322 | struct ata_timing t; |
| 323 | |
| 324 | /* Get the timing data in cycles. For now play safe at 50Mhz */ |
| 325 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
| 326 | |
| 327 | active = FIT(t.active, 2, 15); |
| 328 | recover = FIT(t.recover, 4, 15); |
| 329 | |
| 330 | inb(0x3E6); |
| 331 | inb(0x3E6); |
| 332 | inb(0x3E6); |
| 333 | inb(0x3E6); |
| 334 | |
| 335 | outb(recover << 4 | active, ap->ioaddr.device_addr); |
| 336 | inb(ap->ioaddr.status_addr); |
| 337 | } |
| 338 | |
| 339 | static struct ata_port_operations ht6560a_port_ops = { |
| 340 | .set_piomode = ht6560a_set_piomode, |
| 341 | |
| 342 | .port_disable = ata_port_disable, |
| 343 | .tf_load = ata_tf_load, |
| 344 | .tf_read = ata_tf_read, |
| 345 | .check_status = ata_check_status, |
| 346 | .exec_command = ata_exec_command, |
| 347 | .dev_select = ata_std_dev_select, |
| 348 | |
| 349 | .error_handler = ata_bmdma_error_handler, |
| 350 | |
| 351 | .qc_prep = ata_qc_prep, |
| 352 | .qc_issue = ata_qc_issue_prot, |
Jeff Garzik | bda3028 | 2006-09-27 05:41:13 -0400 | [diff] [blame] | 353 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 354 | .data_xfer = ata_pio_data_xfer, /* Check vlb/noirq */ |
| 355 | |
| 356 | .irq_handler = ata_interrupt, |
| 357 | .irq_clear = ata_bmdma_irq_clear, |
| 358 | |
| 359 | .port_start = ata_port_start, |
| 360 | .port_stop = ata_port_stop, |
| 361 | .host_stop = ata_host_stop |
| 362 | }; |
| 363 | |
| 364 | /* |
| 365 | * Holtek 6560B support |
| 366 | * |
| 367 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting |
| 368 | * unless we see an ATAPI device in which case we force it off. |
| 369 | * |
| 370 | * FIXME: need to implement 2nd channel support. |
| 371 | */ |
| 372 | |
| 373 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 374 | { |
| 375 | u8 active, recover; |
| 376 | struct ata_timing t; |
| 377 | |
| 378 | /* Get the timing data in cycles. For now play safe at 50Mhz */ |
| 379 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
| 380 | |
| 381 | active = FIT(t.active, 2, 15); |
| 382 | recover = FIT(t.recover, 2, 16); |
| 383 | recover &= 0x15; |
| 384 | |
| 385 | inb(0x3E6); |
| 386 | inb(0x3E6); |
| 387 | inb(0x3E6); |
| 388 | inb(0x3E6); |
| 389 | |
| 390 | outb(recover << 4 | active, ap->ioaddr.device_addr); |
| 391 | |
| 392 | if (adev->class != ATA_DEV_ATA) { |
| 393 | u8 rconf = inb(0x3E6); |
| 394 | if (rconf & 0x24) { |
| 395 | rconf &= ~ 0x24; |
| 396 | outb(rconf, 0x3E6); |
| 397 | } |
| 398 | } |
| 399 | inb(ap->ioaddr.status_addr); |
| 400 | } |
| 401 | |
| 402 | static struct ata_port_operations ht6560b_port_ops = { |
| 403 | .set_piomode = ht6560b_set_piomode, |
| 404 | |
| 405 | .port_disable = ata_port_disable, |
| 406 | .tf_load = ata_tf_load, |
| 407 | .tf_read = ata_tf_read, |
| 408 | .check_status = ata_check_status, |
| 409 | .exec_command = ata_exec_command, |
| 410 | .dev_select = ata_std_dev_select, |
| 411 | |
| 412 | .error_handler = ata_bmdma_error_handler, |
| 413 | |
| 414 | .qc_prep = ata_qc_prep, |
| 415 | .qc_issue = ata_qc_issue_prot, |
Jeff Garzik | bda3028 | 2006-09-27 05:41:13 -0400 | [diff] [blame] | 416 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 417 | .data_xfer = ata_pio_data_xfer, /* FIXME: Check 32bit and noirq */ |
| 418 | |
| 419 | .irq_handler = ata_interrupt, |
| 420 | .irq_clear = ata_bmdma_irq_clear, |
| 421 | |
| 422 | .port_start = ata_port_start, |
| 423 | .port_stop = ata_port_stop, |
| 424 | .host_stop = ata_host_stop |
| 425 | }; |
| 426 | |
| 427 | /* |
| 428 | * Opti core chipset helpers |
| 429 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 430 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 431 | /** |
| 432 | * opti_syscfg - read OPTI chipset configuration |
| 433 | * @reg: Configuration register to read |
| 434 | * |
| 435 | * Returns the value of an OPTI system board configuration register. |
| 436 | */ |
| 437 | |
| 438 | static u8 opti_syscfg(u8 reg) |
| 439 | { |
| 440 | unsigned long flags; |
| 441 | u8 r; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 442 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 443 | /* Uniprocessor chipset and must force cycles adjancent */ |
| 444 | local_irq_save(flags); |
| 445 | outb(reg, 0x22); |
| 446 | r = inb(0x24); |
| 447 | local_irq_restore(flags); |
| 448 | return r; |
| 449 | } |
| 450 | |
| 451 | /* |
| 452 | * Opti 82C611A |
| 453 | * |
| 454 | * This controller supports PIO0 to PIO3. |
| 455 | */ |
| 456 | |
| 457 | static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 458 | { |
| 459 | u8 active, recover, setup; |
| 460 | struct ata_timing t; |
| 461 | struct ata_device *pair = ata_dev_pair(adev); |
| 462 | int clock; |
| 463 | int khz[4] = { 50000, 40000, 33000, 25000 }; |
| 464 | u8 rc; |
| 465 | |
| 466 | /* Enter configuration mode */ |
| 467 | inw(ap->ioaddr.error_addr); |
| 468 | inw(ap->ioaddr.error_addr); |
| 469 | outb(3, ap->ioaddr.nsect_addr); |
| 470 | |
| 471 | /* Read VLB clock strapping */ |
| 472 | clock = 1000000000 / khz[inb(ap->ioaddr.lbah_addr) & 0x03]; |
| 473 | |
| 474 | /* Get the timing data in cycles */ |
| 475 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
| 476 | |
| 477 | /* Setup timing is shared */ |
| 478 | if (pair) { |
| 479 | struct ata_timing tp; |
| 480 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); |
| 481 | |
| 482 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
| 483 | } |
| 484 | |
| 485 | active = FIT(t.active, 2, 17) - 2; |
| 486 | recover = FIT(t.recover, 1, 16) - 1; |
| 487 | setup = FIT(t.setup, 1, 4) - 1; |
| 488 | |
| 489 | /* Select the right timing bank for write timing */ |
| 490 | rc = inb(ap->ioaddr.lbal_addr); |
| 491 | rc &= 0x7F; |
| 492 | rc |= (adev->devno << 7); |
| 493 | outb(rc, ap->ioaddr.lbal_addr); |
| 494 | |
| 495 | /* Write the timings */ |
| 496 | outb(active << 4 | recover, ap->ioaddr.error_addr); |
| 497 | |
| 498 | /* Select the right bank for read timings, also |
| 499 | load the shared timings for address */ |
| 500 | rc = inb(ap->ioaddr.device_addr); |
| 501 | rc &= 0xC0; |
| 502 | rc |= adev->devno; /* Index select */ |
| 503 | rc |= (setup << 4) | 0x04; |
| 504 | outb(rc, ap->ioaddr.device_addr); |
| 505 | |
| 506 | /* Load the read timings */ |
| 507 | outb(active << 4 | recover, ap->ioaddr.data_addr); |
| 508 | |
| 509 | /* Ensure the timing register mode is right */ |
| 510 | rc = inb (ap->ioaddr.lbal_addr); |
| 511 | rc &= 0x73; |
| 512 | rc |= 0x84; |
| 513 | outb(rc, ap->ioaddr.lbal_addr); |
| 514 | |
| 515 | /* Exit command mode */ |
| 516 | outb(0x83, ap->ioaddr.nsect_addr); |
| 517 | } |
| 518 | |
| 519 | |
| 520 | static struct ata_port_operations opti82c611a_port_ops = { |
| 521 | .set_piomode = opti82c611a_set_piomode, |
| 522 | |
| 523 | .port_disable = ata_port_disable, |
| 524 | .tf_load = ata_tf_load, |
| 525 | .tf_read = ata_tf_read, |
| 526 | .check_status = ata_check_status, |
| 527 | .exec_command = ata_exec_command, |
| 528 | .dev_select = ata_std_dev_select, |
| 529 | |
| 530 | .error_handler = ata_bmdma_error_handler, |
| 531 | |
| 532 | .qc_prep = ata_qc_prep, |
| 533 | .qc_issue = ata_qc_issue_prot, |
Jeff Garzik | bda3028 | 2006-09-27 05:41:13 -0400 | [diff] [blame] | 534 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 535 | .data_xfer = ata_pio_data_xfer, |
| 536 | |
| 537 | .irq_handler = ata_interrupt, |
| 538 | .irq_clear = ata_bmdma_irq_clear, |
| 539 | |
| 540 | .port_start = ata_port_start, |
| 541 | .port_stop = ata_port_stop, |
| 542 | .host_stop = ata_host_stop |
| 543 | }; |
| 544 | |
| 545 | /* |
| 546 | * Opti 82C465MV |
| 547 | * |
| 548 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB |
| 549 | * version is dual channel but doesn't have a lot of unique registers. |
| 550 | */ |
| 551 | |
| 552 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 553 | { |
| 554 | u8 active, recover, setup; |
| 555 | struct ata_timing t; |
| 556 | struct ata_device *pair = ata_dev_pair(adev); |
| 557 | int clock; |
| 558 | int khz[4] = { 50000, 40000, 33000, 25000 }; |
| 559 | u8 rc; |
| 560 | u8 sysclk; |
| 561 | |
| 562 | /* Get the clock */ |
| 563 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ |
| 564 | |
| 565 | /* Enter configuration mode */ |
| 566 | inw(ap->ioaddr.error_addr); |
| 567 | inw(ap->ioaddr.error_addr); |
| 568 | outb(3, ap->ioaddr.nsect_addr); |
| 569 | |
| 570 | /* Read VLB clock strapping */ |
| 571 | clock = 1000000000 / khz[sysclk]; |
| 572 | |
| 573 | /* Get the timing data in cycles */ |
| 574 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
| 575 | |
| 576 | /* Setup timing is shared */ |
| 577 | if (pair) { |
| 578 | struct ata_timing tp; |
| 579 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); |
| 580 | |
| 581 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
| 582 | } |
| 583 | |
| 584 | active = FIT(t.active, 2, 17) - 2; |
| 585 | recover = FIT(t.recover, 1, 16) - 1; |
| 586 | setup = FIT(t.setup, 1, 4) - 1; |
| 587 | |
| 588 | /* Select the right timing bank for write timing */ |
| 589 | rc = inb(ap->ioaddr.lbal_addr); |
| 590 | rc &= 0x7F; |
| 591 | rc |= (adev->devno << 7); |
| 592 | outb(rc, ap->ioaddr.lbal_addr); |
| 593 | |
| 594 | /* Write the timings */ |
| 595 | outb(active << 4 | recover, ap->ioaddr.error_addr); |
| 596 | |
| 597 | /* Select the right bank for read timings, also |
| 598 | load the shared timings for address */ |
| 599 | rc = inb(ap->ioaddr.device_addr); |
| 600 | rc &= 0xC0; |
| 601 | rc |= adev->devno; /* Index select */ |
| 602 | rc |= (setup << 4) | 0x04; |
| 603 | outb(rc, ap->ioaddr.device_addr); |
| 604 | |
| 605 | /* Load the read timings */ |
| 606 | outb(active << 4 | recover, ap->ioaddr.data_addr); |
| 607 | |
| 608 | /* Ensure the timing register mode is right */ |
| 609 | rc = inb (ap->ioaddr.lbal_addr); |
| 610 | rc &= 0x73; |
| 611 | rc |= 0x84; |
| 612 | outb(rc, ap->ioaddr.lbal_addr); |
| 613 | |
| 614 | /* Exit command mode */ |
| 615 | outb(0x83, ap->ioaddr.nsect_addr); |
| 616 | |
| 617 | /* We need to know this for quad device on the MVB */ |
| 618 | ap->host->private_data = ap; |
| 619 | } |
| 620 | |
| 621 | /** |
| 622 | * opt82c465mv_qc_issue_prot - command issue |
| 623 | * @qc: command pending |
| 624 | * |
| 625 | * Called when the libata layer is about to issue a command. We wrap |
| 626 | * this interface so that we can load the correct ATA timings. The |
| 627 | * MVB has a single set of timing registers and these are shared |
| 628 | * across channels. As there are two registers we really ought to |
| 629 | * track the last two used values as a sort of register window. For |
| 630 | * now we just reload on a channel switch. On the single channel |
| 631 | * setup this condition never fires so we do nothing extra. |
| 632 | * |
| 633 | * FIXME: dual channel needs ->serialize support |
| 634 | */ |
| 635 | |
| 636 | static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc) |
| 637 | { |
| 638 | struct ata_port *ap = qc->ap; |
| 639 | struct ata_device *adev = qc->dev; |
| 640 | |
| 641 | /* If timings are set and for the wrong channel (2nd test is |
| 642 | due to a libata shortcoming and will eventually go I hope) */ |
| 643 | if (ap->host->private_data != ap->host |
| 644 | && ap->host->private_data != NULL) |
| 645 | opti82c46x_set_piomode(ap, adev); |
| 646 | |
| 647 | return ata_qc_issue_prot(qc); |
| 648 | } |
| 649 | |
| 650 | static struct ata_port_operations opti82c46x_port_ops = { |
| 651 | .set_piomode = opti82c46x_set_piomode, |
| 652 | |
| 653 | .port_disable = ata_port_disable, |
| 654 | .tf_load = ata_tf_load, |
| 655 | .tf_read = ata_tf_read, |
| 656 | .check_status = ata_check_status, |
| 657 | .exec_command = ata_exec_command, |
| 658 | .dev_select = ata_std_dev_select, |
| 659 | |
| 660 | .error_handler = ata_bmdma_error_handler, |
| 661 | |
| 662 | .qc_prep = ata_qc_prep, |
| 663 | .qc_issue = opti82c46x_qc_issue_prot, |
Jeff Garzik | bda3028 | 2006-09-27 05:41:13 -0400 | [diff] [blame] | 664 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 665 | .data_xfer = ata_pio_data_xfer, |
| 666 | |
| 667 | .irq_handler = ata_interrupt, |
| 668 | .irq_clear = ata_bmdma_irq_clear, |
| 669 | |
| 670 | .port_start = ata_port_start, |
| 671 | .port_stop = ata_port_stop, |
| 672 | .host_stop = ata_host_stop |
| 673 | }; |
| 674 | |
| 675 | |
| 676 | /** |
| 677 | * legacy_init_one - attach a legacy interface |
| 678 | * @port: port number |
| 679 | * @io: I/O port start |
| 680 | * @ctrl: control port |
| 681 | * @irq: interrupt line |
| 682 | * |
| 683 | * Register an ISA bus IDE interface. Such interfaces are PIO and we |
| 684 | * assume do not support IRQ sharing. |
| 685 | */ |
| 686 | |
| 687 | static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq) |
| 688 | { |
| 689 | struct legacy_data *ld = &legacy_data[nr_legacy_host]; |
| 690 | struct ata_probe_ent ae; |
| 691 | struct platform_device *pdev; |
| 692 | int ret = -EBUSY; |
| 693 | struct ata_port_operations *ops = &legacy_port_ops; |
| 694 | int pio_modes = pio_mask; |
| 695 | u32 mask = (1 << port); |
| 696 | |
| 697 | if (request_region(io, 8, "pata_legacy") == NULL) |
| 698 | return -EBUSY; |
| 699 | if (request_region(ctrl, 1, "pata_legacy") == NULL) |
| 700 | goto fail_io; |
| 701 | |
| 702 | pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0); |
Akinobu Mita | 9825d73 | 2006-12-15 13:08:51 -0800 | [diff] [blame] | 703 | if (IS_ERR(pdev)) { |
| 704 | ret = PTR_ERR(pdev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 705 | goto fail_dev; |
Akinobu Mita | 9825d73 | 2006-12-15 13:08:51 -0800 | [diff] [blame] | 706 | } |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 707 | |
| 708 | if (ht6560a & mask) { |
| 709 | ops = &ht6560a_port_ops; |
| 710 | pio_modes = 0x07; |
| 711 | } |
| 712 | if (ht6560b & mask) { |
| 713 | ops = &ht6560b_port_ops; |
| 714 | pio_modes = 0x1F; |
| 715 | } |
| 716 | if (opti82c611a & mask) { |
| 717 | ops = &opti82c611a_port_ops; |
| 718 | pio_modes = 0x0F; |
| 719 | } |
| 720 | if (opti82c46x & mask) { |
| 721 | ops = &opti82c46x_port_ops; |
| 722 | pio_modes = 0x0F; |
| 723 | } |
| 724 | |
| 725 | /* Probe for automatically detectable controllers */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 726 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 727 | if (io == 0x1F0 && ops == &legacy_port_ops) { |
| 728 | unsigned long flags; |
| 729 | |
| 730 | local_irq_save(flags); |
| 731 | |
| 732 | /* Probes */ |
| 733 | inb(0x1F5); |
| 734 | outb(inb(0x1F2) | 0x80, 0x1F2); |
| 735 | inb(0x1F2); |
| 736 | inb(0x3F6); |
| 737 | inb(0x3F6); |
| 738 | inb(0x1F2); |
| 739 | inb(0x1F2); |
| 740 | |
| 741 | if ((inb(0x1F2) & 0x80) == 0) { |
| 742 | /* PDC20230c or 20630 ? */ |
| 743 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n"); |
| 744 | pio_modes = 0x07; |
| 745 | ops = &pdc20230_port_ops; |
| 746 | udelay(100); |
| 747 | inb(0x1F5); |
| 748 | } else { |
| 749 | outb(0x55, 0x1F2); |
| 750 | inb(0x1F2); |
| 751 | inb(0x1F2); |
| 752 | if (inb(0x1F2) == 0x00) { |
| 753 | printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n"); |
| 754 | } |
| 755 | } |
| 756 | local_irq_restore(flags); |
| 757 | } |
| 758 | |
| 759 | |
| 760 | /* Chip does mode setting by command snooping */ |
| 761 | if (ops == &legacy_port_ops && (autospeed & mask)) |
| 762 | ops = &simple_port_ops; |
| 763 | memset(&ae, 0, sizeof(struct ata_probe_ent)); |
| 764 | INIT_LIST_HEAD(&ae.node); |
| 765 | ae.dev = &pdev->dev; |
| 766 | ae.port_ops = ops; |
| 767 | ae.sht = &legacy_sht; |
| 768 | ae.n_ports = 1; |
| 769 | ae.pio_mask = pio_modes; |
| 770 | ae.irq = irq; |
| 771 | ae.irq_flags = 0; |
| 772 | ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST; |
| 773 | ae.port[0].cmd_addr = io; |
| 774 | ae.port[0].altstatus_addr = ctrl; |
| 775 | ae.port[0].ctl_addr = ctrl; |
| 776 | ata_std_ports(&ae.port[0]); |
| 777 | ae.private_data = ld; |
| 778 | |
| 779 | ret = ata_device_add(&ae); |
| 780 | if (ret == 0) { |
| 781 | ret = -ENODEV; |
| 782 | goto fail; |
| 783 | } |
| 784 | legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev); |
| 785 | ld->platform_dev = pdev; |
| 786 | return 0; |
| 787 | |
| 788 | fail: |
| 789 | platform_device_unregister(pdev); |
| 790 | fail_dev: |
| 791 | release_region(ctrl, 1); |
| 792 | fail_io: |
| 793 | release_region(io, 8); |
| 794 | return ret; |
| 795 | } |
| 796 | |
| 797 | /** |
| 798 | * legacy_check_special_cases - ATA special cases |
| 799 | * @p: PCI device to check |
| 800 | * @master: set this if we find an ATA master |
| 801 | * @master: set this if we find an ATA secondary |
| 802 | * |
| 803 | * A small number of vendors implemented early PCI ATA interfaces on bridge logic |
| 804 | * without the ATA interface being PCI visible. Where we have a matching PCI driver |
| 805 | * we must skip the relevant device here. If we don't know about it then the legacy |
| 806 | * driver is the right driver anyway. |
| 807 | */ |
| 808 | |
| 809 | static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary) |
| 810 | { |
| 811 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ |
| 812 | if (p->vendor == 0x1078 && p->device == 0x0000) { |
| 813 | *primary = *secondary = 1; |
| 814 | return; |
| 815 | } |
| 816 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ |
| 817 | if (p->vendor == 0x1078 && p->device == 0x0002) { |
| 818 | *primary = *secondary = 1; |
| 819 | return; |
| 820 | } |
| 821 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ |
| 822 | if (p->vendor == 0x8086 && p->device == 0x1234) { |
| 823 | u16 r; |
| 824 | pci_read_config_word(p, 0x6C, &r); |
| 825 | if (r & 0x8000) { /* ATA port enabled */ |
| 826 | if (r & 0x4000) |
| 827 | *secondary = 1; |
| 828 | else |
| 829 | *primary = 1; |
| 830 | } |
| 831 | return; |
| 832 | } |
| 833 | } |
| 834 | |
| 835 | |
| 836 | /** |
| 837 | * legacy_init - attach legacy interfaces |
| 838 | * |
| 839 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. |
| 840 | * Right now we do not scan the ide0 and ide1 address but should do so |
| 841 | * for non PCI systems or systems with no PCI IDE legacy mode devices. |
| 842 | * If you fix that note there are special cases to consider like VLB |
| 843 | * drivers and CS5510/20. |
| 844 | */ |
| 845 | |
| 846 | static __init int legacy_init(void) |
| 847 | { |
| 848 | int i; |
| 849 | int ct = 0; |
| 850 | int primary = 0; |
| 851 | int secondary = 0; |
| 852 | int last_port = NR_HOST; |
| 853 | |
| 854 | struct pci_dev *p = NULL; |
| 855 | |
| 856 | for_each_pci_dev(p) { |
| 857 | int r; |
| 858 | /* Check for any overlap of the system ATA mappings. Native mode controllers |
| 859 | stuck on these addresses or some devices in 'raid' mode won't be found by |
| 860 | the storage class test */ |
| 861 | for (r = 0; r < 6; r++) { |
| 862 | if (pci_resource_start(p, r) == 0x1f0) |
| 863 | primary = 1; |
| 864 | if (pci_resource_start(p, r) == 0x170) |
| 865 | secondary = 1; |
| 866 | } |
| 867 | /* Check for special cases */ |
| 868 | legacy_check_special_cases(p, &primary, &secondary); |
| 869 | |
| 870 | /* If PCI bus is present then don't probe for tertiary legacy ports */ |
| 871 | if (probe_all == 0) |
| 872 | last_port = 2; |
| 873 | } |
| 874 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 875 | /* If an OPTI 82C46X is present find out where the channels are */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 876 | if (opti82c46x) { |
| 877 | static const char *optis[4] = { |
| 878 | "3/463MV", "5MV", |
| 879 | "5MVA", "5MVB" |
| 880 | }; |
| 881 | u8 chans = 1; |
| 882 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 883 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 884 | opti82c46x = 3; /* Assume master and slave first */ |
| 885 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]); |
| 886 | if (ctrl == 3) |
| 887 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; |
| 888 | ctrl = opti_syscfg(0xAC); |
| 889 | /* Check enabled and this port is the 465MV port. On the |
| 890 | MVB we may have two channels */ |
| 891 | if (ctrl & 8) { |
| 892 | if (ctrl & 4) |
| 893 | opti82c46x = 2; /* Slave */ |
| 894 | else |
| 895 | opti82c46x = 1; /* Master */ |
| 896 | if (chans == 2) |
| 897 | opti82c46x = 3; /* Master and Slave */ |
| 898 | } /* Slave only */ |
| 899 | else if (chans == 1) |
| 900 | opti82c46x = 1; |
| 901 | } |
| 902 | |
| 903 | for (i = 0; i < last_port; i++) { |
| 904 | /* Skip primary if we have seen a PCI one */ |
| 905 | if (i == 0 && primary == 1) |
| 906 | continue; |
| 907 | /* Skip secondary if we have seen a PCI one */ |
| 908 | if (i == 1 && secondary == 1) |
| 909 | continue; |
| 910 | if (legacy_init_one(i, legacy_port[i], |
| 911 | legacy_port[i] + 0x0206, |
| 912 | legacy_irq[i]) == 0) |
| 913 | ct++; |
| 914 | } |
| 915 | if (ct != 0) |
| 916 | return 0; |
| 917 | return -ENODEV; |
| 918 | } |
| 919 | |
| 920 | static __exit void legacy_exit(void) |
| 921 | { |
| 922 | int i; |
| 923 | |
| 924 | for (i = 0; i < nr_legacy_host; i++) { |
| 925 | struct legacy_data *ld = &legacy_data[i]; |
| 926 | struct ata_port *ap =legacy_host[i]->ports[0]; |
| 927 | unsigned long io = ap->ioaddr.cmd_addr; |
| 928 | unsigned long ctrl = ap->ioaddr.ctl_addr; |
| 929 | ata_host_remove(legacy_host[i]); |
| 930 | platform_device_unregister(ld->platform_dev); |
| 931 | if (ld->timing) |
| 932 | release_region(ld->timing, 2); |
| 933 | release_region(io, 8); |
| 934 | release_region(ctrl, 1); |
| 935 | } |
| 936 | } |
| 937 | |
| 938 | MODULE_AUTHOR("Alan Cox"); |
| 939 | MODULE_DESCRIPTION("low-level driver for legacy ATA"); |
| 940 | MODULE_LICENSE("GPL"); |
| 941 | MODULE_VERSION(DRV_VERSION); |
| 942 | |
| 943 | module_param(probe_all, int, 0); |
| 944 | module_param(autospeed, int, 0); |
| 945 | module_param(ht6560a, int, 0); |
| 946 | module_param(ht6560b, int, 0); |
| 947 | module_param(opti82c611a, int, 0); |
| 948 | module_param(opti82c46x, int, 0); |
| 949 | module_param(pio_mask, int, 0); |
| 950 | |
| 951 | module_init(legacy_init); |
| 952 | module_exit(legacy_exit); |
| 953 | |