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Adrian Salido-Moreno45228942012-08-13 16:19:18 -07001Qualcomm MDSS MDP
2
3MDSS is Mobile Display SubSystem which implements Linux framebuffer APIs to
4drive user interface to different panel interfaces. MDP driver is the core of
5MDSS which manage all data paths to different panel interfaces.
6
7Required properties
8- compatible : Must be "qcom,mdss_mdp"
9- reg : offset and length of the register set for the device.
10- reg-names : names to refer to register sets related to this device
11- interrupts : Interrupt associated with MDSS.
12- vdd-supply : Phandle for vdd regulator device node.
Adrian Salido-Moreno2a228652012-10-01 11:17:33 -070013- qcom,max-clk-rate: Specify maximum MDP core clock rate in hz that this
14 device supports.
Sree Sesha Aravind Vadrevu8be4b982013-01-04 14:09:20 -080015- qcom,mdss-pipe-vig-off: Array of offset for MDP source surface pipes of
16 type VIG, the offsets are calculated from
17 register "mdp_phys" defined in reg property.
18 The number of offsets defined here should
19 reflect the amount of VIG pipes that can be
20 active in MDP for this configuration.
21- qcom,mdss-pipe-vig-fetch-id: Array of shared memory pool fetch ids
22 corresponding to the VIG pipe offsets defined in
23 previous property, the amount of fetch ids
24 defined should match the number of offsets
25 defined in property: qcom,mdss-pipe-vig-off
26- qcom,mdss-pipe-rgb-off: Array of offsets for MDP source surface pipes of
27 type RGB, the offsets are calculated from
28 register "mdp_phys" defined in reg property.
29 The number of offsets defined here should
30 reflect the amount of RGB pipes that can be
31 active in MDP for this configuration.
32- qcom,mdss-pipe-rgb-fetch-id: Array of shared memory pool fetch ids
33 corresponding to the RGB pipe offsets defined in
34 previous property, the amount of fetch ids
35 defined should match the number of offsets
36 defined in property: qcom,mdss-pipe-rgb-off
37- qcom,mdss-pipe-dma-off: Array of offsets for MDP source surface pipes of
38 type DMA, the offsets are calculated from
39 register "mdp_phys" defined in reg property.
40 The number of offsets defined here should
41 reflect the amount of DMA pipes that can be
42 active in MDP for this configuration.
43- qcom,mdss-pipe-dma-fetch-id: Array of shared memory pool fetch ids
44 corresponding to the DMA pipe offsets defined in
45 previous property, the amount of fetch ids
46 defined should match the number of offsets
47 defined in property: qcom,mdss-pipe-dma-off
Sree Sesha Aravind Vadrevu6dc413b2013-02-27 17:02:04 -080048- qcom,mdss-smp-data: Array of shared memory pool data. There should
49 be only two values in this property. The first
50 value corresponds to the number of smp blocks
51 and the second is the size of each block
52 present in the mdss hardware.
Sree Sesha Aravind Vadrevu8be4b982013-01-04 14:09:20 -080053- qcom,mdss-ctl-off: Array of offset addresses for the available ctl
54 hw blocks within MDP, these offsets are
55 calculated from register "mdp_phys" defined in
56 reg property. The number of ctl offsets defined
57 here should reflect the number of control paths
58 that can be configured concurrently on MDP for
59 this configuration.
60- qcom,mdss-wb-off: Array of offset addresses for the progammable
61 writeback blocks within MDP. The number of
62 offsets defined should match the number of ctl
63 blocks defined in property: qcom,mdss-ctl-off
64- qcom,mdss-mixer-intf-off: Array of offset addresses for the available
65 mixer blocks that can drive data to panel
66 interfaces.
67 These offsets are be calculated from register
68 "mdp_phys" defined in reg property.
69 The number of offsets defined should reflect the
70 amount of mixers that can drive data to a panel
71 interface.
72- qcom,mdss-dspp-off: Array of offset addresses for the available dspp
73 blocks. These offsets are calculated from
74 regsiter "mdp_phys" defined in reg property.
75 The number of dspp blocks should match the
76 number of mixers driving data to interface
77 defined in property: qcom,mdss-mixer-intf-off
Siddhartha Agrawal98f415c2013-03-26 16:58:01 -070078- qcom,mdss-pingpong-off: Array of offset addresses for the available
79 pingpong blocks. These offsets are calculated
80 from regsiter "mdp_phys" defined in reg property.
81 The number of pingpong blocks should match the
82 number of mixers driving data to interface
83 defined in property: qcom,mdss-mixer-intf-off
Sree Sesha Aravind Vadrevu8be4b982013-01-04 14:09:20 -080084- qcom,mdss-mixer-wb-off: Array of offset addresses for the available
85 mixer blocks that can be drive data to writeback
86 block. These offsets will be calculated from
87 register "mdp_phys" defined in reg property.
88 The number of writeback mixer offsets defined
89 should reflect the number of mixers that can
90 drive data to a writeback block.
Adrian Salido-Moreno26045502013-02-05 22:46:01 -080091- qcom,mdss-intf-off: Array of offset addresses for the available MDP
92 video interface blocks that can drive data to a
93 panel controller through timing engine.
94 The offsets are calculated from "mdp_phys"
95 defined in reg property. The number of offsets
96 defiend should reflect the number of progammable
Manoj Raob182d132013-06-19 17:37:50 -070097 interface blocks available in hardware.
98- qcom,mdss-pref-prim-intf: A string which indicates the configured hardware
99 interface between MDP and the primary panel.
100 Individual panel controller drivers initialize
101 hardware based on this property.
102 Based on the interfaces supported at present,
103 possible values are:
104 - "dsi"
105 - "edp"
106 - "hdmi"
Adrian Salido-Moreno4fe81062012-12-04 21:05:03 -0800107
Adrian Salido-Morenoe2e742b2013-02-07 01:54:14 -0800108Optional properties:
Chandan Uddaraju29b95f42013-08-27 20:03:14 -0700109- vdd-cx-supply : Phandle for vdd CX regulator device node.
Ujwal Patel954bbbc92013-08-07 21:52:15 -0700110- batfet-supply : Phandle for battery FET regulator device node.
Adrian Salido-Morenoe2e742b2013-02-07 01:54:14 -0800111- qcom,vbif-settings : Array with key-value pairs of constant VBIF register
112 settings used to setup MDSS QoS for optimum performance.
113 The key used should be offset from "vbif_phys" register
114 defined in reg property.
115- qcom,mdp-settings : Array with key-value pairs of constant MDP register
116 settings used to setup MDSS QoS for best performance.
117 The key used should be offset from "mdp_phys" register
118 defined in reg property.
Aravind Venkateswaranc0163532013-03-18 14:17:12 -0700119- qcom,mdss-rot-block-size: The size of a memory block (in pixels) to be used
120 by the rotator. If this property is not specified,
121 then a default value of 128 pixels would be used.
Sree Sesha Aravind Vadrevu10c4d772013-03-28 13:11:12 -0700122- qcom,mdss-has-bwc: Boolean property to indicate the presence of bandwidth
123 compression feature in the rotator.
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700124- qcom,mdss-has-decimation: Boolean property to indicate the presence of
125 decimation feature in fetch.
Carl Vanderlipace4b4b2013-04-24 10:09:49 -0700126- qcom,mdss-ad-off: Array of offset addresses for the available
127 Assertive Display (AD) blocks. These offsets
128 are calculated from the register "mdp_phys"
129 defined in reg property. The number of AD
130 offsets should be less than or equal to the
131 number of mixers driving interfaces defined in
132 property: qcom,mdss-mixer-intf-off. Assumes
133 that AD blocks are aligned with the mixer
134 offsets as well (i.e. the first mixer offset
135 corresponds to the same pathway as the first
136 AD offset).
Sree Sesha Aravind Vadrevuc6deb392013-06-07 15:50:49 -0700137- qcom,mdss-has-wfd-blk: Boolean property to indicate the presence of dedicated
138 writeback wfd block in MDSS as opposed to writeback
139 block that is shared between rotator and wfd.
Mayank Chopra710652b2013-06-12 15:58:04 +0530140- qcom,mdss-smp-mb-per-pipe: Maximum number of shared memory pool blocks
141 restricted for a source surface pipe. If this
142 property is not specified, no such restriction
143 would be applied.
Ujwal Patel0ced4ec2013-09-02 14:33:41 -0700144- qcom,mdss-pipe-rgb-fixed-mmb: Array of indexes describing fixed Memory Macro
145 Blocks (MMBs) for rgb pipes. First value denotes
146 total numbers of MMBs per pipe while values, if
147 any, following first one denotes indexes of MMBs
148 to that RGB pipe.
Mayank Chopra710652b2013-06-12 15:58:04 +0530149
Adrian Salido-Moreno4fe81062012-12-04 21:05:03 -0800150Optional subnodes:
151Child nodes representing the frame buffer virtual devices.
152
153Subnode properties:
154- compatible : Must be "qcom,mdss-fb"
155- cell-index : Index representing frame buffer
Sree Sesha Aravind Vadrevu465accd2013-04-17 18:33:47 -0700156- qcom,mdss-mixer-swap: A boolean property that indicates if the mixer muxes
157 need to be swapped based on the target panel.
158 By default the property is not defined.
Huaibin Yang581fc632013-06-13 17:05:23 -0700159- qcom,mdss-fb-split: Array of splitted framebuffer size. There should
160 be only two values in this property. The values
161 correspond to the left and right size respectively.
162 MDP muxes two mixer output together before sending to
163 the panel interface and these values are used to set
164 each mixer width, so the sum of these two values
165 should be equal to the panel x-resolution.
Adrian Salido-Moreno4fe81062012-12-04 21:05:03 -0800166
Huaibin Yang581fc632013-06-13 17:05:23 -0700167 Note that if the sum of two values is not equal to
168 x-resolution or this subnode itself is not defined
169 in device tree there are two cases: 1)split is not
170 enabled if framebuffer size is less than max mixer
171 width; 2) the defaut even split is enabled if frambuffer
172 size is greater than max mixer width.
Siddhartha Agrawale6de0482013-07-18 16:30:27 -0700173- qcom,memblock-reserve: Specifies the memory location and the size reserved
174 for the framebuffer used to display the splash screen.
175 This property is required whenever the continuous splash
176 screen feature is enabled for the corresponding
177 framebuffer device.
Adrian Salido-Moreno4fe81062012-12-04 21:05:03 -0800178
Adrian Salido-Moreno45228942012-08-13 16:19:18 -0700179Example:
Manoj Rao702a0432013-08-12 22:58:27 -0700180 mdss_mdp: qcom,mdss_mdp@fd900000 {
Adrian Salido-Moreno45228942012-08-13 16:19:18 -0700181 compatible = "qcom,mdss_mdp";
182 reg = <0xfd900000 0x22100>,
183 <0xfd924000 0x1000>;
184 reg-names = "mdp_phys", "vbif_phys";
185 interrupts = <0 72 0>;
186 vdd-supply = <&gdsc_mdss>;
Chandan Uddaraju29b95f42013-08-27 20:03:14 -0700187 vdd-cx-supply = <&pm8841_s2_corner>;
Ujwal Patel954bbbc92013-08-07 21:52:15 -0700188 batfet-supply = <&pm8941_chg_batif>;
Adrian Salido-Moreno2a228652012-10-01 11:17:33 -0700189 qcom,max-clk-rate = <320000000>;
Adrian Salido-Morenoe2e742b2013-02-07 01:54:14 -0800190 qcom,vbif-settings = <0x0004 0x00000001>,
191 <0x00D8 0x00000707>;
192 qcom,mdp-settings = <0x02E0 0x000000AA>,
193 <0x02E4 0x00000055>;
Sree Sesha Aravind Vadrevu8be4b982013-01-04 14:09:20 -0800194 qcom,mdss-pipe-vig-off = <0x00001200 0x00001600
195 0x00001A00>;
196 qcom,mdss-pipe-rgb-off = <0x00001E00 0x00002200
197 0x00002600>;
198 qcom,mdss-pipe-dma-off = <0x00002A00 0x00002E00>;
199 qcom,mdss-pipe-vig-fetch-id = <1 4 7>;
200 qcom,mdss-pipe-rgb-fetch-id = <16 17 18>;
201 qcom,mdss-pipe-dma-fetch-id = <10 13>;
Ujwal Patel0ced4ec2013-09-02 14:33:41 -0700202 qcom,mdss-pipe-rgb-fixed-mmb = <2 0 1>,
203 <2 2 3>,
204 <2 4 5>,
205 <2 6 7>;
Sree Sesha Aravind Vadrevu6dc413b2013-02-27 17:02:04 -0800206 qcom,mdss-smp-data = <22 4096>;
Aravind Venkateswaranc0163532013-03-18 14:17:12 -0700207 qcom,mdss-rot-block-size = <64>;
Mayank Chopra710652b2013-06-12 15:58:04 +0530208 qcom,mdss-smp-mb-per-pipe = <2>;
Manoj Raob182d132013-06-19 17:37:50 -0700209 qcom,mdss-pref-prim-intf = "dsi";
Sree Sesha Aravind Vadrevu10c4d772013-03-28 13:11:12 -0700210 qcom,mdss-has-bwc;
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700211 qcom,mdss-has-decimation;
Sree Sesha Aravind Vadrevuc6deb392013-06-07 15:50:49 -0700212 qcom,mdss-has-wfd-blk;
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700213
Sree Sesha Aravind Vadrevu8be4b982013-01-04 14:09:20 -0800214 qcom,mdss-ctl-off = <0x00000600 0x00000700 0x00000800
215 0x00000900 0x0000A00>;
216 qcom,mdss-mixer-intf-off = <0x00003200 0x00003600
217 0x00003A00>;
218 qcom,mdss-mixer-wb-off = <0x00003E00 0x00004200>;
219 qcom,mdss-dspp-off = <0x00004600 0x00004A00 0x00004E00>;
Siddhartha Agrawal98f415c2013-03-26 16:58:01 -0700220 qcom,mdss-pingpong-off = <0x00012D00 0x00012E00 0x00012F00>;
Sree Sesha Aravind Vadrevu8be4b982013-01-04 14:09:20 -0800221 qcom,mdss-wb-off = <0x00011100 0x00013100 0x00015100
222 0x00017100 0x00019100>;
Adrian Salido-Moreno26045502013-02-05 22:46:01 -0800223 qcom,mdss-intf-off = <0x00021100 0x00021300
224 0x00021500 0x00021700>;
Sree Sesha Aravind Vadrevu8be4b982013-01-04 14:09:20 -0800225
Adrian Salido-Moreno4fe81062012-12-04 21:05:03 -0800226 mdss_fb0: qcom,mdss_fb_primary {
227 cell-index = <0>;
228 compatible = "qcom,mdss-fb";
Sree Sesha Aravind Vadrevu465accd2013-04-17 18:33:47 -0700229 qcom,mdss-mixer-swap;
Huaibin Yang581fc632013-06-13 17:05:23 -0700230 qcom,mdss-fb-split = <480 240>
Adrian Salido-Moreno4fe81062012-12-04 21:05:03 -0800231 };
Adrian Salido-Moreno45228942012-08-13 16:19:18 -0700232 };
233