Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1 | /* |
| 2 | * QLogic QLA41xx NIC HBA Driver |
| 3 | * Copyright (c) 2003-2006 QLogic Corporation |
| 4 | * |
| 5 | * See LICENSE.qlge for copyright and licensing details. |
| 6 | */ |
| 7 | #ifndef _QLGE_H_ |
| 8 | #define _QLGE_H_ |
| 9 | |
| 10 | #include <linux/pci.h> |
| 11 | #include <linux/netdevice.h> |
| 12 | |
| 13 | /* |
| 14 | * General definitions... |
| 15 | */ |
| 16 | #define DRV_NAME "qlge" |
| 17 | #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver " |
| 18 | #define DRV_VERSION "v1.00.00-b3" |
| 19 | |
| 20 | #define PFX "qlge: " |
| 21 | #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \ |
| 22 | do { \ |
| 23 | if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \ |
| 24 | ; \ |
| 25 | else \ |
| 26 | dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \ |
| 27 | "%s: " fmt, __func__, ##args); \ |
| 28 | } while (0) |
| 29 | |
| 30 | #define QLGE_VENDOR_ID 0x1077 |
| 31 | #define QLGE_DEVICE_ID1 0x8012 |
| 32 | #define QLGE_DEVICE_ID 0x8000 |
| 33 | |
| 34 | #define MAX_RX_RINGS 128 |
| 35 | #define MAX_TX_RINGS 128 |
| 36 | |
| 37 | #define NUM_TX_RING_ENTRIES 256 |
| 38 | #define NUM_RX_RING_ENTRIES 256 |
| 39 | |
| 40 | #define NUM_SMALL_BUFFERS 512 |
| 41 | #define NUM_LARGE_BUFFERS 512 |
| 42 | |
| 43 | #define SMALL_BUFFER_SIZE 256 |
| 44 | #define LARGE_BUFFER_SIZE PAGE_SIZE |
| 45 | #define MAX_SPLIT_SIZE 1023 |
| 46 | #define QLGE_SB_PAD 32 |
| 47 | |
| 48 | #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */ |
| 49 | #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */ |
| 50 | #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2) |
| 51 | #define UDELAY_COUNT 3 |
| 52 | #define UDELAY_DELAY 10 |
| 53 | |
| 54 | |
| 55 | #define TX_DESC_PER_IOCB 8 |
| 56 | /* The maximum number of frags we handle is based |
| 57 | * on PAGE_SIZE... |
| 58 | */ |
| 59 | #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */ |
| 60 | #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2) |
Ron Mercer | 4850137 | 2008-10-13 22:55:59 -0700 | [diff] [blame] | 61 | #else /* all other page sizes */ |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 62 | #define TX_DESC_PER_OAL 0 |
| 63 | #endif |
| 64 | |
| 65 | #define DB_PAGE_SIZE 4096 |
| 66 | |
| 67 | /* |
| 68 | * Processor Address Register (PROC_ADDR) bit definitions. |
| 69 | */ |
| 70 | enum { |
| 71 | |
| 72 | /* Misc. stuff */ |
| 73 | MAILBOX_COUNT = 16, |
| 74 | |
| 75 | PROC_ADDR_RDY = (1 << 31), |
| 76 | PROC_ADDR_R = (1 << 30), |
| 77 | PROC_ADDR_ERR = (1 << 29), |
| 78 | PROC_ADDR_DA = (1 << 28), |
| 79 | PROC_ADDR_FUNC0_MBI = 0x00001180, |
| 80 | PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT), |
| 81 | PROC_ADDR_FUNC0_CTL = 0x000011a1, |
| 82 | PROC_ADDR_FUNC2_MBI = 0x00001280, |
| 83 | PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT), |
| 84 | PROC_ADDR_FUNC2_CTL = 0x000012a1, |
| 85 | PROC_ADDR_MPI_RISC = 0x00000000, |
| 86 | PROC_ADDR_MDE = 0x00010000, |
| 87 | PROC_ADDR_REGBLOCK = 0x00020000, |
| 88 | PROC_ADDR_RISC_REG = 0x00030000, |
| 89 | }; |
| 90 | |
| 91 | /* |
| 92 | * System Register (SYS) bit definitions. |
| 93 | */ |
| 94 | enum { |
| 95 | SYS_EFE = (1 << 0), |
| 96 | SYS_FAE = (1 << 1), |
| 97 | SYS_MDC = (1 << 2), |
| 98 | SYS_DST = (1 << 3), |
| 99 | SYS_DWC = (1 << 4), |
| 100 | SYS_EVW = (1 << 5), |
| 101 | SYS_OMP_DLY_MASK = 0x3f000000, |
| 102 | /* |
| 103 | * There are no values defined as of edit #15. |
| 104 | */ |
| 105 | SYS_ODI = (1 << 14), |
| 106 | }; |
| 107 | |
| 108 | /* |
| 109 | * Reset/Failover Register (RST_FO) bit definitions. |
| 110 | */ |
| 111 | enum { |
| 112 | RST_FO_TFO = (1 << 0), |
| 113 | RST_FO_RR_MASK = 0x00060000, |
| 114 | RST_FO_RR_CQ_CAM = 0x00000000, |
| 115 | RST_FO_RR_DROP = 0x00000001, |
| 116 | RST_FO_RR_DQ = 0x00000002, |
| 117 | RST_FO_RR_RCV_FUNC_CQ = 0x00000003, |
| 118 | RST_FO_FRB = (1 << 12), |
| 119 | RST_FO_MOP = (1 << 13), |
| 120 | RST_FO_REG = (1 << 14), |
| 121 | RST_FO_FR = (1 << 15), |
| 122 | }; |
| 123 | |
| 124 | /* |
| 125 | * Function Specific Control Register (FSC) bit definitions. |
| 126 | */ |
| 127 | enum { |
| 128 | FSC_DBRST_MASK = 0x00070000, |
| 129 | FSC_DBRST_256 = 0x00000000, |
| 130 | FSC_DBRST_512 = 0x00000001, |
| 131 | FSC_DBRST_768 = 0x00000002, |
| 132 | FSC_DBRST_1024 = 0x00000003, |
| 133 | FSC_DBL_MASK = 0x00180000, |
| 134 | FSC_DBL_DBRST = 0x00000000, |
| 135 | FSC_DBL_MAX_PLD = 0x00000008, |
| 136 | FSC_DBL_MAX_BRST = 0x00000010, |
| 137 | FSC_DBL_128_BYTES = 0x00000018, |
| 138 | FSC_EC = (1 << 5), |
| 139 | FSC_EPC_MASK = 0x00c00000, |
| 140 | FSC_EPC_INBOUND = (1 << 6), |
| 141 | FSC_EPC_OUTBOUND = (1 << 7), |
| 142 | FSC_VM_PAGESIZE_MASK = 0x07000000, |
| 143 | FSC_VM_PAGE_2K = 0x00000100, |
| 144 | FSC_VM_PAGE_4K = 0x00000200, |
| 145 | FSC_VM_PAGE_8K = 0x00000300, |
| 146 | FSC_VM_PAGE_64K = 0x00000600, |
| 147 | FSC_SH = (1 << 11), |
| 148 | FSC_DSB = (1 << 12), |
| 149 | FSC_STE = (1 << 13), |
| 150 | FSC_FE = (1 << 15), |
| 151 | }; |
| 152 | |
| 153 | /* |
| 154 | * Host Command Status Register (CSR) bit definitions. |
| 155 | */ |
| 156 | enum { |
| 157 | CSR_ERR_STS_MASK = 0x0000003f, |
| 158 | /* |
| 159 | * There are no valued defined as of edit #15. |
| 160 | */ |
| 161 | CSR_RR = (1 << 8), |
| 162 | CSR_HRI = (1 << 9), |
| 163 | CSR_RP = (1 << 10), |
| 164 | CSR_CMD_PARM_SHIFT = 22, |
| 165 | CSR_CMD_NOP = 0x00000000, |
| 166 | CSR_CMD_SET_RST = 0x1000000, |
| 167 | CSR_CMD_CLR_RST = 0x20000000, |
| 168 | CSR_CMD_SET_PAUSE = 0x30000000, |
| 169 | CSR_CMD_CLR_PAUSE = 0x40000000, |
| 170 | CSR_CMD_SET_H2R_INT = 0x50000000, |
| 171 | CSR_CMD_CLR_H2R_INT = 0x60000000, |
| 172 | CSR_CMD_PAR_EN = 0x70000000, |
| 173 | CSR_CMD_SET_BAD_PAR = 0x80000000, |
| 174 | CSR_CMD_CLR_BAD_PAR = 0x90000000, |
| 175 | CSR_CMD_CLR_R2PCI_INT = 0xa0000000, |
| 176 | }; |
| 177 | |
| 178 | /* |
| 179 | * Configuration Register (CFG) bit definitions. |
| 180 | */ |
| 181 | enum { |
| 182 | CFG_LRQ = (1 << 0), |
| 183 | CFG_DRQ = (1 << 1), |
| 184 | CFG_LR = (1 << 2), |
| 185 | CFG_DR = (1 << 3), |
| 186 | CFG_LE = (1 << 5), |
| 187 | CFG_LCQ = (1 << 6), |
| 188 | CFG_DCQ = (1 << 7), |
| 189 | CFG_Q_SHIFT = 8, |
| 190 | CFG_Q_MASK = 0x7f000000, |
| 191 | }; |
| 192 | |
| 193 | /* |
| 194 | * Status Register (STS) bit definitions. |
| 195 | */ |
| 196 | enum { |
| 197 | STS_FE = (1 << 0), |
| 198 | STS_PI = (1 << 1), |
| 199 | STS_PL0 = (1 << 2), |
| 200 | STS_PL1 = (1 << 3), |
| 201 | STS_PI0 = (1 << 4), |
| 202 | STS_PI1 = (1 << 5), |
| 203 | STS_FUNC_ID_MASK = 0x000000c0, |
| 204 | STS_FUNC_ID_SHIFT = 6, |
| 205 | STS_F0E = (1 << 8), |
| 206 | STS_F1E = (1 << 9), |
| 207 | STS_F2E = (1 << 10), |
| 208 | STS_F3E = (1 << 11), |
| 209 | STS_NFE = (1 << 12), |
| 210 | }; |
| 211 | |
| 212 | /* |
| 213 | * Interrupt Enable Register (INTR_EN) bit definitions. |
| 214 | */ |
| 215 | enum { |
| 216 | INTR_EN_INTR_MASK = 0x007f0000, |
| 217 | INTR_EN_TYPE_MASK = 0x03000000, |
| 218 | INTR_EN_TYPE_ENABLE = 0x00000100, |
| 219 | INTR_EN_TYPE_DISABLE = 0x00000200, |
| 220 | INTR_EN_TYPE_READ = 0x00000300, |
| 221 | INTR_EN_IHD = (1 << 13), |
| 222 | INTR_EN_IHD_MASK = (INTR_EN_IHD << 16), |
| 223 | INTR_EN_EI = (1 << 14), |
| 224 | INTR_EN_EN = (1 << 15), |
| 225 | }; |
| 226 | |
| 227 | /* |
| 228 | * Interrupt Mask Register (INTR_MASK) bit definitions. |
| 229 | */ |
| 230 | enum { |
| 231 | INTR_MASK_PI = (1 << 0), |
| 232 | INTR_MASK_HL0 = (1 << 1), |
| 233 | INTR_MASK_LH0 = (1 << 2), |
| 234 | INTR_MASK_HL1 = (1 << 3), |
| 235 | INTR_MASK_LH1 = (1 << 4), |
| 236 | INTR_MASK_SE = (1 << 5), |
| 237 | INTR_MASK_LSC = (1 << 6), |
| 238 | INTR_MASK_MC = (1 << 7), |
| 239 | INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC, |
| 240 | }; |
| 241 | |
| 242 | /* |
| 243 | * Register (REV_ID) bit definitions. |
| 244 | */ |
| 245 | enum { |
| 246 | REV_ID_MASK = 0x0000000f, |
| 247 | REV_ID_NICROLL_SHIFT = 0, |
| 248 | REV_ID_NICREV_SHIFT = 4, |
| 249 | REV_ID_XGROLL_SHIFT = 8, |
| 250 | REV_ID_XGREV_SHIFT = 12, |
| 251 | REV_ID_CHIPREV_SHIFT = 28, |
| 252 | }; |
| 253 | |
| 254 | /* |
| 255 | * Force ECC Error Register (FRC_ECC_ERR) bit definitions. |
| 256 | */ |
| 257 | enum { |
| 258 | FRC_ECC_ERR_VW = (1 << 12), |
| 259 | FRC_ECC_ERR_VB = (1 << 13), |
| 260 | FRC_ECC_ERR_NI = (1 << 14), |
| 261 | FRC_ECC_ERR_NO = (1 << 15), |
| 262 | FRC_ECC_PFE_SHIFT = 16, |
| 263 | FRC_ECC_ERR_DO = (1 << 18), |
| 264 | FRC_ECC_P14 = (1 << 19), |
| 265 | }; |
| 266 | |
| 267 | /* |
| 268 | * Error Status Register (ERR_STS) bit definitions. |
| 269 | */ |
| 270 | enum { |
| 271 | ERR_STS_NOF = (1 << 0), |
| 272 | ERR_STS_NIF = (1 << 1), |
| 273 | ERR_STS_DRP = (1 << 2), |
| 274 | ERR_STS_XGP = (1 << 3), |
| 275 | ERR_STS_FOU = (1 << 4), |
| 276 | ERR_STS_FOC = (1 << 5), |
| 277 | ERR_STS_FOF = (1 << 6), |
| 278 | ERR_STS_FIU = (1 << 7), |
| 279 | ERR_STS_FIC = (1 << 8), |
| 280 | ERR_STS_FIF = (1 << 9), |
| 281 | ERR_STS_MOF = (1 << 10), |
| 282 | ERR_STS_TA = (1 << 11), |
| 283 | ERR_STS_MA = (1 << 12), |
| 284 | ERR_STS_MPE = (1 << 13), |
| 285 | ERR_STS_SCE = (1 << 14), |
| 286 | ERR_STS_STE = (1 << 15), |
| 287 | ERR_STS_FOW = (1 << 16), |
| 288 | ERR_STS_UE = (1 << 17), |
| 289 | ERR_STS_MCH = (1 << 26), |
| 290 | ERR_STS_LOC_SHIFT = 27, |
| 291 | }; |
| 292 | |
| 293 | /* |
| 294 | * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions. |
| 295 | */ |
| 296 | enum { |
| 297 | RAM_DBG_ADDR_FW = (1 << 30), |
| 298 | RAM_DBG_ADDR_FR = (1 << 31), |
| 299 | }; |
| 300 | |
| 301 | /* |
| 302 | * Semaphore Register (SEM) bit definitions. |
| 303 | */ |
| 304 | enum { |
| 305 | /* |
| 306 | * Example: |
| 307 | * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT) |
| 308 | */ |
| 309 | SEM_CLEAR = 0, |
| 310 | SEM_SET = 1, |
| 311 | SEM_FORCE = 3, |
| 312 | SEM_XGMAC0_SHIFT = 0, |
| 313 | SEM_XGMAC1_SHIFT = 2, |
| 314 | SEM_ICB_SHIFT = 4, |
| 315 | SEM_MAC_ADDR_SHIFT = 6, |
| 316 | SEM_FLASH_SHIFT = 8, |
| 317 | SEM_PROBE_SHIFT = 10, |
| 318 | SEM_RT_IDX_SHIFT = 12, |
| 319 | SEM_PROC_REG_SHIFT = 14, |
| 320 | SEM_XGMAC0_MASK = 0x00030000, |
| 321 | SEM_XGMAC1_MASK = 0x000c0000, |
| 322 | SEM_ICB_MASK = 0x00300000, |
| 323 | SEM_MAC_ADDR_MASK = 0x00c00000, |
| 324 | SEM_FLASH_MASK = 0x03000000, |
| 325 | SEM_PROBE_MASK = 0x0c000000, |
| 326 | SEM_RT_IDX_MASK = 0x30000000, |
| 327 | SEM_PROC_REG_MASK = 0xc0000000, |
| 328 | }; |
| 329 | |
| 330 | /* |
| 331 | * 10G MAC Address Register (XGMAC_ADDR) bit definitions. |
| 332 | */ |
| 333 | enum { |
| 334 | XGMAC_ADDR_RDY = (1 << 31), |
| 335 | XGMAC_ADDR_R = (1 << 30), |
| 336 | XGMAC_ADDR_XME = (1 << 29), |
| 337 | |
| 338 | /* XGMAC control registers */ |
| 339 | PAUSE_SRC_LO = 0x00000100, |
| 340 | PAUSE_SRC_HI = 0x00000104, |
| 341 | GLOBAL_CFG = 0x00000108, |
| 342 | GLOBAL_CFG_RESET = (1 << 0), |
| 343 | GLOBAL_CFG_JUMBO = (1 << 6), |
| 344 | GLOBAL_CFG_TX_STAT_EN = (1 << 10), |
| 345 | GLOBAL_CFG_RX_STAT_EN = (1 << 11), |
| 346 | TX_CFG = 0x0000010c, |
| 347 | TX_CFG_RESET = (1 << 0), |
| 348 | TX_CFG_EN = (1 << 1), |
| 349 | TX_CFG_PREAM = (1 << 2), |
| 350 | RX_CFG = 0x00000110, |
| 351 | RX_CFG_RESET = (1 << 0), |
| 352 | RX_CFG_EN = (1 << 1), |
| 353 | RX_CFG_PREAM = (1 << 2), |
| 354 | FLOW_CTL = 0x0000011c, |
| 355 | PAUSE_OPCODE = 0x00000120, |
| 356 | PAUSE_TIMER = 0x00000124, |
| 357 | PAUSE_FRM_DEST_LO = 0x00000128, |
| 358 | PAUSE_FRM_DEST_HI = 0x0000012c, |
| 359 | MAC_TX_PARAMS = 0x00000134, |
| 360 | MAC_TX_PARAMS_JUMBO = (1 << 31), |
| 361 | MAC_TX_PARAMS_SIZE_SHIFT = 16, |
| 362 | MAC_RX_PARAMS = 0x00000138, |
| 363 | MAC_SYS_INT = 0x00000144, |
| 364 | MAC_SYS_INT_MASK = 0x00000148, |
| 365 | MAC_MGMT_INT = 0x0000014c, |
| 366 | MAC_MGMT_IN_MASK = 0x00000150, |
| 367 | EXT_ARB_MODE = 0x000001fc, |
| 368 | |
| 369 | /* XGMAC TX statistics registers */ |
| 370 | TX_PKTS = 0x00000200, |
| 371 | TX_BYTES = 0x00000208, |
| 372 | TX_MCAST_PKTS = 0x00000210, |
| 373 | TX_BCAST_PKTS = 0x00000218, |
| 374 | TX_UCAST_PKTS = 0x00000220, |
| 375 | TX_CTL_PKTS = 0x00000228, |
| 376 | TX_PAUSE_PKTS = 0x00000230, |
| 377 | TX_64_PKT = 0x00000238, |
| 378 | TX_65_TO_127_PKT = 0x00000240, |
| 379 | TX_128_TO_255_PKT = 0x00000248, |
| 380 | TX_256_511_PKT = 0x00000250, |
| 381 | TX_512_TO_1023_PKT = 0x00000258, |
| 382 | TX_1024_TO_1518_PKT = 0x00000260, |
| 383 | TX_1519_TO_MAX_PKT = 0x00000268, |
| 384 | TX_UNDERSIZE_PKT = 0x00000270, |
| 385 | TX_OVERSIZE_PKT = 0x00000278, |
| 386 | |
| 387 | /* XGMAC statistics control registers */ |
| 388 | RX_HALF_FULL_DET = 0x000002a0, |
| 389 | TX_HALF_FULL_DET = 0x000002a4, |
| 390 | RX_OVERFLOW_DET = 0x000002a8, |
| 391 | TX_OVERFLOW_DET = 0x000002ac, |
| 392 | RX_HALF_FULL_MASK = 0x000002b0, |
| 393 | TX_HALF_FULL_MASK = 0x000002b4, |
| 394 | RX_OVERFLOW_MASK = 0x000002b8, |
| 395 | TX_OVERFLOW_MASK = 0x000002bc, |
| 396 | STAT_CNT_CTL = 0x000002c0, |
| 397 | STAT_CNT_CTL_CLEAR_TX = (1 << 0), |
| 398 | STAT_CNT_CTL_CLEAR_RX = (1 << 1), |
| 399 | AUX_RX_HALF_FULL_DET = 0x000002d0, |
| 400 | AUX_TX_HALF_FULL_DET = 0x000002d4, |
| 401 | AUX_RX_OVERFLOW_DET = 0x000002d8, |
| 402 | AUX_TX_OVERFLOW_DET = 0x000002dc, |
| 403 | AUX_RX_HALF_FULL_MASK = 0x000002f0, |
| 404 | AUX_TX_HALF_FULL_MASK = 0x000002f4, |
| 405 | AUX_RX_OVERFLOW_MASK = 0x000002f8, |
| 406 | AUX_TX_OVERFLOW_MASK = 0x000002fc, |
| 407 | |
| 408 | /* XGMAC RX statistics registers */ |
| 409 | RX_BYTES = 0x00000300, |
| 410 | RX_BYTES_OK = 0x00000308, |
| 411 | RX_PKTS = 0x00000310, |
| 412 | RX_PKTS_OK = 0x00000318, |
| 413 | RX_BCAST_PKTS = 0x00000320, |
| 414 | RX_MCAST_PKTS = 0x00000328, |
| 415 | RX_UCAST_PKTS = 0x00000330, |
| 416 | RX_UNDERSIZE_PKTS = 0x00000338, |
| 417 | RX_OVERSIZE_PKTS = 0x00000340, |
| 418 | RX_JABBER_PKTS = 0x00000348, |
| 419 | RX_UNDERSIZE_FCERR_PKTS = 0x00000350, |
| 420 | RX_DROP_EVENTS = 0x00000358, |
| 421 | RX_FCERR_PKTS = 0x00000360, |
| 422 | RX_ALIGN_ERR = 0x00000368, |
| 423 | RX_SYMBOL_ERR = 0x00000370, |
| 424 | RX_MAC_ERR = 0x00000378, |
| 425 | RX_CTL_PKTS = 0x00000380, |
| 426 | RX_PAUSE_PKTS = 0x00000384, |
| 427 | RX_64_PKTS = 0x00000390, |
| 428 | RX_65_TO_127_PKTS = 0x00000398, |
| 429 | RX_128_255_PKTS = 0x000003a0, |
| 430 | RX_256_511_PKTS = 0x000003a8, |
| 431 | RX_512_TO_1023_PKTS = 0x000003b0, |
| 432 | RX_1024_TO_1518_PKTS = 0x000003b8, |
| 433 | RX_1519_TO_MAX_PKTS = 0x000003c0, |
| 434 | RX_LEN_ERR_PKTS = 0x000003c8, |
| 435 | |
| 436 | /* XGMAC MDIO control registers */ |
| 437 | MDIO_TX_DATA = 0x00000400, |
| 438 | MDIO_RX_DATA = 0x00000410, |
| 439 | MDIO_CMD = 0x00000420, |
| 440 | MDIO_PHY_ADDR = 0x00000430, |
| 441 | MDIO_PORT = 0x00000440, |
| 442 | MDIO_STATUS = 0x00000450, |
| 443 | |
| 444 | /* XGMAC AUX statistics registers */ |
| 445 | }; |
| 446 | |
| 447 | /* |
| 448 | * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions. |
| 449 | */ |
| 450 | enum { |
| 451 | ETS_QUEUE_SHIFT = 29, |
| 452 | ETS_REF = (1 << 26), |
| 453 | ETS_RS = (1 << 27), |
| 454 | ETS_P = (1 << 28), |
| 455 | ETS_FC_COS_SHIFT = 23, |
| 456 | }; |
| 457 | |
| 458 | /* |
| 459 | * Flash Address Register (FLASH_ADDR) bit definitions. |
| 460 | */ |
| 461 | enum { |
| 462 | FLASH_ADDR_RDY = (1 << 31), |
| 463 | FLASH_ADDR_R = (1 << 30), |
| 464 | FLASH_ADDR_ERR = (1 << 29), |
| 465 | }; |
| 466 | |
| 467 | /* |
| 468 | * Stop CQ Processing Register (CQ_STOP) bit definitions. |
| 469 | */ |
| 470 | enum { |
| 471 | CQ_STOP_QUEUE_MASK = (0x007f0000), |
| 472 | CQ_STOP_TYPE_MASK = (0x03000000), |
| 473 | CQ_STOP_TYPE_START = 0x00000100, |
| 474 | CQ_STOP_TYPE_STOP = 0x00000200, |
| 475 | CQ_STOP_TYPE_READ = 0x00000300, |
| 476 | CQ_STOP_EN = (1 << 15), |
| 477 | }; |
| 478 | |
| 479 | /* |
| 480 | * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions. |
| 481 | */ |
| 482 | enum { |
| 483 | MAC_ADDR_IDX_SHIFT = 4, |
| 484 | MAC_ADDR_TYPE_SHIFT = 16, |
| 485 | MAC_ADDR_TYPE_MASK = 0x000f0000, |
| 486 | MAC_ADDR_TYPE_CAM_MAC = 0x00000000, |
| 487 | MAC_ADDR_TYPE_MULTI_MAC = 0x00010000, |
| 488 | MAC_ADDR_TYPE_VLAN = 0x00020000, |
| 489 | MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000, |
| 490 | MAC_ADDR_TYPE_FC_MAC = 0x00040000, |
| 491 | MAC_ADDR_TYPE_MGMT_MAC = 0x00050000, |
| 492 | MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000, |
| 493 | MAC_ADDR_TYPE_MGMT_V4 = 0x00070000, |
| 494 | MAC_ADDR_TYPE_MGMT_V6 = 0x00080000, |
| 495 | MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000, |
| 496 | MAC_ADDR_ADR = (1 << 25), |
| 497 | MAC_ADDR_RS = (1 << 26), |
| 498 | MAC_ADDR_E = (1 << 27), |
| 499 | MAC_ADDR_MR = (1 << 30), |
| 500 | MAC_ADDR_MW = (1 << 31), |
| 501 | MAX_MULTICAST_ENTRIES = 32, |
| 502 | }; |
| 503 | |
| 504 | /* |
| 505 | * MAC Protocol Address Index Register (SPLT_HDR) bit definitions. |
| 506 | */ |
| 507 | enum { |
| 508 | SPLT_HDR_EP = (1 << 31), |
| 509 | }; |
| 510 | |
| 511 | /* |
| 512 | * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions. |
| 513 | */ |
| 514 | enum { |
| 515 | FC_RCV_CFG_ECT = (1 << 15), |
| 516 | FC_RCV_CFG_DFH = (1 << 20), |
| 517 | FC_RCV_CFG_DVF = (1 << 21), |
| 518 | FC_RCV_CFG_RCE = (1 << 27), |
| 519 | FC_RCV_CFG_RFE = (1 << 28), |
| 520 | FC_RCV_CFG_TEE = (1 << 29), |
| 521 | FC_RCV_CFG_TCE = (1 << 30), |
| 522 | FC_RCV_CFG_TFE = (1 << 31), |
| 523 | }; |
| 524 | |
| 525 | /* |
| 526 | * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions. |
| 527 | */ |
| 528 | enum { |
| 529 | NIC_RCV_CFG_PPE = (1 << 0), |
| 530 | NIC_RCV_CFG_VLAN_MASK = 0x00060000, |
| 531 | NIC_RCV_CFG_VLAN_ALL = 0x00000000, |
| 532 | NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002, |
| 533 | NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004, |
| 534 | NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006, |
| 535 | NIC_RCV_CFG_RV = (1 << 3), |
| 536 | NIC_RCV_CFG_DFQ_MASK = (0x7f000000), |
| 537 | NIC_RCV_CFG_DFQ_SHIFT = 8, |
| 538 | NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */ |
| 539 | }; |
| 540 | |
| 541 | /* |
| 542 | * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions. |
| 543 | */ |
| 544 | enum { |
| 545 | MGMT_RCV_CFG_ARP = (1 << 0), |
| 546 | MGMT_RCV_CFG_DHC = (1 << 1), |
| 547 | MGMT_RCV_CFG_DHS = (1 << 2), |
| 548 | MGMT_RCV_CFG_NP = (1 << 3), |
| 549 | MGMT_RCV_CFG_I6N = (1 << 4), |
| 550 | MGMT_RCV_CFG_I6R = (1 << 5), |
| 551 | MGMT_RCV_CFG_DH6 = (1 << 6), |
| 552 | MGMT_RCV_CFG_UD1 = (1 << 7), |
| 553 | MGMT_RCV_CFG_UD0 = (1 << 8), |
| 554 | MGMT_RCV_CFG_BCT = (1 << 9), |
| 555 | MGMT_RCV_CFG_MCT = (1 << 10), |
| 556 | MGMT_RCV_CFG_DM = (1 << 11), |
| 557 | MGMT_RCV_CFG_RM = (1 << 12), |
| 558 | MGMT_RCV_CFG_STL = (1 << 13), |
| 559 | MGMT_RCV_CFG_VLAN_MASK = 0xc0000000, |
| 560 | MGMT_RCV_CFG_VLAN_ALL = 0x00000000, |
| 561 | MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000, |
| 562 | MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000, |
| 563 | MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000, |
| 564 | }; |
| 565 | |
| 566 | /* |
| 567 | * Routing Index Register (RT_IDX) bit definitions. |
| 568 | */ |
| 569 | enum { |
| 570 | RT_IDX_IDX_SHIFT = 8, |
| 571 | RT_IDX_TYPE_MASK = 0x000f0000, |
| 572 | RT_IDX_TYPE_RT = 0x00000000, |
| 573 | RT_IDX_TYPE_RT_INV = 0x00010000, |
| 574 | RT_IDX_TYPE_NICQ = 0x00020000, |
| 575 | RT_IDX_TYPE_NICQ_INV = 0x00030000, |
| 576 | RT_IDX_DST_MASK = 0x00700000, |
| 577 | RT_IDX_DST_RSS = 0x00000000, |
| 578 | RT_IDX_DST_CAM_Q = 0x00100000, |
| 579 | RT_IDX_DST_COS_Q = 0x00200000, |
| 580 | RT_IDX_DST_DFLT_Q = 0x00300000, |
| 581 | RT_IDX_DST_DEST_Q = 0x00400000, |
| 582 | RT_IDX_RS = (1 << 26), |
| 583 | RT_IDX_E = (1 << 27), |
| 584 | RT_IDX_MR = (1 << 30), |
| 585 | RT_IDX_MW = (1 << 31), |
| 586 | |
| 587 | /* Nic Queue format - type 2 bits */ |
| 588 | RT_IDX_BCAST = (1 << 0), |
| 589 | RT_IDX_MCAST = (1 << 1), |
| 590 | RT_IDX_MCAST_MATCH = (1 << 2), |
| 591 | RT_IDX_MCAST_REG_MATCH = (1 << 3), |
| 592 | RT_IDX_MCAST_HASH_MATCH = (1 << 4), |
| 593 | RT_IDX_FC_MACH = (1 << 5), |
| 594 | RT_IDX_ETH_FCOE = (1 << 6), |
| 595 | RT_IDX_CAM_HIT = (1 << 7), |
| 596 | RT_IDX_CAM_BIT0 = (1 << 8), |
| 597 | RT_IDX_CAM_BIT1 = (1 << 9), |
| 598 | RT_IDX_VLAN_TAG = (1 << 10), |
| 599 | RT_IDX_VLAN_MATCH = (1 << 11), |
| 600 | RT_IDX_VLAN_FILTER = (1 << 12), |
| 601 | RT_IDX_ETH_SKIP1 = (1 << 13), |
| 602 | RT_IDX_ETH_SKIP2 = (1 << 14), |
| 603 | RT_IDX_BCAST_MCAST_MATCH = (1 << 15), |
| 604 | RT_IDX_802_3 = (1 << 16), |
| 605 | RT_IDX_LLDP = (1 << 17), |
| 606 | RT_IDX_UNUSED018 = (1 << 18), |
| 607 | RT_IDX_UNUSED019 = (1 << 19), |
| 608 | RT_IDX_UNUSED20 = (1 << 20), |
| 609 | RT_IDX_UNUSED21 = (1 << 21), |
| 610 | RT_IDX_ERR = (1 << 22), |
| 611 | RT_IDX_VALID = (1 << 23), |
| 612 | RT_IDX_TU_CSUM_ERR = (1 << 24), |
| 613 | RT_IDX_IP_CSUM_ERR = (1 << 25), |
| 614 | RT_IDX_MAC_ERR = (1 << 26), |
| 615 | RT_IDX_RSS_TCP6 = (1 << 27), |
| 616 | RT_IDX_RSS_TCP4 = (1 << 28), |
| 617 | RT_IDX_RSS_IPV6 = (1 << 29), |
| 618 | RT_IDX_RSS_IPV4 = (1 << 30), |
| 619 | RT_IDX_RSS_MATCH = (1 << 31), |
| 620 | |
| 621 | /* Hierarchy for the NIC Queue Mask */ |
| 622 | RT_IDX_ALL_ERR_SLOT = 0, |
| 623 | RT_IDX_MAC_ERR_SLOT = 0, |
| 624 | RT_IDX_IP_CSUM_ERR_SLOT = 1, |
| 625 | RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2, |
| 626 | RT_IDX_BCAST_SLOT = 3, |
| 627 | RT_IDX_MCAST_MATCH_SLOT = 4, |
| 628 | RT_IDX_ALLMULTI_SLOT = 5, |
| 629 | RT_IDX_UNUSED6_SLOT = 6, |
| 630 | RT_IDX_UNUSED7_SLOT = 7, |
| 631 | RT_IDX_RSS_MATCH_SLOT = 8, |
| 632 | RT_IDX_RSS_IPV4_SLOT = 8, |
| 633 | RT_IDX_RSS_IPV6_SLOT = 9, |
| 634 | RT_IDX_RSS_TCP4_SLOT = 10, |
| 635 | RT_IDX_RSS_TCP6_SLOT = 11, |
| 636 | RT_IDX_CAM_HIT_SLOT = 12, |
| 637 | RT_IDX_UNUSED013 = 13, |
| 638 | RT_IDX_UNUSED014 = 14, |
| 639 | RT_IDX_PROMISCUOUS_SLOT = 15, |
| 640 | RT_IDX_MAX_SLOTS = 16, |
| 641 | }; |
| 642 | |
| 643 | /* |
| 644 | * Control Register Set Map |
| 645 | */ |
| 646 | enum { |
| 647 | PROC_ADDR = 0, /* Use semaphore */ |
| 648 | PROC_DATA = 0x04, /* Use semaphore */ |
| 649 | SYS = 0x08, |
| 650 | RST_FO = 0x0c, |
| 651 | FSC = 0x10, |
| 652 | CSR = 0x14, |
| 653 | LED = 0x18, |
| 654 | ICB_RID = 0x1c, /* Use semaphore */ |
| 655 | ICB_L = 0x20, /* Use semaphore */ |
| 656 | ICB_H = 0x24, /* Use semaphore */ |
| 657 | CFG = 0x28, |
| 658 | BIOS_ADDR = 0x2c, |
| 659 | STS = 0x30, |
| 660 | INTR_EN = 0x34, |
| 661 | INTR_MASK = 0x38, |
| 662 | ISR1 = 0x3c, |
| 663 | ISR2 = 0x40, |
| 664 | ISR3 = 0x44, |
| 665 | ISR4 = 0x48, |
| 666 | REV_ID = 0x4c, |
| 667 | FRC_ECC_ERR = 0x50, |
| 668 | ERR_STS = 0x54, |
| 669 | RAM_DBG_ADDR = 0x58, |
| 670 | RAM_DBG_DATA = 0x5c, |
| 671 | ECC_ERR_CNT = 0x60, |
| 672 | SEM = 0x64, |
| 673 | GPIO_1 = 0x68, /* Use semaphore */ |
| 674 | GPIO_2 = 0x6c, /* Use semaphore */ |
| 675 | GPIO_3 = 0x70, /* Use semaphore */ |
| 676 | RSVD2 = 0x74, |
| 677 | XGMAC_ADDR = 0x78, /* Use semaphore */ |
| 678 | XGMAC_DATA = 0x7c, /* Use semaphore */ |
| 679 | NIC_ETS = 0x80, |
| 680 | CNA_ETS = 0x84, |
| 681 | FLASH_ADDR = 0x88, /* Use semaphore */ |
| 682 | FLASH_DATA = 0x8c, /* Use semaphore */ |
| 683 | CQ_STOP = 0x90, |
| 684 | PAGE_TBL_RID = 0x94, |
| 685 | WQ_PAGE_TBL_LO = 0x98, |
| 686 | WQ_PAGE_TBL_HI = 0x9c, |
| 687 | CQ_PAGE_TBL_LO = 0xa0, |
| 688 | CQ_PAGE_TBL_HI = 0xa4, |
| 689 | MAC_ADDR_IDX = 0xa8, /* Use semaphore */ |
| 690 | MAC_ADDR_DATA = 0xac, /* Use semaphore */ |
| 691 | COS_DFLT_CQ1 = 0xb0, |
| 692 | COS_DFLT_CQ2 = 0xb4, |
| 693 | ETYPE_SKIP1 = 0xb8, |
| 694 | ETYPE_SKIP2 = 0xbc, |
| 695 | SPLT_HDR = 0xc0, |
| 696 | FC_PAUSE_THRES = 0xc4, |
| 697 | NIC_PAUSE_THRES = 0xc8, |
| 698 | FC_ETHERTYPE = 0xcc, |
| 699 | FC_RCV_CFG = 0xd0, |
| 700 | NIC_RCV_CFG = 0xd4, |
| 701 | FC_COS_TAGS = 0xd8, |
| 702 | NIC_COS_TAGS = 0xdc, |
| 703 | MGMT_RCV_CFG = 0xe0, |
| 704 | RT_IDX = 0xe4, |
| 705 | RT_DATA = 0xe8, |
| 706 | RSVD7 = 0xec, |
| 707 | XG_SERDES_ADDR = 0xf0, |
| 708 | XG_SERDES_DATA = 0xf4, |
| 709 | PRB_MX_ADDR = 0xf8, /* Use semaphore */ |
| 710 | PRB_MX_DATA = 0xfc, /* Use semaphore */ |
| 711 | }; |
| 712 | |
| 713 | /* |
| 714 | * CAM output format. |
| 715 | */ |
| 716 | enum { |
| 717 | CAM_OUT_ROUTE_FC = 0, |
| 718 | CAM_OUT_ROUTE_NIC = 1, |
| 719 | CAM_OUT_FUNC_SHIFT = 2, |
| 720 | CAM_OUT_RV = (1 << 4), |
| 721 | CAM_OUT_SH = (1 << 15), |
| 722 | CAM_OUT_CQ_ID_SHIFT = 5, |
| 723 | }; |
| 724 | |
| 725 | /* |
| 726 | * Mailbox definitions |
| 727 | */ |
| 728 | enum { |
| 729 | /* Asynchronous Event Notifications */ |
| 730 | AEN_SYS_ERR = 0x00008002, |
| 731 | AEN_LINK_UP = 0x00008011, |
| 732 | AEN_LINK_DOWN = 0x00008012, |
| 733 | AEN_IDC_CMPLT = 0x00008100, |
| 734 | AEN_IDC_REQ = 0x00008101, |
| 735 | AEN_FW_INIT_DONE = 0x00008400, |
| 736 | AEN_FW_INIT_FAIL = 0x00008401, |
| 737 | |
| 738 | /* Mailbox Command Opcodes. */ |
| 739 | MB_CMD_NOP = 0x00000000, |
| 740 | MB_CMD_EX_FW = 0x00000002, |
| 741 | MB_CMD_MB_TEST = 0x00000006, |
| 742 | MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */ |
| 743 | MB_CMD_ABOUT_FW = 0x00000008, |
| 744 | MB_CMD_LOAD_RISC_RAM = 0x0000000b, |
| 745 | MB_CMD_DUMP_RISC_RAM = 0x0000000c, |
| 746 | MB_CMD_WRITE_RAM = 0x0000000d, |
| 747 | MB_CMD_READ_RAM = 0x0000000f, |
| 748 | MB_CMD_STOP_FW = 0x00000014, |
| 749 | MB_CMD_MAKE_SYS_ERR = 0x0000002a, |
| 750 | MB_CMD_INIT_FW = 0x00000060, |
| 751 | MB_CMD_GET_INIT_CB = 0x00000061, |
| 752 | MB_CMD_GET_FW_STATE = 0x00000069, |
| 753 | MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */ |
| 754 | MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */ |
| 755 | MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */ |
| 756 | MB_WOL_DISABLE = 0x00000000, |
| 757 | MB_WOL_MAGIC_PKT = 0x00000001, |
| 758 | MB_WOL_FLTR = 0x00000002, |
| 759 | MB_WOL_UCAST = 0x00000004, |
| 760 | MB_WOL_MCAST = 0x00000008, |
| 761 | MB_WOL_BCAST = 0x00000010, |
| 762 | MB_WOL_LINK_UP = 0x00000020, |
| 763 | MB_WOL_LINK_DOWN = 0x00000040, |
| 764 | MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */ |
| 765 | MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */ |
| 766 | MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */ |
| 767 | MB_CMD_CLEAR_WOL_MAGIC = 0x00000114, /* Wake On Lan Magic Packet */ |
| 768 | MB_CMD_PORT_RESET = 0x00000120, |
| 769 | MB_CMD_SET_PORT_CFG = 0x00000122, |
| 770 | MB_CMD_GET_PORT_CFG = 0x00000123, |
| 771 | MB_CMD_SET_ASIC_VOLTS = 0x00000130, |
| 772 | MB_CMD_GET_SNS_DATA = 0x00000131, /* Temp and Volt Sense data. */ |
| 773 | |
| 774 | /* Mailbox Command Status. */ |
| 775 | MB_CMD_STS_GOOD = 0x00004000, /* Success. */ |
| 776 | MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */ |
| 777 | MB_CMD_STS_ERR = 0x00004005, /* Error. */ |
| 778 | }; |
| 779 | |
| 780 | struct mbox_params { |
| 781 | u32 mbox_in[MAILBOX_COUNT]; |
| 782 | u32 mbox_out[MAILBOX_COUNT]; |
| 783 | int in_count; |
| 784 | int out_count; |
| 785 | }; |
| 786 | |
| 787 | struct flash_params { |
| 788 | u8 dev_id_str[4]; |
| 789 | u16 size; |
| 790 | u16 csum; |
| 791 | u16 ver; |
| 792 | u16 sub_dev_id; |
| 793 | u8 mac_addr[6]; |
| 794 | u16 res; |
| 795 | }; |
| 796 | |
| 797 | |
| 798 | /* |
| 799 | * doorbell space for the rx ring context |
| 800 | */ |
| 801 | struct rx_doorbell_context { |
| 802 | u32 cnsmr_idx; /* 0x00 */ |
| 803 | u32 valid; /* 0x04 */ |
| 804 | u32 reserved[4]; /* 0x08-0x14 */ |
| 805 | u32 lbq_prod_idx; /* 0x18 */ |
| 806 | u32 sbq_prod_idx; /* 0x1c */ |
| 807 | }; |
| 808 | |
| 809 | /* |
| 810 | * doorbell space for the tx ring context |
| 811 | */ |
| 812 | struct tx_doorbell_context { |
| 813 | u32 prod_idx; /* 0x00 */ |
| 814 | u32 valid; /* 0x04 */ |
| 815 | u32 reserved[4]; /* 0x08-0x14 */ |
| 816 | u32 lbq_prod_idx; /* 0x18 */ |
| 817 | u32 sbq_prod_idx; /* 0x1c */ |
| 818 | }; |
| 819 | |
| 820 | /* DATA STRUCTURES SHARED WITH HARDWARE. */ |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 821 | struct tx_buf_desc { |
| 822 | __le64 addr; |
| 823 | __le32 len; |
| 824 | #define TX_DESC_LEN_MASK 0x000fffff |
| 825 | #define TX_DESC_C 0x40000000 |
| 826 | #define TX_DESC_E 0x80000000 |
| 827 | } __attribute((packed)); |
| 828 | |
| 829 | /* |
| 830 | * IOCB Definitions... |
| 831 | */ |
| 832 | |
| 833 | #define OPCODE_OB_MAC_IOCB 0x01 |
| 834 | #define OPCODE_OB_MAC_TSO_IOCB 0x02 |
| 835 | #define OPCODE_IB_MAC_IOCB 0x20 |
| 836 | #define OPCODE_IB_MPI_IOCB 0x21 |
| 837 | #define OPCODE_IB_AE_IOCB 0x3f |
| 838 | |
| 839 | struct ob_mac_iocb_req { |
| 840 | u8 opcode; |
| 841 | u8 flags1; |
| 842 | #define OB_MAC_IOCB_REQ_OI 0x01 |
| 843 | #define OB_MAC_IOCB_REQ_I 0x02 |
| 844 | #define OB_MAC_IOCB_REQ_D 0x08 |
| 845 | #define OB_MAC_IOCB_REQ_F 0x10 |
| 846 | u8 flags2; |
| 847 | u8 flags3; |
| 848 | #define OB_MAC_IOCB_DFP 0x02 |
| 849 | #define OB_MAC_IOCB_V 0x04 |
| 850 | __le32 reserved1[2]; |
| 851 | __le16 frame_len; |
| 852 | #define OB_MAC_IOCB_LEN_MASK 0x3ffff |
| 853 | __le16 reserved2; |
Ron Mercer | 3537d54 | 2009-01-05 18:19:59 -0800 | [diff] [blame] | 854 | u32 tid; |
| 855 | u32 txq_idx; |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 856 | __le32 reserved3; |
| 857 | __le16 vlan_tci; |
| 858 | __le16 reserved4; |
| 859 | struct tx_buf_desc tbd[TX_DESC_PER_IOCB]; |
| 860 | } __attribute((packed)); |
| 861 | |
| 862 | struct ob_mac_iocb_rsp { |
| 863 | u8 opcode; /* */ |
| 864 | u8 flags1; /* */ |
| 865 | #define OB_MAC_IOCB_RSP_OI 0x01 /* */ |
| 866 | #define OB_MAC_IOCB_RSP_I 0x02 /* */ |
| 867 | #define OB_MAC_IOCB_RSP_E 0x08 /* */ |
| 868 | #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */ |
| 869 | #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */ |
| 870 | #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */ |
| 871 | u8 flags2; /* */ |
| 872 | u8 flags3; /* */ |
| 873 | #define OB_MAC_IOCB_RSP_B 0x80 /* */ |
Ron Mercer | 3537d54 | 2009-01-05 18:19:59 -0800 | [diff] [blame] | 874 | u32 tid; |
| 875 | u32 txq_idx; |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 876 | __le32 reserved[13]; |
| 877 | } __attribute((packed)); |
| 878 | |
| 879 | struct ob_mac_tso_iocb_req { |
| 880 | u8 opcode; |
| 881 | u8 flags1; |
| 882 | #define OB_MAC_TSO_IOCB_OI 0x01 |
| 883 | #define OB_MAC_TSO_IOCB_I 0x02 |
| 884 | #define OB_MAC_TSO_IOCB_D 0x08 |
| 885 | #define OB_MAC_TSO_IOCB_IP4 0x40 |
| 886 | #define OB_MAC_TSO_IOCB_IP6 0x80 |
| 887 | u8 flags2; |
| 888 | #define OB_MAC_TSO_IOCB_LSO 0x20 |
| 889 | #define OB_MAC_TSO_IOCB_UC 0x40 |
| 890 | #define OB_MAC_TSO_IOCB_TC 0x80 |
| 891 | u8 flags3; |
| 892 | #define OB_MAC_TSO_IOCB_IC 0x01 |
| 893 | #define OB_MAC_TSO_IOCB_DFP 0x02 |
| 894 | #define OB_MAC_TSO_IOCB_V 0x04 |
| 895 | __le32 reserved1[2]; |
| 896 | __le32 frame_len; |
Ron Mercer | 3537d54 | 2009-01-05 18:19:59 -0800 | [diff] [blame] | 897 | u32 tid; |
| 898 | u32 txq_idx; |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 899 | __le16 total_hdrs_len; |
| 900 | __le16 net_trans_offset; |
| 901 | #define OB_MAC_TRANSPORT_HDR_SHIFT 6 |
| 902 | __le16 vlan_tci; |
| 903 | __le16 mss; |
| 904 | struct tx_buf_desc tbd[TX_DESC_PER_IOCB]; |
| 905 | } __attribute((packed)); |
| 906 | |
| 907 | struct ob_mac_tso_iocb_rsp { |
| 908 | u8 opcode; |
| 909 | u8 flags1; |
| 910 | #define OB_MAC_TSO_IOCB_RSP_OI 0x01 |
| 911 | #define OB_MAC_TSO_IOCB_RSP_I 0x02 |
| 912 | #define OB_MAC_TSO_IOCB_RSP_E 0x08 |
| 913 | #define OB_MAC_TSO_IOCB_RSP_S 0x10 |
| 914 | #define OB_MAC_TSO_IOCB_RSP_L 0x20 |
| 915 | #define OB_MAC_TSO_IOCB_RSP_P 0x40 |
| 916 | u8 flags2; /* */ |
| 917 | u8 flags3; /* */ |
| 918 | #define OB_MAC_TSO_IOCB_RSP_B 0x8000 |
Ron Mercer | 3537d54 | 2009-01-05 18:19:59 -0800 | [diff] [blame] | 919 | u32 tid; |
| 920 | u32 txq_idx; |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 921 | __le32 reserved2[13]; |
| 922 | } __attribute((packed)); |
| 923 | |
| 924 | struct ib_mac_iocb_rsp { |
| 925 | u8 opcode; /* 0x20 */ |
| 926 | u8 flags1; |
| 927 | #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ |
| 928 | #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ |
| 929 | #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ |
| 930 | #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ |
| 931 | #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ |
| 932 | #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */ |
| 933 | #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */ |
| 934 | #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */ |
| 935 | #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */ |
| 936 | #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */ |
| 937 | #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */ |
| 938 | u8 flags2; |
| 939 | #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */ |
| 940 | #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */ |
| 941 | #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */ |
| 942 | #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04 |
| 943 | #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08 |
| 944 | #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10 |
| 945 | #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14 |
| 946 | #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18 |
| 947 | #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c |
| 948 | #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */ |
| 949 | #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */ |
| 950 | #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */ |
| 951 | u8 flags3; |
| 952 | #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */ |
| 953 | #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */ |
| 954 | #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */ |
| 955 | #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */ |
| 956 | #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */ |
| 957 | #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */ |
| 958 | #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */ |
| 959 | #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */ |
| 960 | #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */ |
| 961 | #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */ |
| 962 | #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */ |
| 963 | __le32 data_len; /* */ |
| 964 | __le32 data_addr_lo; /* */ |
| 965 | __le32 data_addr_hi; /* */ |
| 966 | __le32 rss; /* */ |
| 967 | __le16 vlan_id; /* 12 bits */ |
| 968 | #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */ |
| 969 | #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */ |
| 970 | |
| 971 | __le16 reserved1; |
| 972 | __le32 reserved2[6]; |
Ron Mercer | a303ce0 | 2009-01-05 18:18:22 -0800 | [diff] [blame] | 973 | u8 reserved3[3]; |
| 974 | u8 flags4; |
| 975 | #define IB_MAC_IOCB_RSP_HV 0x20 |
| 976 | #define IB_MAC_IOCB_RSP_HS 0x40 |
| 977 | #define IB_MAC_IOCB_RSP_HL 0x80 |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 978 | __le32 hdr_len; /* */ |
| 979 | __le32 hdr_addr_lo; /* */ |
| 980 | __le32 hdr_addr_hi; /* */ |
| 981 | } __attribute((packed)); |
| 982 | |
| 983 | struct ib_ae_iocb_rsp { |
| 984 | u8 opcode; |
| 985 | u8 flags1; |
| 986 | #define IB_AE_IOCB_RSP_OI 0x01 |
| 987 | #define IB_AE_IOCB_RSP_I 0x02 |
| 988 | u8 event; |
| 989 | #define LINK_UP_EVENT 0x00 |
| 990 | #define LINK_DOWN_EVENT 0x01 |
| 991 | #define CAM_LOOKUP_ERR_EVENT 0x06 |
| 992 | #define SOFT_ECC_ERROR_EVENT 0x07 |
| 993 | #define MGMT_ERR_EVENT 0x08 |
| 994 | #define TEN_GIG_MAC_EVENT 0x09 |
| 995 | #define GPI0_H2L_EVENT 0x10 |
| 996 | #define GPI0_L2H_EVENT 0x20 |
| 997 | #define GPI1_H2L_EVENT 0x11 |
| 998 | #define GPI1_L2H_EVENT 0x21 |
| 999 | #define PCI_ERR_ANON_BUF_RD 0x40 |
| 1000 | u8 q_id; |
| 1001 | __le32 reserved[15]; |
| 1002 | } __attribute((packed)); |
| 1003 | |
| 1004 | /* |
| 1005 | * These three structures are for generic |
| 1006 | * handling of ib and ob iocbs. |
| 1007 | */ |
| 1008 | struct ql_net_rsp_iocb { |
| 1009 | u8 opcode; |
| 1010 | u8 flags0; |
| 1011 | __le16 length; |
| 1012 | __le32 tid; |
| 1013 | __le32 reserved[14]; |
| 1014 | } __attribute((packed)); |
| 1015 | |
| 1016 | struct net_req_iocb { |
| 1017 | u8 opcode; |
| 1018 | u8 flags0; |
| 1019 | __le16 flags1; |
| 1020 | __le32 tid; |
| 1021 | __le32 reserved1[30]; |
| 1022 | } __attribute((packed)); |
| 1023 | |
| 1024 | /* |
| 1025 | * tx ring initialization control block for chip. |
| 1026 | * It is defined as: |
| 1027 | * "Work Queue Initialization Control Block" |
| 1028 | */ |
| 1029 | struct wqicb { |
| 1030 | __le16 len; |
| 1031 | #define Q_LEN_V (1 << 4) |
| 1032 | #define Q_LEN_CPP_CONT 0x0000 |
| 1033 | #define Q_LEN_CPP_16 0x0001 |
| 1034 | #define Q_LEN_CPP_32 0x0002 |
| 1035 | #define Q_LEN_CPP_64 0x0003 |
| 1036 | __le16 flags; |
| 1037 | #define Q_PRI_SHIFT 1 |
| 1038 | #define Q_FLAGS_LC 0x1000 |
| 1039 | #define Q_FLAGS_LB 0x2000 |
| 1040 | #define Q_FLAGS_LI 0x4000 |
| 1041 | #define Q_FLAGS_LO 0x8000 |
| 1042 | __le16 cq_id_rss; |
| 1043 | #define Q_CQ_ID_RSS_RV 0x8000 |
| 1044 | __le16 rid; |
| 1045 | __le32 addr_lo; |
| 1046 | __le32 addr_hi; |
| 1047 | __le32 cnsmr_idx_addr_lo; |
| 1048 | __le32 cnsmr_idx_addr_hi; |
| 1049 | } __attribute((packed)); |
| 1050 | |
| 1051 | /* |
| 1052 | * rx ring initialization control block for chip. |
| 1053 | * It is defined as: |
| 1054 | * "Completion Queue Initialization Control Block" |
| 1055 | */ |
| 1056 | struct cqicb { |
| 1057 | u8 msix_vect; |
| 1058 | u8 reserved1; |
| 1059 | u8 reserved2; |
| 1060 | u8 flags; |
| 1061 | #define FLAGS_LV 0x08 |
| 1062 | #define FLAGS_LS 0x10 |
| 1063 | #define FLAGS_LL 0x20 |
| 1064 | #define FLAGS_LI 0x40 |
| 1065 | #define FLAGS_LC 0x80 |
| 1066 | __le16 len; |
| 1067 | #define LEN_V (1 << 4) |
| 1068 | #define LEN_CPP_CONT 0x0000 |
| 1069 | #define LEN_CPP_32 0x0001 |
| 1070 | #define LEN_CPP_64 0x0002 |
| 1071 | #define LEN_CPP_128 0x0003 |
| 1072 | __le16 rid; |
| 1073 | __le32 addr_lo; |
| 1074 | __le32 addr_hi; |
| 1075 | __le32 prod_idx_addr_lo; |
| 1076 | __le32 prod_idx_addr_hi; |
| 1077 | __le16 pkt_delay; |
| 1078 | __le16 irq_delay; |
| 1079 | __le32 lbq_addr_lo; |
| 1080 | __le32 lbq_addr_hi; |
| 1081 | __le16 lbq_buf_size; |
| 1082 | __le16 lbq_len; /* entry count */ |
| 1083 | __le32 sbq_addr_lo; |
| 1084 | __le32 sbq_addr_hi; |
| 1085 | __le16 sbq_buf_size; |
| 1086 | __le16 sbq_len; /* entry count */ |
| 1087 | } __attribute((packed)); |
| 1088 | |
| 1089 | struct ricb { |
| 1090 | u8 base_cq; |
| 1091 | #define RSS_L4K 0x80 |
| 1092 | u8 flags; |
| 1093 | #define RSS_L6K 0x01 |
| 1094 | #define RSS_LI 0x02 |
| 1095 | #define RSS_LB 0x04 |
| 1096 | #define RSS_LM 0x08 |
| 1097 | #define RSS_RI4 0x10 |
| 1098 | #define RSS_RT4 0x20 |
| 1099 | #define RSS_RI6 0x40 |
| 1100 | #define RSS_RT6 0x80 |
| 1101 | __le16 mask; |
| 1102 | __le32 hash_cq_id[256]; |
| 1103 | __le32 ipv6_hash_key[10]; |
| 1104 | __le32 ipv4_hash_key[4]; |
| 1105 | } __attribute((packed)); |
| 1106 | |
| 1107 | /* SOFTWARE/DRIVER DATA STRUCTURES. */ |
| 1108 | |
| 1109 | struct oal { |
| 1110 | struct tx_buf_desc oal[TX_DESC_PER_OAL]; |
| 1111 | }; |
| 1112 | |
| 1113 | struct map_list { |
| 1114 | DECLARE_PCI_UNMAP_ADDR(mapaddr); |
| 1115 | DECLARE_PCI_UNMAP_LEN(maplen); |
| 1116 | }; |
| 1117 | |
| 1118 | struct tx_ring_desc { |
| 1119 | struct sk_buff *skb; |
| 1120 | struct ob_mac_iocb_req *queue_entry; |
Ron Mercer | 3537d54 | 2009-01-05 18:19:59 -0800 | [diff] [blame] | 1121 | u32 index; |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1122 | struct oal oal; |
| 1123 | struct map_list map[MAX_SKB_FRAGS + 1]; |
| 1124 | int map_cnt; |
| 1125 | struct tx_ring_desc *next; |
| 1126 | }; |
| 1127 | |
| 1128 | struct bq_desc { |
| 1129 | union { |
| 1130 | struct page *lbq_page; |
| 1131 | struct sk_buff *skb; |
| 1132 | } p; |
Ron Mercer | 2c9a0d4 | 2009-01-05 18:19:20 -0800 | [diff] [blame] | 1133 | __le64 *addr; |
Ron Mercer | 3537d54 | 2009-01-05 18:19:59 -0800 | [diff] [blame] | 1134 | u32 index; |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1135 | DECLARE_PCI_UNMAP_ADDR(mapaddr); |
| 1136 | DECLARE_PCI_UNMAP_LEN(maplen); |
| 1137 | }; |
| 1138 | |
| 1139 | #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count)) |
| 1140 | |
| 1141 | struct tx_ring { |
| 1142 | /* |
| 1143 | * queue info. |
| 1144 | */ |
| 1145 | struct wqicb wqicb; /* structure used to inform chip of new queue */ |
| 1146 | void *wq_base; /* pci_alloc:virtual addr for tx */ |
| 1147 | dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */ |
Ron Mercer | ba7cd3b | 2009-01-09 11:31:49 +0000 | [diff] [blame^] | 1148 | __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */ |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1149 | dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */ |
| 1150 | u32 wq_size; /* size in bytes of queue area */ |
| 1151 | u32 wq_len; /* number of entries in queue */ |
| 1152 | void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */ |
| 1153 | void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */ |
| 1154 | u16 prod_idx; /* current value for prod idx */ |
| 1155 | u16 cq_id; /* completion (rx) queue for tx completions */ |
| 1156 | u8 wq_id; /* queue id for this entry */ |
| 1157 | u8 reserved1[3]; |
| 1158 | struct tx_ring_desc *q; /* descriptor list for the queue */ |
| 1159 | spinlock_t lock; |
| 1160 | atomic_t tx_count; /* counts down for every outstanding IO */ |
| 1161 | atomic_t queue_stopped; /* Turns queue off when full. */ |
| 1162 | struct delayed_work tx_work; |
| 1163 | struct ql_adapter *qdev; |
| 1164 | }; |
| 1165 | |
| 1166 | /* |
| 1167 | * Type of inbound queue. |
| 1168 | */ |
| 1169 | enum { |
| 1170 | DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */ |
| 1171 | TX_Q = 3, /* Handles outbound completions. */ |
| 1172 | RX_Q = 4, /* Handles inbound completions. */ |
| 1173 | }; |
| 1174 | |
| 1175 | struct rx_ring { |
| 1176 | struct cqicb cqicb; /* The chip's completion queue init control block. */ |
| 1177 | |
| 1178 | /* Completion queue elements. */ |
| 1179 | void *cq_base; |
| 1180 | dma_addr_t cq_base_dma; |
| 1181 | u32 cq_size; |
| 1182 | u32 cq_len; |
| 1183 | u16 cq_id; |
Ron Mercer | ba7cd3b | 2009-01-09 11:31:49 +0000 | [diff] [blame^] | 1184 | __le32 *prod_idx_sh_reg; /* Shadowed producer register. */ |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1185 | dma_addr_t prod_idx_sh_reg_dma; |
| 1186 | void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */ |
| 1187 | u32 cnsmr_idx; /* current sw idx */ |
| 1188 | struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */ |
| 1189 | void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */ |
| 1190 | |
| 1191 | /* Large buffer queue elements. */ |
| 1192 | u32 lbq_len; /* entry count */ |
| 1193 | u32 lbq_size; /* size in bytes of queue */ |
| 1194 | u32 lbq_buf_size; |
| 1195 | void *lbq_base; |
| 1196 | dma_addr_t lbq_base_dma; |
| 1197 | void *lbq_base_indirect; |
| 1198 | dma_addr_t lbq_base_indirect_dma; |
| 1199 | struct bq_desc *lbq; /* array of control blocks */ |
| 1200 | void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */ |
| 1201 | u32 lbq_prod_idx; /* current sw prod idx */ |
| 1202 | u32 lbq_curr_idx; /* next entry we expect */ |
| 1203 | u32 lbq_clean_idx; /* beginning of new descs */ |
| 1204 | u32 lbq_free_cnt; /* free buffer desc cnt */ |
| 1205 | |
| 1206 | /* Small buffer queue elements. */ |
| 1207 | u32 sbq_len; /* entry count */ |
| 1208 | u32 sbq_size; /* size in bytes of queue */ |
| 1209 | u32 sbq_buf_size; |
| 1210 | void *sbq_base; |
| 1211 | dma_addr_t sbq_base_dma; |
| 1212 | void *sbq_base_indirect; |
| 1213 | dma_addr_t sbq_base_indirect_dma; |
| 1214 | struct bq_desc *sbq; /* array of control blocks */ |
| 1215 | void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */ |
| 1216 | u32 sbq_prod_idx; /* current sw prod idx */ |
| 1217 | u32 sbq_curr_idx; /* next entry we expect */ |
| 1218 | u32 sbq_clean_idx; /* beginning of new descs */ |
| 1219 | u32 sbq_free_cnt; /* free buffer desc cnt */ |
| 1220 | |
| 1221 | /* Misc. handler elements. */ |
| 1222 | u32 type; /* Type of queue, tx, rx, or default. */ |
| 1223 | u32 irq; /* Which vector this ring is assigned. */ |
| 1224 | u32 cpu; /* Which CPU this should run on. */ |
| 1225 | char name[IFNAMSIZ + 5]; |
| 1226 | struct napi_struct napi; |
| 1227 | struct delayed_work rx_work; |
| 1228 | u8 reserved; |
| 1229 | struct ql_adapter *qdev; |
| 1230 | }; |
| 1231 | |
| 1232 | /* |
| 1233 | * RSS Initialization Control Block |
| 1234 | */ |
| 1235 | struct hash_id { |
| 1236 | u8 value[4]; |
| 1237 | }; |
| 1238 | |
| 1239 | struct nic_stats { |
| 1240 | /* |
| 1241 | * These stats come from offset 200h to 278h |
| 1242 | * in the XGMAC register. |
| 1243 | */ |
| 1244 | u64 tx_pkts; |
| 1245 | u64 tx_bytes; |
| 1246 | u64 tx_mcast_pkts; |
| 1247 | u64 tx_bcast_pkts; |
| 1248 | u64 tx_ucast_pkts; |
| 1249 | u64 tx_ctl_pkts; |
| 1250 | u64 tx_pause_pkts; |
| 1251 | u64 tx_64_pkt; |
| 1252 | u64 tx_65_to_127_pkt; |
| 1253 | u64 tx_128_to_255_pkt; |
| 1254 | u64 tx_256_511_pkt; |
| 1255 | u64 tx_512_to_1023_pkt; |
| 1256 | u64 tx_1024_to_1518_pkt; |
| 1257 | u64 tx_1519_to_max_pkt; |
| 1258 | u64 tx_undersize_pkt; |
| 1259 | u64 tx_oversize_pkt; |
| 1260 | |
| 1261 | /* |
| 1262 | * These stats come from offset 300h to 3C8h |
| 1263 | * in the XGMAC register. |
| 1264 | */ |
| 1265 | u64 rx_bytes; |
| 1266 | u64 rx_bytes_ok; |
| 1267 | u64 rx_pkts; |
| 1268 | u64 rx_pkts_ok; |
| 1269 | u64 rx_bcast_pkts; |
| 1270 | u64 rx_mcast_pkts; |
| 1271 | u64 rx_ucast_pkts; |
| 1272 | u64 rx_undersize_pkts; |
| 1273 | u64 rx_oversize_pkts; |
| 1274 | u64 rx_jabber_pkts; |
| 1275 | u64 rx_undersize_fcerr_pkts; |
| 1276 | u64 rx_drop_events; |
| 1277 | u64 rx_fcerr_pkts; |
| 1278 | u64 rx_align_err; |
| 1279 | u64 rx_symbol_err; |
| 1280 | u64 rx_mac_err; |
| 1281 | u64 rx_ctl_pkts; |
| 1282 | u64 rx_pause_pkts; |
| 1283 | u64 rx_64_pkts; |
| 1284 | u64 rx_65_to_127_pkts; |
| 1285 | u64 rx_128_255_pkts; |
| 1286 | u64 rx_256_511_pkts; |
| 1287 | u64 rx_512_to_1023_pkts; |
| 1288 | u64 rx_1024_to_1518_pkts; |
| 1289 | u64 rx_1519_to_max_pkts; |
| 1290 | u64 rx_len_err_pkts; |
| 1291 | }; |
| 1292 | |
| 1293 | /* |
| 1294 | * intr_context structure is used during initialization |
| 1295 | * to hook the interrupts. It is also used in a single |
| 1296 | * irq environment as a context to the ISR. |
| 1297 | */ |
| 1298 | struct intr_context { |
| 1299 | struct ql_adapter *qdev; |
| 1300 | u32 intr; |
| 1301 | u32 hooked; |
| 1302 | u32 intr_en_mask; /* value/mask used to enable this intr */ |
| 1303 | u32 intr_dis_mask; /* value/mask used to disable this intr */ |
| 1304 | u32 intr_read_mask; /* value/mask used to read this intr */ |
| 1305 | char name[IFNAMSIZ * 2]; |
| 1306 | atomic_t irq_cnt; /* irq_cnt is used in single vector |
| 1307 | * environment. It's incremented for each |
| 1308 | * irq handler that is scheduled. When each |
| 1309 | * handler finishes it decrements irq_cnt and |
| 1310 | * enables interrupts if it's zero. */ |
| 1311 | irq_handler_t handler; |
| 1312 | }; |
| 1313 | |
| 1314 | /* adapter flags definitions. */ |
| 1315 | enum { |
| 1316 | QL_ADAPTER_UP = (1 << 0), /* Adapter has been brought up. */ |
| 1317 | QL_LEGACY_ENABLED = (1 << 3), |
| 1318 | QL_MSI_ENABLED = (1 << 3), |
| 1319 | QL_MSIX_ENABLED = (1 << 4), |
| 1320 | QL_DMA64 = (1 << 5), |
| 1321 | QL_PROMISCUOUS = (1 << 6), |
| 1322 | QL_ALLMULTI = (1 << 7), |
| 1323 | }; |
| 1324 | |
| 1325 | /* link_status bit definitions */ |
| 1326 | enum { |
| 1327 | LOOPBACK_MASK = 0x00000700, |
| 1328 | LOOPBACK_PCS = 0x00000100, |
| 1329 | LOOPBACK_HSS = 0x00000200, |
| 1330 | LOOPBACK_EXT = 0x00000300, |
| 1331 | PAUSE_MASK = 0x000000c0, |
| 1332 | PAUSE_STD = 0x00000040, |
| 1333 | PAUSE_PRI = 0x00000080, |
| 1334 | SPEED_MASK = 0x00000038, |
| 1335 | SPEED_100Mb = 0x00000000, |
| 1336 | SPEED_1Gb = 0x00000008, |
| 1337 | SPEED_10Gb = 0x00000010, |
| 1338 | LINK_TYPE_MASK = 0x00000007, |
| 1339 | LINK_TYPE_XFI = 0x00000001, |
| 1340 | LINK_TYPE_XAUI = 0x00000002, |
| 1341 | LINK_TYPE_XFI_BP = 0x00000003, |
| 1342 | LINK_TYPE_XAUI_BP = 0x00000004, |
| 1343 | LINK_TYPE_10GBASET = 0x00000005, |
| 1344 | }; |
| 1345 | |
| 1346 | /* |
| 1347 | * The main Adapter structure definition. |
| 1348 | * This structure has all fields relevant to the hardware. |
| 1349 | */ |
| 1350 | struct ql_adapter { |
| 1351 | struct ricb ricb; |
| 1352 | unsigned long flags; |
| 1353 | u32 wol; |
| 1354 | |
| 1355 | struct nic_stats nic_stats; |
| 1356 | |
| 1357 | struct vlan_group *vlgrp; |
| 1358 | |
| 1359 | /* PCI Configuration information for this device */ |
| 1360 | struct pci_dev *pdev; |
| 1361 | struct net_device *ndev; /* Parent NET device */ |
| 1362 | |
| 1363 | /* Hardware information */ |
| 1364 | u32 chip_rev_id; |
| 1365 | u32 func; /* PCI function for this adapter */ |
| 1366 | |
| 1367 | spinlock_t adapter_lock; |
| 1368 | spinlock_t hw_lock; |
| 1369 | spinlock_t stats_lock; |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1370 | |
| 1371 | /* PCI Bus Relative Register Addresses */ |
| 1372 | void __iomem *reg_base; |
| 1373 | void __iomem *doorbell_area; |
| 1374 | u32 doorbell_area_size; |
| 1375 | |
| 1376 | u32 msg_enable; |
| 1377 | |
| 1378 | /* Page for Shadow Registers */ |
| 1379 | void *rx_ring_shadow_reg_area; |
| 1380 | dma_addr_t rx_ring_shadow_reg_dma; |
| 1381 | void *tx_ring_shadow_reg_area; |
| 1382 | dma_addr_t tx_ring_shadow_reg_dma; |
| 1383 | |
| 1384 | u32 mailbox_in; |
| 1385 | u32 mailbox_out; |
| 1386 | |
| 1387 | int tx_ring_size; |
| 1388 | int rx_ring_size; |
| 1389 | u32 intr_count; |
| 1390 | struct msix_entry *msi_x_entry; |
| 1391 | struct intr_context intr_context[MAX_RX_RINGS]; |
| 1392 | |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1393 | int tx_ring_count; /* One per online CPU. */ |
| 1394 | u32 rss_ring_first_cq_id;/* index of first inbound (rss) rx_ring */ |
| 1395 | u32 rss_ring_count; /* One per online CPU. */ |
| 1396 | /* |
| 1397 | * rx_ring_count = |
| 1398 | * one default queue + |
| 1399 | * (CPU count * outbound completion rx_ring) + |
| 1400 | * (CPU count * inbound (RSS) completion rx_ring) |
| 1401 | */ |
| 1402 | int rx_ring_count; |
| 1403 | int ring_mem_size; |
| 1404 | void *ring_mem; |
| 1405 | struct rx_ring *rx_ring; |
| 1406 | int rx_csum; |
| 1407 | struct tx_ring *tx_ring; |
| 1408 | u32 default_rx_queue; |
| 1409 | |
| 1410 | u16 rx_coalesce_usecs; /* cqicb->int_delay */ |
| 1411 | u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */ |
| 1412 | u16 tx_coalesce_usecs; /* cqicb->int_delay */ |
| 1413 | u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */ |
| 1414 | |
| 1415 | u32 xg_sem_mask; |
| 1416 | u32 port_link_up; |
| 1417 | u32 port_init; |
| 1418 | u32 link_status; |
| 1419 | |
| 1420 | struct flash_params flash; |
| 1421 | |
| 1422 | struct net_device_stats stats; |
| 1423 | struct workqueue_struct *q_workqueue; |
| 1424 | struct workqueue_struct *workqueue; |
| 1425 | struct delayed_work asic_reset_work; |
| 1426 | struct delayed_work mpi_reset_work; |
| 1427 | struct delayed_work mpi_work; |
| 1428 | }; |
| 1429 | |
| 1430 | /* |
| 1431 | * Typical Register accessor for memory mapped device. |
| 1432 | */ |
| 1433 | static inline u32 ql_read32(const struct ql_adapter *qdev, int reg) |
| 1434 | { |
| 1435 | return readl(qdev->reg_base + reg); |
| 1436 | } |
| 1437 | |
| 1438 | /* |
| 1439 | * Typical Register accessor for memory mapped device. |
| 1440 | */ |
| 1441 | static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val) |
| 1442 | { |
| 1443 | writel(val, qdev->reg_base + reg); |
| 1444 | } |
| 1445 | |
| 1446 | /* |
| 1447 | * Doorbell Registers: |
| 1448 | * Doorbell registers are virtual registers in the PCI memory space. |
| 1449 | * The space is allocated by the chip during PCI initialization. The |
| 1450 | * device driver finds the doorbell address in BAR 3 in PCI config space. |
| 1451 | * The registers are used to control outbound and inbound queues. For |
| 1452 | * example, the producer index for an outbound queue. Each queue uses |
| 1453 | * 1 4k chunk of memory. The lower half of the space is for outbound |
| 1454 | * queues. The upper half is for inbound queues. |
| 1455 | */ |
| 1456 | static inline void ql_write_db_reg(u32 val, void __iomem *addr) |
| 1457 | { |
| 1458 | writel(val, addr); |
| 1459 | mmiowb(); |
| 1460 | } |
| 1461 | |
Ron Mercer | ba7cd3b | 2009-01-09 11:31:49 +0000 | [diff] [blame^] | 1462 | /* |
| 1463 | * Shadow Registers: |
| 1464 | * Outbound queues have a consumer index that is maintained by the chip. |
| 1465 | * Inbound queues have a producer index that is maintained by the chip. |
| 1466 | * For lower overhead, these registers are "shadowed" to host memory |
| 1467 | * which allows the device driver to track the queue progress without |
| 1468 | * PCI reads. When an entry is placed on an inbound queue, the chip will |
| 1469 | * update the relevant index register and then copy the value to the |
| 1470 | * shadow register in host memory. |
| 1471 | */ |
| 1472 | static inline u32 ql_read_sh_reg(__le32 *addr) |
| 1473 | { |
| 1474 | u32 reg; |
| 1475 | reg = le32_to_cpu(*addr); |
| 1476 | rmb(); |
| 1477 | return reg; |
| 1478 | } |
| 1479 | |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1480 | extern char qlge_driver_name[]; |
| 1481 | extern const char qlge_driver_version[]; |
| 1482 | extern const struct ethtool_ops qlge_ethtool_ops; |
| 1483 | |
| 1484 | extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask); |
| 1485 | extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask); |
| 1486 | extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data); |
| 1487 | extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, |
| 1488 | u32 *value); |
| 1489 | extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value); |
| 1490 | extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, |
| 1491 | u16 q_id); |
| 1492 | void ql_queue_fw_error(struct ql_adapter *qdev); |
| 1493 | void ql_mpi_work(struct work_struct *work); |
| 1494 | void ql_mpi_reset_work(struct work_struct *work); |
| 1495 | int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit); |
| 1496 | void ql_queue_asic_error(struct ql_adapter *qdev); |
Ron Mercer | bb0d215 | 2008-10-20 10:30:26 -0700 | [diff] [blame] | 1497 | u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr); |
Ron Mercer | c4e84bd | 2008-09-18 11:56:28 -0400 | [diff] [blame] | 1498 | void ql_set_ethtool_ops(struct net_device *ndev); |
| 1499 | int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data); |
| 1500 | |
| 1501 | #if 1 |
| 1502 | #define QL_ALL_DUMP |
| 1503 | #define QL_REG_DUMP |
| 1504 | #define QL_DEV_DUMP |
| 1505 | #define QL_CB_DUMP |
| 1506 | /* #define QL_IB_DUMP */ |
| 1507 | /* #define QL_OB_DUMP */ |
| 1508 | #endif |
| 1509 | |
| 1510 | #ifdef QL_REG_DUMP |
| 1511 | extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev); |
| 1512 | extern void ql_dump_routing_entries(struct ql_adapter *qdev); |
| 1513 | extern void ql_dump_regs(struct ql_adapter *qdev); |
| 1514 | #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev) |
| 1515 | #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev) |
| 1516 | #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev) |
| 1517 | #else |
| 1518 | #define QL_DUMP_REGS(qdev) |
| 1519 | #define QL_DUMP_ROUTE(qdev) |
| 1520 | #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) |
| 1521 | #endif |
| 1522 | |
| 1523 | #ifdef QL_STAT_DUMP |
| 1524 | extern void ql_dump_stat(struct ql_adapter *qdev); |
| 1525 | #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev) |
| 1526 | #else |
| 1527 | #define QL_DUMP_STAT(qdev) |
| 1528 | #endif |
| 1529 | |
| 1530 | #ifdef QL_DEV_DUMP |
| 1531 | extern void ql_dump_qdev(struct ql_adapter *qdev); |
| 1532 | #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev) |
| 1533 | #else |
| 1534 | #define QL_DUMP_QDEV(qdev) |
| 1535 | #endif |
| 1536 | |
| 1537 | #ifdef QL_CB_DUMP |
| 1538 | extern void ql_dump_wqicb(struct wqicb *wqicb); |
| 1539 | extern void ql_dump_tx_ring(struct tx_ring *tx_ring); |
| 1540 | extern void ql_dump_ricb(struct ricb *ricb); |
| 1541 | extern void ql_dump_cqicb(struct cqicb *cqicb); |
| 1542 | extern void ql_dump_rx_ring(struct rx_ring *rx_ring); |
| 1543 | extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id); |
| 1544 | #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb) |
| 1545 | #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb) |
| 1546 | #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring) |
| 1547 | #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb) |
| 1548 | #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring) |
| 1549 | #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \ |
| 1550 | ql_dump_hw_cb(qdev, size, bit, q_id) |
| 1551 | #else |
| 1552 | #define QL_DUMP_RICB(ricb) |
| 1553 | #define QL_DUMP_WQICB(wqicb) |
| 1554 | #define QL_DUMP_TX_RING(tx_ring) |
| 1555 | #define QL_DUMP_CQICB(cqicb) |
| 1556 | #define QL_DUMP_RX_RING(rx_ring) |
| 1557 | #define QL_DUMP_HW_CB(qdev, size, bit, q_id) |
| 1558 | #endif |
| 1559 | |
| 1560 | #ifdef QL_OB_DUMP |
| 1561 | extern void ql_dump_tx_desc(struct tx_buf_desc *tbd); |
| 1562 | extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb); |
| 1563 | extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp); |
| 1564 | #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb) |
| 1565 | #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp) |
| 1566 | #else |
| 1567 | #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) |
| 1568 | #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) |
| 1569 | #endif |
| 1570 | |
| 1571 | #ifdef QL_IB_DUMP |
| 1572 | extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp); |
| 1573 | #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp) |
| 1574 | #else |
| 1575 | #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) |
| 1576 | #endif |
| 1577 | |
| 1578 | #ifdef QL_ALL_DUMP |
| 1579 | extern void ql_dump_all(struct ql_adapter *qdev); |
| 1580 | #define QL_DUMP_ALL(qdev) ql_dump_all(qdev) |
| 1581 | #else |
| 1582 | #define QL_DUMP_ALL(qdev) |
| 1583 | #endif |
| 1584 | |
| 1585 | #endif /* _QLGE_H_ */ |