Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1 | /* bnx2x.h: Broadcom Everest network driver. |
| 2 | * |
Eliezer Tamir | 49d6677 | 2008-02-28 11:53:13 -0800 | [diff] [blame] | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
Eilon Greenstein | 24e3fce | 2008-06-12 14:30:28 -0700 | [diff] [blame] | 9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
| 10 | * Written by: Eliezer Tamir |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11 | * Based on code from Michael Chan's bnx2 driver |
| 12 | */ |
| 13 | |
| 14 | #ifndef BNX2X_H |
| 15 | #define BNX2X_H |
| 16 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 17 | /* compilation time flags */ |
| 18 | |
| 19 | /* define this to make the driver freeze on error to allow getting debug info |
| 20 | * (you will need to reboot afterwards) */ |
| 21 | /* #define BNX2X_STOP_ON_ERROR */ |
| 22 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 23 | /* error/debug prints */ |
| 24 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 25 | #define DRV_MODULE_NAME "bnx2x" |
| 26 | #define PFX DRV_MODULE_NAME ": " |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 27 | |
| 28 | /* for messages that are currently off */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 29 | #define BNX2X_MSG_OFF 0 |
| 30 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ |
| 31 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ |
| 32 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ |
| 33 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 34 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
| 35 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 36 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 37 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 38 | |
| 39 | /* regular debug print */ |
| 40 | #define DP(__mask, __fmt, __args...) do { \ |
| 41 | if (bp->msglevel & (__mask)) \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 42 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ |
| 43 | bp->dev?(bp->dev->name):"?", ##__args); \ |
| 44 | } while (0) |
| 45 | |
| 46 | /* errors debug print */ |
| 47 | #define BNX2X_DBG_ERR(__fmt, __args...) do { \ |
| 48 | if (bp->msglevel & NETIF_MSG_PROBE) \ |
| 49 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ |
| 50 | bp->dev?(bp->dev->name):"?", ##__args); \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 51 | } while (0) |
| 52 | |
| 53 | /* for errors (never masked) */ |
| 54 | #define BNX2X_ERR(__fmt, __args...) do { \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 55 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ |
| 56 | bp->dev?(bp->dev->name):"?", ##__args); \ |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 57 | } while (0) |
| 58 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 59 | /* before we have a dev->name use dev_info() */ |
| 60 | #define BNX2X_DEV_INFO(__fmt, __args...) do { \ |
| 61 | if (bp->msglevel & NETIF_MSG_PROBE) \ |
| 62 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ |
| 63 | } while (0) |
| 64 | |
| 65 | |
| 66 | #ifdef BNX2X_STOP_ON_ERROR |
| 67 | #define bnx2x_panic() do { \ |
| 68 | bp->panic = 1; \ |
| 69 | BNX2X_ERR("driver assert\n"); \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 70 | bnx2x_int_disable(bp); \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 71 | bnx2x_panic_dump(bp); \ |
| 72 | } while (0) |
| 73 | #else |
| 74 | #define bnx2x_panic() do { \ |
| 75 | BNX2X_ERR("driver assert\n"); \ |
| 76 | bnx2x_panic_dump(bp); \ |
| 77 | } while (0) |
| 78 | #endif |
| 79 | |
| 80 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 81 | #ifdef NETIF_F_HW_VLAN_TX |
| 82 | #define BCM_VLAN 1 |
| 83 | #endif |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 84 | |
| 85 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 86 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
| 87 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) |
| 88 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 89 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 90 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 91 | #define REG_ADDR(bp, offset) (bp->regview + offset) |
| 92 | |
| 93 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
| 94 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) |
| 95 | #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset)) |
| 96 | |
| 97 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 98 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 99 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
| 100 | #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 101 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 102 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
| 103 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 104 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 105 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
| 106 | do { \ |
| 107 | bnx2x_read_dmae(bp, offset, len32);\ |
| 108 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \ |
| 109 | } while (0) |
| 110 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 111 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 112 | do { \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 113 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 114 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
| 115 | offset, len32); \ |
| 116 | } while (0) |
| 117 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 118 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
| 119 | offsetof(struct shmem_region, field)) |
| 120 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) |
| 121 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 122 | |
| 123 | #define NIG_WR(reg, val) REG_WR(bp, reg, val) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 124 | #define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) |
| 125 | #define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 126 | |
| 127 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 128 | #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 129 | |
| 130 | #define for_each_nondefault_queue(bp, var) \ |
| 131 | for (var = 1; var < bp->num_queues; var++) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 132 | #define is_multi(bp) (bp->num_queues > 1) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 133 | |
| 134 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 135 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 136 | #define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 137 | struct sw_rx_bd { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 138 | struct sk_buff *skb; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 139 | DECLARE_PCI_UNMAP_ADDR(mapping) |
| 140 | }; |
| 141 | |
| 142 | struct sw_tx_bd { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 143 | struct sk_buff *skb; |
| 144 | u16 first_bd; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 145 | }; |
| 146 | |
| 147 | struct bnx2x_fastpath { |
| 148 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 149 | struct napi_struct napi; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 150 | |
| 151 | struct host_status_block *status_blk; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 152 | dma_addr_t status_blk_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 153 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 154 | struct eth_tx_db_data *hw_tx_prods; |
| 155 | dma_addr_t tx_prods_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 156 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 157 | struct sw_tx_bd *tx_buf_ring; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 158 | |
| 159 | struct eth_tx_bd *tx_desc_ring; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 160 | dma_addr_t tx_desc_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 161 | |
| 162 | struct sw_rx_bd *rx_buf_ring; |
| 163 | |
| 164 | struct eth_rx_bd *rx_desc_ring; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 165 | dma_addr_t rx_desc_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 166 | |
| 167 | union eth_rx_cqe *rx_comp_ring; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 168 | dma_addr_t rx_comp_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 169 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 170 | int state; |
| 171 | #define BNX2X_FP_STATE_CLOSED 0 |
| 172 | #define BNX2X_FP_STATE_IRQ 0x80000 |
| 173 | #define BNX2X_FP_STATE_OPENING 0x90000 |
| 174 | #define BNX2X_FP_STATE_OPEN 0xa0000 |
| 175 | #define BNX2X_FP_STATE_HALTING 0xb0000 |
| 176 | #define BNX2X_FP_STATE_HALTED 0xc0000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 177 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 178 | u8 index; /* number in fp array */ |
| 179 | u8 cl_id; /* eth client id */ |
| 180 | u8 sb_id; /* status block number in HW */ |
| 181 | #define FP_IDX(fp) (fp->index) |
| 182 | #define FP_CL_ID(fp) (fp->cl_id) |
| 183 | #define BP_CL_ID(bp) (bp->fp[0].cl_id) |
| 184 | #define FP_SB_ID(fp) (fp->sb_id) |
| 185 | #define CNIC_SB_ID 0 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 186 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 187 | u16 tx_pkt_prod; |
| 188 | u16 tx_pkt_cons; |
| 189 | u16 tx_bd_prod; |
| 190 | u16 tx_bd_cons; |
| 191 | u16 *tx_cons_sb; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 192 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 193 | u16 fp_c_idx; |
| 194 | u16 fp_u_idx; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 195 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 196 | u16 rx_bd_prod; |
| 197 | u16 rx_bd_cons; |
| 198 | u16 rx_comp_prod; |
| 199 | u16 rx_comp_cons; |
| 200 | u16 *rx_cons_sb; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 201 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 202 | unsigned long tx_pkt, |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 203 | rx_pkt, |
| 204 | rx_calls; |
| 205 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 206 | struct bnx2x *bp; /* parent */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 207 | }; |
| 208 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 209 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
| 210 | /* This is needed for determening of last_max */ |
| 211 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
| 212 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 213 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
| 214 | le32_to_cpu((bd)->addr_lo)) |
| 215 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) |
| 216 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 217 | /* stuff added to make the code fit 80Col */ |
| 218 | |
| 219 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
| 220 | |
| 221 | #define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \ |
| 222 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \ |
| 223 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 224 | |
| 225 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 226 | #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) |
| 227 | #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES) |
| 228 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 229 | #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS |
| 230 | #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS |
| 231 | #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 232 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 233 | #define BNX2X_RX_SB_INDEX \ |
| 234 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 235 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 236 | #define BNX2X_RX_SB_BD_INDEX \ |
| 237 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX]) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 238 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 239 | #define BNX2X_RX_SB_INDEX_NUM \ |
| 240 | (((U_SB_ETH_RX_CQ_INDEX << \ |
| 241 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \ |
| 242 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \ |
| 243 | ((U_SB_ETH_RX_BD_INDEX << \ |
| 244 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \ |
| 245 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 246 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 247 | #define BNX2X_TX_SB_INDEX \ |
| 248 | (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 249 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 250 | /* common */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 251 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 252 | struct bnx2x_common { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 253 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 254 | u32 chip_id; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 255 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 256 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 257 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 258 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 259 | #define CHIP_NUM_57710 0x164e |
| 260 | #define CHIP_NUM_57711 0x164f |
| 261 | #define CHIP_NUM_57711E 0x1650 |
| 262 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
| 263 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) |
| 264 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) |
| 265 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
| 266 | CHIP_IS_57711E(bp)) |
| 267 | #define IS_E1H_OFFSET CHIP_IS_E1H(bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 268 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 269 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 270 | #define CHIP_REV_Ax 0x00000000 |
| 271 | /* assume maximum 5 revisions */ |
| 272 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) |
| 273 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ |
| 274 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ |
| 275 | !(CHIP_REV(bp) & 0x00001000)) |
| 276 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ |
| 277 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ |
| 278 | (CHIP_REV(bp) & 0x00001000)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 279 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 280 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ |
| 281 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) |
| 282 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 283 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
| 284 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 285 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 286 | int flash_size; |
| 287 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
| 288 | #define NVRAM_TIMEOUT_COUNT 30000 |
| 289 | #define NVRAM_PAGE_SIZE 256 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 290 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 291 | u32 shmem_base; |
| 292 | |
| 293 | u32 hw_config; |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 294 | u32 board; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 295 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 296 | u32 bc_ver; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 297 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 298 | char *name; |
| 299 | }; |
| 300 | |
| 301 | |
| 302 | /* end of common */ |
| 303 | |
| 304 | /* port */ |
| 305 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 306 | struct nig_stats { |
| 307 | u32 brb_discard; |
| 308 | u32 brb_packet; |
| 309 | u32 brb_truncate; |
| 310 | u32 flow_ctrl_discard; |
| 311 | u32 flow_ctrl_octets; |
| 312 | u32 flow_ctrl_packet; |
| 313 | u32 mng_discard; |
| 314 | u32 mng_octet_inp; |
| 315 | u32 mng_octet_out; |
| 316 | u32 mng_packet_inp; |
| 317 | u32 mng_packet_out; |
| 318 | u32 pbf_octets; |
| 319 | u32 pbf_packet; |
| 320 | u32 safc_inp; |
| 321 | u32 egress_mac_pkt0_lo; |
| 322 | u32 egress_mac_pkt0_hi; |
| 323 | u32 egress_mac_pkt1_lo; |
| 324 | u32 egress_mac_pkt1_hi; |
| 325 | }; |
| 326 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 327 | struct bnx2x_port { |
| 328 | u32 pmf; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 329 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 330 | u32 link_config; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 331 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 332 | u32 supported; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 333 | /* link settings - missing defines */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 334 | #define SUPPORTED_2500baseX_Full (1 << 15) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 335 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 336 | u32 advertising; |
| 337 | /* link settings - missing defines */ |
| 338 | #define ADVERTISED_2500baseX_Full (1 << 15) |
| 339 | |
| 340 | u32 phy_addr; |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 341 | |
| 342 | /* used to synchronize phy accesses */ |
| 343 | struct mutex phy_mutex; |
| 344 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 345 | u32 port_stx; |
| 346 | |
| 347 | struct nig_stats old_nig_stats; |
| 348 | }; |
| 349 | |
| 350 | /* end of port */ |
| 351 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 352 | |
| 353 | enum bnx2x_stats_event { |
| 354 | STATS_EVENT_PMF = 0, |
| 355 | STATS_EVENT_LINK_UP, |
| 356 | STATS_EVENT_UPDATE, |
| 357 | STATS_EVENT_STOP, |
| 358 | STATS_EVENT_MAX |
| 359 | }; |
| 360 | |
| 361 | enum bnx2x_stats_state { |
| 362 | STATS_STATE_DISABLED = 0, |
| 363 | STATS_STATE_ENABLED, |
| 364 | STATS_STATE_MAX |
| 365 | }; |
| 366 | |
| 367 | struct bnx2x_eth_stats { |
| 368 | u32 total_bytes_received_hi; |
| 369 | u32 total_bytes_received_lo; |
| 370 | u32 total_bytes_transmitted_hi; |
| 371 | u32 total_bytes_transmitted_lo; |
| 372 | u32 total_unicast_packets_received_hi; |
| 373 | u32 total_unicast_packets_received_lo; |
| 374 | u32 total_multicast_packets_received_hi; |
| 375 | u32 total_multicast_packets_received_lo; |
| 376 | u32 total_broadcast_packets_received_hi; |
| 377 | u32 total_broadcast_packets_received_lo; |
| 378 | u32 total_unicast_packets_transmitted_hi; |
| 379 | u32 total_unicast_packets_transmitted_lo; |
| 380 | u32 total_multicast_packets_transmitted_hi; |
| 381 | u32 total_multicast_packets_transmitted_lo; |
| 382 | u32 total_broadcast_packets_transmitted_hi; |
| 383 | u32 total_broadcast_packets_transmitted_lo; |
| 384 | u32 valid_bytes_received_hi; |
| 385 | u32 valid_bytes_received_lo; |
| 386 | |
| 387 | u32 error_bytes_received_hi; |
| 388 | u32 error_bytes_received_lo; |
| 389 | |
| 390 | u32 rx_stat_ifhcinbadoctets_hi; |
| 391 | u32 rx_stat_ifhcinbadoctets_lo; |
| 392 | u32 tx_stat_ifhcoutbadoctets_hi; |
| 393 | u32 tx_stat_ifhcoutbadoctets_lo; |
| 394 | u32 rx_stat_dot3statsfcserrors_hi; |
| 395 | u32 rx_stat_dot3statsfcserrors_lo; |
| 396 | u32 rx_stat_dot3statsalignmenterrors_hi; |
| 397 | u32 rx_stat_dot3statsalignmenterrors_lo; |
| 398 | u32 rx_stat_dot3statscarriersenseerrors_hi; |
| 399 | u32 rx_stat_dot3statscarriersenseerrors_lo; |
| 400 | u32 rx_stat_falsecarriererrors_hi; |
| 401 | u32 rx_stat_falsecarriererrors_lo; |
| 402 | u32 rx_stat_etherstatsundersizepkts_hi; |
| 403 | u32 rx_stat_etherstatsundersizepkts_lo; |
| 404 | u32 rx_stat_dot3statsframestoolong_hi; |
| 405 | u32 rx_stat_dot3statsframestoolong_lo; |
| 406 | u32 rx_stat_etherstatsfragments_hi; |
| 407 | u32 rx_stat_etherstatsfragments_lo; |
| 408 | u32 rx_stat_etherstatsjabbers_hi; |
| 409 | u32 rx_stat_etherstatsjabbers_lo; |
| 410 | u32 rx_stat_maccontrolframesreceived_hi; |
| 411 | u32 rx_stat_maccontrolframesreceived_lo; |
| 412 | u32 rx_stat_bmac_xpf_hi; |
| 413 | u32 rx_stat_bmac_xpf_lo; |
| 414 | u32 rx_stat_bmac_xcf_hi; |
| 415 | u32 rx_stat_bmac_xcf_lo; |
| 416 | u32 rx_stat_xoffstateentered_hi; |
| 417 | u32 rx_stat_xoffstateentered_lo; |
| 418 | u32 rx_stat_xonpauseframesreceived_hi; |
| 419 | u32 rx_stat_xonpauseframesreceived_lo; |
| 420 | u32 rx_stat_xoffpauseframesreceived_hi; |
| 421 | u32 rx_stat_xoffpauseframesreceived_lo; |
| 422 | u32 tx_stat_outxonsent_hi; |
| 423 | u32 tx_stat_outxonsent_lo; |
| 424 | u32 tx_stat_outxoffsent_hi; |
| 425 | u32 tx_stat_outxoffsent_lo; |
| 426 | u32 tx_stat_flowcontroldone_hi; |
| 427 | u32 tx_stat_flowcontroldone_lo; |
| 428 | u32 tx_stat_etherstatscollisions_hi; |
| 429 | u32 tx_stat_etherstatscollisions_lo; |
| 430 | u32 tx_stat_dot3statssinglecollisionframes_hi; |
| 431 | u32 tx_stat_dot3statssinglecollisionframes_lo; |
| 432 | u32 tx_stat_dot3statsmultiplecollisionframes_hi; |
| 433 | u32 tx_stat_dot3statsmultiplecollisionframes_lo; |
| 434 | u32 tx_stat_dot3statsdeferredtransmissions_hi; |
| 435 | u32 tx_stat_dot3statsdeferredtransmissions_lo; |
| 436 | u32 tx_stat_dot3statsexcessivecollisions_hi; |
| 437 | u32 tx_stat_dot3statsexcessivecollisions_lo; |
| 438 | u32 tx_stat_dot3statslatecollisions_hi; |
| 439 | u32 tx_stat_dot3statslatecollisions_lo; |
| 440 | u32 tx_stat_etherstatspkts64octets_hi; |
| 441 | u32 tx_stat_etherstatspkts64octets_lo; |
| 442 | u32 tx_stat_etherstatspkts65octetsto127octets_hi; |
| 443 | u32 tx_stat_etherstatspkts65octetsto127octets_lo; |
| 444 | u32 tx_stat_etherstatspkts128octetsto255octets_hi; |
| 445 | u32 tx_stat_etherstatspkts128octetsto255octets_lo; |
| 446 | u32 tx_stat_etherstatspkts256octetsto511octets_hi; |
| 447 | u32 tx_stat_etherstatspkts256octetsto511octets_lo; |
| 448 | u32 tx_stat_etherstatspkts512octetsto1023octets_hi; |
| 449 | u32 tx_stat_etherstatspkts512octetsto1023octets_lo; |
| 450 | u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; |
| 451 | u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; |
| 452 | u32 tx_stat_etherstatspktsover1522octets_hi; |
| 453 | u32 tx_stat_etherstatspktsover1522octets_lo; |
| 454 | u32 tx_stat_bmac_2047_hi; |
| 455 | u32 tx_stat_bmac_2047_lo; |
| 456 | u32 tx_stat_bmac_4095_hi; |
| 457 | u32 tx_stat_bmac_4095_lo; |
| 458 | u32 tx_stat_bmac_9216_hi; |
| 459 | u32 tx_stat_bmac_9216_lo; |
| 460 | u32 tx_stat_bmac_16383_hi; |
| 461 | u32 tx_stat_bmac_16383_lo; |
| 462 | u32 tx_stat_dot3statsinternalmactransmiterrors_hi; |
| 463 | u32 tx_stat_dot3statsinternalmactransmiterrors_lo; |
| 464 | u32 tx_stat_bmac_ufl_hi; |
| 465 | u32 tx_stat_bmac_ufl_lo; |
| 466 | |
| 467 | u32 brb_drop_hi; |
| 468 | u32 brb_drop_lo; |
| 469 | |
| 470 | u32 jabber_packets_received; |
| 471 | |
| 472 | u32 etherstatspkts1024octetsto1522octets_hi; |
| 473 | u32 etherstatspkts1024octetsto1522octets_lo; |
| 474 | u32 etherstatspktsover1522octets_hi; |
| 475 | u32 etherstatspktsover1522octets_lo; |
| 476 | |
| 477 | u32 no_buff_discard; |
| 478 | |
| 479 | u32 mac_filter_discard; |
| 480 | u32 xxoverflow_discard; |
| 481 | u32 brb_truncate_discard; |
| 482 | u32 mac_discard; |
| 483 | |
| 484 | u32 driver_xoff; |
| 485 | }; |
| 486 | |
| 487 | #define STATS_OFFSET32(stat_name) \ |
| 488 | (offsetof(struct bnx2x_eth_stats, stat_name) / 4) |
| 489 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 490 | |
| 491 | #ifdef BNX2X_MULTI |
| 492 | #define MAX_CONTEXT 16 |
| 493 | #else |
| 494 | #define MAX_CONTEXT 1 |
| 495 | #endif |
| 496 | |
| 497 | union cdu_context { |
| 498 | struct eth_context eth; |
| 499 | char pad[1024]; |
| 500 | }; |
| 501 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 502 | #define MAX_DMAE_C 8 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 503 | |
| 504 | /* DMA memory not used in fastpath */ |
| 505 | struct bnx2x_slowpath { |
| 506 | union cdu_context context[MAX_CONTEXT]; |
| 507 | struct eth_stats_query fw_stats; |
| 508 | struct mac_configuration_cmd mac_config; |
| 509 | struct mac_configuration_cmd mcast_config; |
| 510 | |
| 511 | /* used by dmae command executer */ |
| 512 | struct dmae_command dmae[MAX_DMAE_C]; |
| 513 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 514 | u32 stats_comp; |
| 515 | union mac_stats mac_stats; |
| 516 | struct nig_stats nig_stats; |
| 517 | struct host_port_stats port_stats; |
| 518 | struct host_func_stats func_stats; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 519 | |
| 520 | u32 wb_comp; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 521 | u32 wb_data[4]; |
| 522 | }; |
| 523 | |
| 524 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) |
| 525 | #define bnx2x_sp_mapping(bp, var) \ |
| 526 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 527 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 528 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 529 | /* attn group wiring */ |
| 530 | #define MAX_DYNAMIC_ATTN_GRPS 8 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 531 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 532 | struct attn_route { |
| 533 | u32 sig[4]; |
| 534 | }; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 535 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 536 | struct bnx2x { |
| 537 | /* Fields used in the tx and intr/napi performance paths |
| 538 | * are grouped together in the beginning of the structure |
| 539 | */ |
| 540 | struct bnx2x_fastpath fp[MAX_CONTEXT]; |
| 541 | void __iomem *regview; |
| 542 | void __iomem *doorbells; |
| 543 | #define BNX2X_DB_SIZE (16*2048) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 544 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 545 | struct net_device *dev; |
| 546 | struct pci_dev *pdev; |
| 547 | |
| 548 | atomic_t intr_sem; |
| 549 | struct msix_entry msix_table[MAX_CONTEXT+1]; |
| 550 | |
| 551 | int tx_ring_size; |
| 552 | |
| 553 | #ifdef BCM_VLAN |
| 554 | struct vlan_group *vlgrp; |
| 555 | #endif |
| 556 | |
| 557 | u32 rx_csum; |
| 558 | u32 rx_offset; |
| 559 | u32 rx_buf_use_size; /* useable size */ |
| 560 | u32 rx_buf_size; /* with alignment */ |
| 561 | #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ |
| 562 | #define ETH_MIN_PACKET_SIZE 60 |
| 563 | #define ETH_MAX_PACKET_SIZE 1500 |
| 564 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 |
| 565 | |
| 566 | struct host_def_status_block *def_status_blk; |
| 567 | #define DEF_SB_ID 16 |
| 568 | u16 def_c_idx; |
| 569 | u16 def_u_idx; |
| 570 | u16 def_x_idx; |
| 571 | u16 def_t_idx; |
| 572 | u16 def_att_idx; |
| 573 | u32 attn_state; |
| 574 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; |
| 575 | u32 aeu_mask; |
| 576 | u32 nig_mask; |
| 577 | |
| 578 | /* slow path ring */ |
| 579 | struct eth_spe *spq; |
| 580 | dma_addr_t spq_mapping; |
| 581 | u16 spq_prod_idx; |
| 582 | struct eth_spe *spq_prod_bd; |
| 583 | struct eth_spe *spq_last_bd; |
| 584 | u16 *dsb_sp_prod; |
| 585 | u16 spq_left; /* serialize spq */ |
| 586 | /* used to synchronize spq accesses */ |
| 587 | spinlock_t spq_lock; |
| 588 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 589 | /* Flags for marking that there is a STAT_QUERY or |
| 590 | SET_MAC ramrod pending */ |
| 591 | u8 stats_pending; |
| 592 | u8 set_mac_pending; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 593 | |
| 594 | /* End of fileds used in the performance code paths */ |
| 595 | |
| 596 | int panic; |
| 597 | int msglevel; |
| 598 | |
| 599 | u32 flags; |
| 600 | #define PCIX_FLAG 1 |
| 601 | #define PCI_32BIT_FLAG 2 |
| 602 | #define ONE_TDMA_FLAG 4 /* no longer used */ |
| 603 | #define NO_WOL_FLAG 8 |
| 604 | #define USING_DAC_FLAG 0x10 |
| 605 | #define USING_MSIX_FLAG 0x20 |
| 606 | #define ASF_ENABLE_FLAG 0x40 |
| 607 | #define NO_MCP_FLAG 0x100 |
| 608 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
| 609 | |
| 610 | int func; |
| 611 | #define BP_PORT(bp) (bp->func % PORT_MAX) |
| 612 | #define BP_FUNC(bp) (bp->func) |
| 613 | #define BP_E1HVN(bp) (bp->func >> 1) |
| 614 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) |
| 615 | /* assorted E1HVN */ |
| 616 | #define IS_E1HMF(bp) (bp->e1hmf != 0) |
| 617 | #define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16) |
| 618 | |
| 619 | int pm_cap; |
| 620 | int pcie_cap; |
| 621 | |
| 622 | struct work_struct sp_task; |
| 623 | struct work_struct reset_task; |
| 624 | |
| 625 | struct timer_list timer; |
| 626 | int timer_interval; |
| 627 | int current_interval; |
| 628 | |
| 629 | u16 fw_seq; |
| 630 | u16 fw_drv_pulse_wr_seq; |
| 631 | u32 func_stx; |
| 632 | |
| 633 | struct link_params link_params; |
| 634 | struct link_vars link_vars; |
| 635 | |
| 636 | struct bnx2x_common common; |
| 637 | struct bnx2x_port port; |
| 638 | |
| 639 | u32 mf_config; |
| 640 | u16 e1hov; |
| 641 | u8 e1hmf; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 642 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 643 | u8 wol; |
| 644 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 645 | int rx_ring_size; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 646 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 647 | u16 tx_quick_cons_trip_int; |
| 648 | u16 tx_quick_cons_trip; |
| 649 | u16 tx_ticks_int; |
| 650 | u16 tx_ticks; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 651 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 652 | u16 rx_quick_cons_trip_int; |
| 653 | u16 rx_quick_cons_trip; |
| 654 | u16 rx_ticks_int; |
| 655 | u16 rx_ticks; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 656 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 657 | u32 stats_ticks; |
| 658 | u32 lin_cnt; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 659 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 660 | int state; |
| 661 | #define BNX2X_STATE_CLOSED 0x0 |
| 662 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
| 663 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 664 | #define BNX2X_STATE_OPEN 0x3000 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 665 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 666 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
| 667 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 668 | #define BNX2X_STATE_DISABLED 0xd000 |
| 669 | #define BNX2X_STATE_DIAG 0xe000 |
| 670 | #define BNX2X_STATE_ERROR 0xf000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 671 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 672 | int num_queues; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 673 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 674 | u32 rx_mode; |
| 675 | #define BNX2X_RX_MODE_NONE 0 |
| 676 | #define BNX2X_RX_MODE_NORMAL 1 |
| 677 | #define BNX2X_RX_MODE_ALLMULTI 2 |
| 678 | #define BNX2X_RX_MODE_PROMISC 3 |
| 679 | #define BNX2X_MAX_MULTICAST 64 |
| 680 | #define BNX2X_MAX_EMUL_MULTI 16 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 681 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 682 | dma_addr_t def_status_blk_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 683 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 684 | struct bnx2x_slowpath *slowpath; |
| 685 | dma_addr_t slowpath_mapping; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 686 | |
| 687 | #ifdef BCM_ISCSI |
| 688 | void *t1; |
| 689 | dma_addr_t t1_mapping; |
| 690 | void *t2; |
| 691 | dma_addr_t t2_mapping; |
| 692 | void *timers; |
| 693 | dma_addr_t timers_mapping; |
| 694 | void *qm; |
| 695 | dma_addr_t qm_mapping; |
| 696 | #endif |
| 697 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 698 | int dmae_ready; |
| 699 | /* used to synchronize dmae accesses */ |
| 700 | struct mutex dmae_mutex; |
| 701 | struct dmae_command init_dmae; |
| 702 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 703 | /* used to synchronize stats collecting */ |
| 704 | int stats_state; |
| 705 | /* used by dmae command loader */ |
| 706 | struct dmae_command stats_dmae; |
| 707 | int executer_idx; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 708 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 709 | u16 stats_counter; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 710 | struct tstorm_per_client_stats old_tclient; |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 711 | struct xstorm_per_client_stats old_xclient; |
| 712 | struct bnx2x_eth_stats eth_stats; |
| 713 | |
| 714 | struct z_stream_s *strm; |
| 715 | void *gunzip_buf; |
| 716 | dma_addr_t gunzip_mapping; |
| 717 | int gunzip_outlen; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 718 | #define FW_BUF_SIZE 0x8000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 719 | |
| 720 | }; |
| 721 | |
| 722 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 723 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
| 724 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, |
| 725 | u32 len32); |
| 726 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); |
| 727 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 728 | |
| 729 | /* MC hsi */ |
| 730 | #define RX_COPY_THRESH 92 |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 731 | #define BCM_PAGE_SHIFT 12 |
| 732 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) |
| 733 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) |
| 734 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 735 | |
| 736 | #define NUM_TX_RINGS 16 |
| 737 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) |
| 738 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) |
| 739 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) |
| 740 | #define MAX_TX_BD (NUM_TX_BD - 1) |
| 741 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) |
| 742 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
| 743 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) |
| 744 | #define TX_BD(x) ((x) & MAX_TX_BD) |
| 745 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) |
| 746 | |
| 747 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ |
| 748 | #define NUM_RX_RINGS 8 |
| 749 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
| 750 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) |
| 751 | #define RX_DESC_MASK (RX_DESC_CNT - 1) |
| 752 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) |
| 753 | #define MAX_RX_BD (NUM_RX_BD - 1) |
| 754 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) |
| 755 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
| 756 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) |
| 757 | #define RX_BD(x) ((x) & MAX_RX_BD) |
| 758 | |
| 759 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 2) |
| 760 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
| 761 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) |
| 762 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) |
| 763 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) |
| 764 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) |
| 765 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ |
| 766 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) |
| 767 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) |
| 768 | |
| 769 | |
| 770 | /* used on a CID received from the HW */ |
| 771 | #define SW_CID(x) (le32_to_cpu(x) & \ |
| 772 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 1)) |
| 773 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ |
| 774 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) |
| 775 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 776 | #define STROM_ASSERT_ARRAY_SIZE 50 |
| 777 | |
| 778 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 779 | |
| 780 | /* must be used on a CID before placing it on a HW ring */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 781 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 782 | |
| 783 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) |
| 784 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) |
| 785 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 786 | |
| 787 | #define BNX2X_BTR 3 |
| 788 | #define MAX_SPQ_PENDING 8 |
| 789 | |
| 790 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 791 | #define DPM_TRIGER_TYPE 0x40 |
| 792 | #define DOORBELL(bp, cid, val) \ |
| 793 | do { \ |
| 794 | writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \ |
| 795 | DPM_TRIGER_TYPE); \ |
| 796 | } while (0) |
| 797 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 798 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
| 799 | int wait) |
| 800 | { |
| 801 | u32 val; |
| 802 | |
| 803 | do { |
| 804 | val = REG_RD(bp, reg); |
| 805 | if (val == expected) |
| 806 | break; |
| 807 | ms -= wait; |
| 808 | msleep(wait); |
| 809 | |
| 810 | } while (ms > 0); |
| 811 | |
| 812 | return val; |
| 813 | } |
| 814 | |
| 815 | |
| 816 | /* load/unload mode */ |
| 817 | #define LOAD_NORMAL 0 |
| 818 | #define LOAD_OPEN 1 |
| 819 | #define LOAD_DIAG 2 |
| 820 | #define UNLOAD_NORMAL 0 |
| 821 | #define UNLOAD_CLOSE 1 |
| 822 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 823 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 824 | /* DMAE command defines */ |
| 825 | #define DMAE_CMD_SRC_PCI 0 |
| 826 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC |
| 827 | |
| 828 | #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT) |
| 829 | #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT) |
| 830 | |
| 831 | #define DMAE_CMD_C_DST_PCI 0 |
| 832 | #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) |
| 833 | |
| 834 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE |
| 835 | |
| 836 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 837 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 838 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 839 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 840 | |
| 841 | #define DMAE_CMD_PORT_0 0 |
| 842 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT |
| 843 | |
| 844 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET |
| 845 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET |
| 846 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT |
| 847 | |
| 848 | #define DMAE_LEN32_RD_MAX 0x80 |
| 849 | #define DMAE_LEN32_WR_MAX 0x400 |
| 850 | |
| 851 | #define DMAE_COMP_VAL 0xe0d0d0ae |
| 852 | |
| 853 | #define MAX_DMAE_C_PER_PORT 8 |
| 854 | #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ |
| 855 | BP_E1HVN(bp)) |
| 856 | #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ |
| 857 | E1HVN_MAX) |
| 858 | |
| 859 | |
Eliezer Tamir | 2504795 | 2008-02-28 11:50:16 -0800 | [diff] [blame] | 860 | /* PCIE link and speed */ |
| 861 | #define PCICFG_LINK_WIDTH 0x1f00000 |
| 862 | #define PCICFG_LINK_WIDTH_SHIFT 20 |
| 863 | #define PCICFG_LINK_SPEED 0xf0000 |
| 864 | #define PCICFG_LINK_SPEED_SHIFT 16 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 865 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame^] | 866 | |
| 867 | #define BNX2X_NUM_STATS 39 |
| 868 | #define BNX2X_NUM_TESTS 8 |
| 869 | |
| 870 | #define BNX2X_MAC_LOOPBACK 0 |
| 871 | #define BNX2X_PHY_LOOPBACK 1 |
| 872 | #define BNX2X_MAC_LOOPBACK_FAILED 1 |
| 873 | #define BNX2X_PHY_LOOPBACK_FAILED 2 |
| 874 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
| 875 | BNX2X_PHY_LOOPBACK_FAILED) |
Eliezer Tamir | 96fc178 | 2008-02-28 11:57:55 -0800 | [diff] [blame] | 876 | |
| 877 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) |
| 878 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 879 | /* must be used on a CID before placing it on a HW ring */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 880 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 881 | #define BNX2X_RX_SUM_OK(cqe) \ |
| 882 | (!(cqe->fast_path_cqe.status_flags & \ |
| 883 | (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ |
| 884 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) |
| 885 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 886 | /* CMNG constants |
| 887 | derived from lab experiments, and not from system spec calculations !!! */ |
| 888 | #define DEF_MIN_RATE 100 |
| 889 | /* resolution of the rate shaping timer - 100 usec */ |
| 890 | #define RS_PERIODIC_TIMEOUT_USEC 100 |
| 891 | /* resolution of fairness algorithm in usecs - |
| 892 | coefficient for clauclating the actuall t fair */ |
| 893 | #define T_FAIR_COEF 10000000 |
| 894 | /* number of bytes in single QM arbitration cycle - |
| 895 | coeffiecnt for calculating the fairness timer */ |
| 896 | #define QM_ARB_BYTES 40000 |
| 897 | #define FAIR_MEM 2 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 898 | |
| 899 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 900 | #define ATTN_NIG_FOR_FUNC (1L << 8) |
| 901 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) |
| 902 | #define GPIO_2_FUNC (1L << 10) |
| 903 | #define GPIO_3_FUNC (1L << 11) |
| 904 | #define GPIO_4_FUNC (1L << 12) |
| 905 | #define ATTN_GENERAL_ATTN_1 (1L << 13) |
| 906 | #define ATTN_GENERAL_ATTN_2 (1L << 14) |
| 907 | #define ATTN_GENERAL_ATTN_3 (1L << 15) |
| 908 | #define ATTN_GENERAL_ATTN_4 (1L << 13) |
| 909 | #define ATTN_GENERAL_ATTN_5 (1L << 14) |
| 910 | #define ATTN_GENERAL_ATTN_6 (1L << 15) |
| 911 | |
| 912 | #define ATTN_HARD_WIRED_MASK 0xff00 |
| 913 | #define ATTENTION_ID 4 |
| 914 | |
| 915 | |
| 916 | /* stuff added to make the code fit 80Col */ |
| 917 | |
| 918 | #define BNX2X_PMF_LINK_ASSERT \ |
| 919 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) |
| 920 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 921 | #define BNX2X_MC_ASSERT_BITS \ |
| 922 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 923 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 924 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 925 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) |
| 926 | |
| 927 | #define BNX2X_MCP_ASSERT \ |
| 928 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) |
| 929 | |
| 930 | #define BNX2X_DOORQ_ASSERT \ |
| 931 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT |
| 932 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 933 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
| 934 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ |
| 935 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ |
| 936 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ |
| 937 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ |
| 938 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ |
| 939 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) |
| 940 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 941 | #define HW_INTERRUT_ASSERT_SET_0 \ |
| 942 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ |
| 943 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ |
| 944 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ |
| 945 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 946 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 947 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
| 948 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ |
| 949 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ |
| 950 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) |
| 951 | #define HW_INTERRUT_ASSERT_SET_1 \ |
| 952 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ |
| 953 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ |
| 954 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ |
| 955 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ |
| 956 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ |
| 957 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ |
| 958 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ |
| 959 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ |
| 960 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ |
| 961 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ |
| 962 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 963 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 964 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
| 965 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ |
| 966 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ |
| 967 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
| 968 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ |
| 969 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
| 970 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ |
| 971 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ |
| 972 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ |
| 973 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) |
| 974 | #define HW_INTERRUT_ASSERT_SET_2 \ |
| 975 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ |
| 976 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ |
| 977 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ |
| 978 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ |
| 979 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 980 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 981 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
| 982 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ |
| 983 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ |
| 984 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ |
| 985 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ |
| 986 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) |
| 987 | |
| 988 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 989 | #define MULTI_FLAGS \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 990 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
| 991 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ |
| 992 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ |
| 993 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ |
| 994 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 995 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 996 | #define MULTI_MASK 0x7f |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 997 | |
| 998 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 999 | #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES) |
| 1000 | #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES) |
| 1001 | #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES) |
| 1002 | #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1003 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1004 | #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1005 | |
| 1006 | #define BNX2X_SP_DSB_INDEX \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1007 | (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1008 | |
| 1009 | |
| 1010 | #define CAM_IS_INVALID(x) \ |
| 1011 | (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
| 1012 | |
| 1013 | #define CAM_INVALIDATE(x) \ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1014 | (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1015 | |
| 1016 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1017 | /* Number of u32 elements in MC hash array */ |
| 1018 | #define MC_HASH_SIZE 8 |
| 1019 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ |
| 1020 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) |
| 1021 | |
| 1022 | |
| 1023 | #ifndef PXP2_REG_PXP2_INT_STS |
| 1024 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 |
| 1025 | #endif |
| 1026 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1027 | /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ |
| 1028 | |
| 1029 | #endif /* bnx2x.h */ |