Sujit Reddy Thumma | c69c44b | 2013-04-02 10:30:40 +0530 | [diff] [blame] | 1 | Introduction |
| 2 | ============ |
| 3 | The SATA Host Controller developed for Qualcomm SoC is used |
| 4 | to facilitate SATA storage devices that connect to SoC through a |
| 5 | standard SATA cable interface. The MSM Advanced Host Controller |
| 6 | Interface (AHCI) driver interfaces with the generic Linux AHCI driver |
| 7 | and communicates with the AHCI controller for data movement between |
| 8 | system memory and SATA devices (persistent storage). |
| 9 | |
| 10 | Hardware description |
| 11 | ==================== |
| 12 | Serial Advanced Technology Attachment (SATA) is a communication |
| 13 | protocol designed to transfer data between a computer and storage |
| 14 | devices (Hard Disk Drive(HDD), Solid State Drives(SSD) etc.). |
| 15 | First generation (Gen1) SATA interfaces communicate at a serial |
| 16 | rate of 1.5Gb/s and use low-voltage differential signaling on |
| 17 | serial links. With 8b-10b encoding, the effective data throughput |
| 18 | for Gen1 interface is 150MB/s. |
| 19 | |
| 20 | The SATA host controller in Qualcomm chipsets adheres to the AHCI 1.3 |
| 21 | specification which describes the interface between system software |
| 22 | and the host controller, as well as the functional behavior needed |
| 23 | for software to communicate with the SATA host controller. |
| 24 | |
| 25 | The SATA PHY hardware macro in Qualcomm chipsets adheres to the |
| 26 | SATA 3.0 specification with Gen1 serial interface. This is used to |
| 27 | serialize and de-serialize data and communicates with SATA HDD. Also, |
| 28 | the PHY can detect SATA HDD during hot swap and raise an interrupt to |
| 29 | the CPU through AHCI controller to notify about the detection/removal. |
| 30 | |
| 31 | The following figure shows the SATA architecture block diagram as |
| 32 | implemented in MSM chipsets. |
| 33 | |
| 34 | +---------+ |
| 35 | |SATA Disk| |
| 36 | | Drive | |
| 37 | +---------+ |
| 38 | ^ ^ |
| 39 | Tx | | Rx |
| 40 | v v |
| 41 | +--------------+ +--------------+ +-----------+ |
| 42 | | System Memory| | SATA PHY | | CPU | |
| 43 | +--------------+ +--------------+ +-----------+ |
| 44 | ^ ^ ^ ^ ^ |
| 45 | | | | | | |
| 46 | | v v | | |
| 47 | | +------------------+(Interrupt)| |
| 48 | | | SATA CONTROLLER |-----+ | |
| 49 | | +------------------+ | |
| 50 | | ^ ^ | |
| 51 | | | | | |
| 52 | v v v v |
| 53 | <---------------------------------------------------------> |
| 54 | < System Fabric (Control and Data) > |
| 55 | <---------------------------------------------------------> |
| 56 | |
| 57 | Some controller capabilities: |
| 58 | - Supports 64-bit addressing |
| 59 | - Supports native command queueing (upto 32 commands) |
| 60 | - Supports First-party DMA to move data to and from system memory |
| 61 | - ATA-7 command set compliant |
| 62 | - Port multiplier support for some chipsets |
| 63 | - Supports aggressive power management (partial, slumber modes) |
| 64 | - Supports asynchronous notification |
| 65 | |
| 66 | Software description |
| 67 | ==================== |
| 68 | The SATA driver uses the generic interface to read/write data to |
| 69 | the Hard Disk Drive (HDD). It uses following components in Linux |
| 70 | to interface with the generic block layer which then interfaces |
| 71 | with file system or user processes. |
| 72 | |
| 73 | 1) AHCI platform Driver (includes MSM-specific glue driver) |
| 74 | 2) LIBAHCI |
| 75 | 3) LIBATA |
| 76 | 4) SCSI |
| 77 | |
| 78 | AHCI platform driver registers as a device driver for platform |
| 79 | device registered during SoC board initialization. It is responsible |
| 80 | for platform specific tasks like PHY configuration, clock initial- |
| 81 | ization, claiming memory resources etc. Also, implements certain |
| 82 | functionality that deviates from the standard specification. |
| 83 | |
| 84 | Library "LIBAHCI" implements software layer functionality described |
| 85 | in the standard AHCI specification. It interfaces with the LIBATA |
| 86 | framework to execute SATA the command set. It converts ATA task files |
| 87 | into AHCI command descriptors and pass them to the controller for |
| 88 | execution. It handles controller interrupts and sends command |
| 89 | completion events to the upper layers. It implements a controller- |
| 90 | specific reset and recover mechanism in case of errors. It implements |
| 91 | link power management policies - partial, slumber modes, runtime power |
| 92 | management and platform power management. It abstracts the low-level |
| 93 | controller details from the LIBATA framework. |
| 94 | |
| 95 | "LIBATA" is a helper library for implementing ATA and SATA command |
| 96 | protocol as described in standard ATA and SATA specifications. It |
| 97 | builds read/write requests from SCSI commands and pass them to the |
| 98 | low-level controller driver (LLD). It handshakes with the SATA |
| 99 | device using standard commands to understand capabilities and carry |
| 100 | out device configurations. It interfaces with the SCSI layer to manage |
| 101 | underlying disks. It manages different devices connected to each host |
| 102 | port using a port multiplier. Also, it manages the link PHY component, |
| 103 | the interconnect interface and any external interface (cables, etc.) |
| 104 | that follow the SATA electrical specification. |
| 105 | |
| 106 | The SCSI layer is a helper library for translating generic block layer |
| 107 | commands to SCSI commands and pass them on to the LIBATA framework. |
| 108 | Certain generic stuff like device scan, media change, and hot plug |
| 109 | detection are handled. This layer handles all types of SCSI devices, |
| 110 | and SATA storage devices are one class of SCSI devices. It also provides |
| 111 | the IOCTL interface to manage disks from userspace. |
| 112 | |
| 113 | Following is the logical code flow: |
| 114 | |
| 115 | +------------------------+ |
| 116 | | File System (ext4 etc.)| |
| 117 | +------------------------+ |
| 118 | ^ |
| 119 | | |
| 120 | v |
| 121 | +------------------------+ |
| 122 | | Generic Block Layer | |
| 123 | +------------------------+ |
| 124 | ^ |
| 125 | | |
| 126 | v |
| 127 | +------------------------+ |
| 128 | | SCSI Layer | |
| 129 | +------------------------+ |
| 130 | ^ |
| 131 | | |
| 132 | v |
| 133 | +------------------------+ |
| 134 | | LIBATA library | |
| 135 | +------------------------+ |
| 136 | ^ |
| 137 | | |
| 138 | v |
| 139 | +------------------------+ |
| 140 | | LIBAHCI library | |
| 141 | +------------------------+ |
| 142 | ^ |
| 143 | | |
| 144 | v |
| 145 | +------------------------+ |
| 146 | | AHCI platform driver + | |
| 147 | | MSM AHCI glue driver | |
| 148 | +------------------------+ |
| 149 | |
| 150 | Design |
| 151 | ====== |
| 152 | The MSM AHCI driver acts as a glue driver for the Linux |
| 153 | AHCI controller driver. It provides the following functionality: |
| 154 | - Registers as a driver for msm_sata device which has an AHCI-compliant |
| 155 | controller and PHY as resources. |
| 156 | - Registers an AHCI platform device in the probe function providing |
| 157 | ahci platform data |
| 158 | - AHCI platform data consists of the following callbacks: |
| 159 | - init |
| 160 | o PHY resource acquisition |
| 161 | o Clock and voltage regulator initialization |
| 162 | o PHY calibration |
| 163 | - exit |
| 164 | o PHY power down |
| 165 | o Clock and voltage regulator turn off |
| 166 | - suspend |
| 167 | - resume |
| 168 | o Sequence described in the next section. |
| 169 | - The Linux AHCI platform driver then probes the AHCI device and |
| 170 | initializes it according to the standard AHCI specification. |
| 171 | - The SATA drive is detected as part of scsi_scan_host() called by |
| 172 | LIBAHCI after controller initialization. |
| 173 | |
| 174 | Power Management |
| 175 | ================ |
| 176 | Various power modes are supported by this driver. |
| 177 | |
| 178 | Platform suspend/resume: |
| 179 | During suspend: |
| 180 | - PHY analog blocks are powered down |
| 181 | - Controller and PHY is kept in Power-on-Reset (POR) mode |
| 182 | - Clocks and voltage regulators are gated |
| 183 | |
| 184 | During resume: |
| 185 | - Clocks and voltage regulators are ungated |
| 186 | - PHY is powered up and calibrated to functional mode |
| 187 | - Controller is re-initialized to process commands. |
| 188 | |
| 189 | Runtime suspend/resume: |
| 190 | - Execute the same steps as in platform suspend/resume. |
| 191 | - Runtime suspend/resume is disabled by default due to regressions |
| 192 | in hot-plug detection (specification limitation). The users can |
| 193 | enable runtime power management with following shell commands. |
| 194 | |
| 195 | # cd /sys/devices/platform/msm_sata.0/ahci.0/ |
| 196 | # echo auto > ./power/control |
| 197 | # echo auto > ./ata1/power/control |
| 198 | # echo auto > ./ata1/host0/target0:0:0/0:0:0:0/power/control |
| 199 | |
| 200 | Note: The device will be runtime-suspended only when user unmounts |
| 201 | all the partitions. |
| 202 | |
| 203 | Link power management (defined by AHCI 1.3 specification): |
| 204 | - Automatic low power mode transition are supported. |
| 205 | - AHCI supports two power modes: partial and slumber. |
| 206 | - Software uses Inteface Communication Control (ICC) bits in AHCI |
| 207 | register space to enable automatic partial/slumber state. |
| 208 | - Partial mode: |
| 209 | - Software asserts automatic partial mode when the use |
| 210 | case demands low latency resume. |
| 211 | - Upon receiving partial mode signal, PHY disables byte clocks |
| 212 | and re-enables them during resume and thus has low latency. |
| 213 | - Slumber mode: |
| 214 | - Software asserts automatic slumber mode when the use |
| 215 | case demands low power consumption and can withstand |
| 216 | high resume latencies. |
| 217 | - Upon receiving slumber mode signal, PHY disables byte |
| 218 | clocks and some internal circuitry. Upon resume PHY |
| 219 | enables byte clocks and reacquires the PLL lock. |
| 220 | - Once the software enables partial/slumber modes, the transitioning |
| 221 | into these modes are automatic and is handled by hardware without |
| 222 | software intervention while the controller is idle with no outstanding |
| 223 | commands to process. |
| 224 | |
| 225 | - The Linux AHCI link power management defines three modes: |
| 226 | - max_performance (default mode) |
| 227 | Doesn't allow partial/slumber transition when host is idle. |
| 228 | - medium_power (Partial mode) |
| 229 | Following shell commands are used to enable this mode: |
| 230 | |
| 231 | # cd /sys/devices/platform/msm_sata.0/ahci.0/ |
| 232 | # echo medium_power > ./ata1/host0/scsi_host/host0/link_power_management_policy |
| 233 | |
| 234 | - min_power (Slumber mode) |
| 235 | Following shell commands are used to enable this mode: |
| 236 | |
| 237 | # cd /sys/devices/platform/msm_sata.0/ahci.0/ |
| 238 | # echo min_power > ./ata1/host0/scsi_host/host0/link_power_management_policy |
| 239 | |
| 240 | SMP/multi-core |
| 241 | ============== |
| 242 | The MSM AHCI driver hooks only init, exit, suspend, resume callbacks to |
| 243 | the AHCI driver which are serialized by design and hence the driver, which |
| 244 | is inherently SMP safe. |
| 245 | |
| 246 | Security |
| 247 | ======== |
| 248 | None. |
| 249 | |
| 250 | Performance |
| 251 | =========== |
| 252 | The theoretical performance with Gen1 SATA PHY is 150MB/s (8b/10b encoding). |
| 253 | The performance is dependent on various factors, mainly: |
| 254 | - Capabilities of the external SATA hard disk connected to the MSM SATA port |
| 255 | - Various system bus frequencies and system loads |
| 256 | - System memory capabilities |
| 257 | - Benchmark test applications that collect performance numbers |
| 258 | |
| 259 | One example of the maximum performance achieved in a specific system |
| 260 | configuration follows: |
| 261 | |
| 262 | Benchmark: Iozone sequential performance |
| 263 | Block size: 128K |
| 264 | File size: 1GB |
| 265 | Platform: APQ8064 V2 CDP |
| 266 | CPU Governor: Performance |
| 267 | |
| 268 | SanDisk SSD (i100 64GB): |
| 269 | Read - 135MB/s |
| 270 | Write - 125MB/s |
| 271 | |
| 272 | Western Digital HDD (WD20EURS 2TB): |
| 273 | Read - 121MB/s |
| 274 | Write - 98MB/s |
| 275 | |
| 276 | Interface |
| 277 | ========= |
| 278 | The MSM AHCI controller driver provides function pointers as the |
| 279 | required interface to the Linux AHCI controller driver. The main |
| 280 | routines implemented are init, exit, suspend, and resume for handling |
| 281 | MSM-specific initialization, freeing of resources on exit, and |
| 282 | MSM-specific power management tweaks during suspend power collapse. |
| 283 | |
| 284 | Driver parameters |
| 285 | ================= |
| 286 | None. |
| 287 | |
| 288 | Config options |
| 289 | ============== |
| 290 | Config option SATA_AHCI_MSM in drivers/ata/Kconfig enables this driver. |
| 291 | |
| 292 | Dependencies |
| 293 | ============ |
| 294 | The MSM AHCI controller driver is dependent on Linux AHCI driver, |
| 295 | Linux ATA framework, Linux SCSI framework and Linux generic block layer. |
| 296 | |
| 297 | While configuring the kernel, the following options should be set: |
| 298 | |
| 299 | - CONFIG_BLOCK |
| 300 | - CONFIG_SCSI |
| 301 | - CONFIG_ATA |
| 302 | - CONFIG_SATA_AHCI_PLATFORM |
| 303 | |
| 304 | User space utilities |
| 305 | ==================== |
| 306 | Any user space component that can mount a block device can be used to |
| 307 | read/write data into persistent storage. However, at the time of this |
| 308 | writing there are no utilities that author is aware of that can manage |
| 309 | h/w from userspace. |
| 310 | |
| 311 | Other |
| 312 | ===== |
| 313 | None. |
| 314 | |
| 315 | Known issues |
| 316 | ============ |
| 317 | None. |
| 318 | |
| 319 | To do |
| 320 | ===== |
| 321 | - Device tree support. |
| 322 | - MSM bus frequency voting support. |