| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * Board definitions for the Radstone PPC7D boards. |
| 3 | * |
| 4 | * Author: James Chapman <jchapman@katalix.com> |
| 5 | * |
| 6 | * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il |
| 7 | * Based on code done by - Mark A. Greer <mgreer@mvista.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | * option) any later version. |
| 13 | */ |
| 14 | |
| 15 | /* |
| 16 | * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to |
| 17 | * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. |
| 18 | * We'll only use one PCI MEM window on each PCI bus. |
| 19 | * |
| 20 | * This is the CPU physical memory map (windows must be at least 1MB |
| 21 | * and start on a boundary that is a multiple of the window size): |
| 22 | * |
| 23 | * 0xff800000-0xffffffff - Boot window |
| 24 | * 0xff000000-0xff000fff - AFIX registers (DevCS2) |
| 25 | * 0xfef00000-0xfef0ffff - Internal MV64x60 registers |
| 26 | * 0xfef40000-0xfef7ffff - Internal SRAM |
| 27 | * 0xfef00000-0xfef0ffff - MV64360 Registers |
| 28 | * 0x70000000-0x7fffffff - soldered flash (DevCS3) |
| 29 | * 0xe8000000-0xe9ffffff - PCI I/O |
| 30 | * 0x80000000-0xbfffffff - PCI MEM |
| 31 | */ |
| 32 | |
| 33 | #ifndef __PPC_PLATFORMS_PPC7D_H |
| 34 | #define __PPC_PLATFORMS_PPC7D_H |
| 35 | |
| 36 | #include <asm/ppcboot.h> |
| 37 | |
| 38 | /***************************************************************************** |
| 39 | * CPU Physical Memory Map setup. |
| 40 | *****************************************************************************/ |
| 41 | |
| 42 | #define PPC7D_BOOT_WINDOW_BASE 0xff800000 |
| 43 | #define PPC7D_AFIX_REG_BASE 0xff000000 |
| 44 | #define PPC7D_INTERNAL_SRAM_BASE 0xfef40000 |
| 45 | #define PPC7D_FLASH_BASE 0x70000000 |
| 46 | |
| 47 | #define PPC7D_BOOT_WINDOW_SIZE_ACTUAL 0x00800000 /* 8MB */ |
| 48 | #define PPC7D_FLASH_SIZE_ACTUAL 0x10000000 /* 256MB */ |
| 49 | |
| 50 | #define PPC7D_BOOT_WINDOW_SIZE max(MV64360_WINDOW_SIZE_MIN, \ |
| 51 | PPC7D_BOOT_WINDOW_SIZE_ACTUAL) |
| 52 | #define PPC7D_FLASH_SIZE max(MV64360_WINDOW_SIZE_MIN, \ |
| 53 | PPC7D_FLASH_SIZE_ACTUAL) |
| 54 | #define PPC7D_AFIX_REG_SIZE max(MV64360_WINDOW_SIZE_MIN, 0xff) |
| 55 | |
| 56 | |
| 57 | #define PPC7D_PCI0_MEM0_START_PROC_ADDR 0x80000000UL |
| 58 | #define PPC7D_PCI0_MEM0_START_PCI_HI_ADDR 0x00000000UL |
| 59 | #define PPC7D_PCI0_MEM0_START_PCI_LO_ADDR 0x80000000UL |
| 60 | #define PPC7D_PCI0_MEM0_SIZE 0x20000000UL |
| 61 | #define PPC7D_PCI0_MEM1_START_PROC_ADDR 0xe8010000UL |
| 62 | #define PPC7D_PCI0_MEM1_START_PCI_HI_ADDR 0x00000000UL |
| 63 | #define PPC7D_PCI0_MEM1_START_PCI_LO_ADDR 0x00000000UL |
| 64 | #define PPC7D_PCI0_MEM1_SIZE 0x000f0000UL |
| 65 | #define PPC7D_PCI0_IO_START_PROC_ADDR 0xe8000000UL |
| 66 | #define PPC7D_PCI0_IO_START_PCI_ADDR 0x00000000UL |
| 67 | #define PPC7D_PCI0_IO_SIZE 0x00010000UL |
| 68 | |
| 69 | #define PPC7D_PCI1_MEM0_START_PROC_ADDR 0xa0000000UL |
| 70 | #define PPC7D_PCI1_MEM0_START_PCI_HI_ADDR 0x00000000UL |
| 71 | #define PPC7D_PCI1_MEM0_START_PCI_LO_ADDR 0xa0000000UL |
| 72 | #define PPC7D_PCI1_MEM0_SIZE 0x20000000UL |
| 73 | #define PPC7D_PCI1_MEM1_START_PROC_ADDR 0xe9800000UL |
| 74 | #define PPC7D_PCI1_MEM1_START_PCI_HI_ADDR 0x00000000UL |
| 75 | #define PPC7D_PCI1_MEM1_START_PCI_LO_ADDR 0x00000000UL |
| 76 | #define PPC7D_PCI1_MEM1_SIZE 0x00800000UL |
| 77 | #define PPC7D_PCI1_IO_START_PROC_ADDR 0xe9000000UL |
| 78 | #define PPC7D_PCI1_IO_START_PCI_ADDR 0x00000000UL |
| 79 | #define PPC7D_PCI1_IO_SIZE 0x00010000UL |
| 80 | |
| 81 | #define PPC7D_DEFAULT_BAUD 9600 |
| 82 | #define PPC7D_MPSC_CLK_SRC 8 /* TCLK */ |
| 83 | #define PPC7D_MPSC_CLK_FREQ 133333333 /* 133.3333... MHz */ |
| 84 | |
| 85 | #define PPC7D_ETH0_PHY_ADDR 8 |
| 86 | #define PPC7D_ETH1_PHY_ADDR 9 |
| 87 | #define PPC7D_ETH2_PHY_ADDR 0 |
| 88 | |
| 89 | #define PPC7D_ETH_TX_QUEUE_SIZE 400 |
| 90 | #define PPC7D_ETH_RX_QUEUE_SIZE 400 |
| 91 | |
| 92 | #define PPC7D_ETH_PORT_CONFIG_VALUE \ |
| 93 | MV64340_ETH_UNICAST_NORMAL_MODE | \ |
| 94 | MV64340_ETH_DEFAULT_RX_QUEUE_0 | \ |
| 95 | MV64340_ETH_DEFAULT_RX_ARP_QUEUE_0 | \ |
| 96 | MV64340_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ |
| 97 | MV64340_ETH_RECEIVE_BC_IF_IP | \ |
| 98 | MV64340_ETH_RECEIVE_BC_IF_ARP | \ |
| 99 | MV64340_ETH_CAPTURE_TCP_FRAMES_DIS | \ |
| 100 | MV64340_ETH_CAPTURE_UDP_FRAMES_DIS | \ |
| 101 | MV64340_ETH_DEFAULT_RX_TCP_QUEUE_0 | \ |
| 102 | MV64340_ETH_DEFAULT_RX_UDP_QUEUE_0 | \ |
| 103 | MV64340_ETH_DEFAULT_RX_BPDU_QUEUE_0 |
| 104 | |
| 105 | #define PPC7D_ETH_PORT_CONFIG_EXTEND_VALUE \ |
| 106 | MV64340_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ |
| 107 | MV64340_ETH_PARTITION_DISABLE |
| 108 | |
| 109 | #define GT_ETH_IPG_INT_RX(value) \ |
| 110 | ((value & 0x3fff) << 8) |
| 111 | |
| 112 | #define PPC7D_ETH_PORT_SDMA_CONFIG_VALUE \ |
| 113 | MV64340_ETH_RX_BURST_SIZE_4_64BIT | \ |
| 114 | GT_ETH_IPG_INT_RX(0) | \ |
| 115 | MV64340_ETH_TX_BURST_SIZE_4_64BIT |
| 116 | |
| 117 | #define PPC7D_ETH_PORT_SERIAL_CONTROL_VALUE \ |
| 118 | MV64340_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ |
| 119 | MV64340_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ |
| 120 | MV64340_ETH_ADV_SYMMETRIC_FLOW_CTRL | \ |
| 121 | MV64340_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ |
| 122 | MV64340_ETH_FORCE_BP_MODE_NO_JAM | \ |
| 123 | (1 << 9) | \ |
| 124 | MV64340_ETH_DO_NOT_FORCE_LINK_FAIL | \ |
| 125 | MV64340_ETH_RETRANSMIT_16_ATTEMPTS | \ |
| 126 | MV64340_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ |
| 127 | MV64340_ETH_DTE_ADV_0 | \ |
| 128 | MV64340_ETH_DISABLE_AUTO_NEG_BYPASS | \ |
| 129 | MV64340_ETH_AUTO_NEG_NO_CHANGE | \ |
| 130 | MV64340_ETH_MAX_RX_PACKET_9700BYTE | \ |
| 131 | MV64340_ETH_CLR_EXT_LOOPBACK | \ |
| 132 | MV64340_ETH_SET_FULL_DUPLEX_MODE | \ |
| 133 | MV64340_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |
| 134 | |
| 135 | /***************************************************************************** |
| 136 | * Serial defines. |
| 137 | *****************************************************************************/ |
| 138 | |
| 139 | #define PPC7D_SERIAL_0 0xe80003f8 |
| 140 | #define PPC7D_SERIAL_1 0xe80002f8 |
| 141 | |
| 142 | #define RS_TABLE_SIZE 2 |
| 143 | |
| 144 | /* Rate for the 1.8432 Mhz clock for the onboard serial chip */ |
| 145 | #define UART_CLK 1843200 |
| 146 | #define BASE_BAUD ( UART_CLK / 16 ) |
| 147 | |
| 148 | #ifdef CONFIG_SERIAL_DETECT_IRQ |
| 149 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ) |
| 150 | #else |
| 151 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF) |
| 152 | #endif |
| 153 | |
| 154 | #define STD_SERIAL_PORT_DFNS \ |
| 155 | { 0, BASE_BAUD, PPC7D_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \ |
| 156 | iomem_base: (u8 *)PPC7D_SERIAL_0, \ |
| 157 | io_type: SERIAL_IO_MEM, }, \ |
| 158 | { 0, BASE_BAUD, PPC7D_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \ |
| 159 | iomem_base: (u8 *)PPC7D_SERIAL_1, \ |
| 160 | io_type: SERIAL_IO_MEM }, |
| 161 | |
| 162 | #define SERIAL_PORT_DFNS \ |
| 163 | STD_SERIAL_PORT_DFNS |
| 164 | |
| 165 | /***************************************************************************** |
| 166 | * CPLD defines. |
| 167 | * |
| 168 | * Register map:- |
| 169 | * |
| 170 | * 0000 to 000F South Bridge DMA 1 Control |
| 171 | * 0020 and 0021 South Bridge Interrupt 1 Control |
| 172 | * 0040 to 0043 South Bridge Counter Control |
| 173 | * 0060 Keyboard |
| 174 | * 0061 South Bridge NMI Status and Control |
| 175 | * 0064 Keyboard |
| 176 | * 0071 and 0072 RTC R/W |
| 177 | * 0078 to 007B South Bridge BIOS Timer |
| 178 | * 0080 to 0090 South Bridge DMA Pages |
| 179 | * 00A0 and 00A1 South Bridge Interrupt 2 Control |
| 180 | * 00C0 to 00DE South Bridge DMA 2 Control |
| 181 | * 02E8 to 02EF COM6 R/W |
| 182 | * 02F8 to 02FF South Bridge COM2 R/W |
| 183 | * 03E8 to 03EF COM5 R/W |
| 184 | * 03F8 to 03FF South Bridge COM1 R/W |
| 185 | * 040A South Bridge DMA Scatter/Gather RO |
| 186 | * 040B DMA 1 Extended Mode WO |
| 187 | * 0410 to 043F South Bridge DMA Scatter/Gather |
| 188 | * 0481 to 048B South Bridge DMA High Pages |
| 189 | * 04D0 and 04D1 South Bridge Edge/Level Control |
| 190 | * 04D6 DMA 2 Extended Mode WO |
| 191 | * 0804 Memory Configuration RO |
| 192 | * 0806 Memory Configuration Extend RO |
| 193 | * 0808 SCSI Activity LED R/W |
| 194 | * 080C Equipment Present 1 RO |
| 195 | * 080E Equipment Present 2 RO |
| 196 | * 0810 Equipment Present 3 RO |
| 197 | * 0812 Equipment Present 4 RO |
| 198 | * 0818 Key Lock RO |
| 199 | * 0820 LEDS R/W |
| 200 | * 0824 COMs R/W |
| 201 | * 0826 RTS R/W |
| 202 | * 0828 Reset R/W |
| 203 | * 082C Watchdog Trig R/W |
| 204 | * 082E Interrupt R/W |
| 205 | * 0830 Interrupt Status RO |
| 206 | * 0832 PCI configuration RO |
| 207 | * 0854 Board Revision RO |
| 208 | * 0858 Extended ID RO |
| 209 | * 0864 ID Link RO |
| 210 | * 0866 Motherboard Type RO |
| 211 | * 0868 FLASH Write control RO |
| 212 | * 086A Software FLASH write protect R/W |
| 213 | * 086E FLASH Control R/W |
| 214 | *****************************************************************************/ |
| 215 | |
| 216 | #define PPC7D_CPLD_MEM_CONFIG 0x0804 |
| 217 | #define PPC7D_CPLD_MEM_CONFIG_EXTEND 0x0806 |
| 218 | #define PPC7D_CPLD_SCSI_ACTIVITY_LED 0x0808 |
| 219 | #define PPC7D_CPLD_EQUIPMENT_PRESENT_1 0x080C |
| 220 | #define PPC7D_CPLD_EQUIPMENT_PRESENT_2 0x080E |
| 221 | #define PPC7D_CPLD_EQUIPMENT_PRESENT_3 0x0810 |
| 222 | #define PPC7D_CPLD_EQUIPMENT_PRESENT_4 0x0812 |
| 223 | #define PPC7D_CPLD_KEY_LOCK 0x0818 |
| 224 | #define PPC7D_CPLD_LEDS 0x0820 |
| 225 | #define PPC7D_CPLD_COMS 0x0824 |
| 226 | #define PPC7D_CPLD_RTS 0x0826 |
| 227 | #define PPC7D_CPLD_RESET 0x0828 |
| 228 | #define PPC7D_CPLD_WATCHDOG_TRIG 0x082C |
| 229 | #define PPC7D_CPLD_INTR 0x082E |
| 230 | #define PPC7D_CPLD_INTR_STATUS 0x0830 |
| 231 | #define PPC7D_CPLD_PCI_CONFIG 0x0832 |
| 232 | #define PPC7D_CPLD_BOARD_REVISION 0x0854 |
| 233 | #define PPC7D_CPLD_EXTENDED_ID 0x0858 |
| 234 | #define PPC7D_CPLD_ID_LINK 0x0864 |
| 235 | #define PPC7D_CPLD_MOTHERBOARD_TYPE 0x0866 |
| 236 | #define PPC7D_CPLD_FLASH_WRITE_CNTL 0x0868 |
| 237 | #define PPC7D_CPLD_SW_FLASH_WRITE_PROTECT 0x086A |
| 238 | #define PPC7D_CPLD_FLASH_CNTL 0x086E |
| 239 | |
| 240 | /* MEMORY_CONFIG_EXTEND */ |
| Chris Elston | 630710e | 2005-05-01 08:58:40 -0700 | [diff] [blame] | 241 | #define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | #define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0 |
| 243 | #define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0 |
| 244 | #define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40 |
| 245 | #define PPC7D_CPLD_SDRAM_BANK_SIZE_512M 0x80 |
| 246 | #define PPC7D_CPLD_SDRAM_BANK_SIZE_1G 0xc0 |
| 247 | #define PPC7D_CPLD_FLASH_DEV_SIZE_MASK 0x03 |
| 248 | #define PPC7D_CPLD_FLASH_BANK_NUM_MASK 0x0c |
| 249 | #define PPC7D_CPLD_FLASH_DEV_SIZE_64M 0 |
| 250 | #define PPC7D_CPLD_FLASH_DEV_SIZE_32M 1 |
| 251 | #define PPC7D_CPLD_FLASH_DEV_SIZE_16M 3 |
| 252 | #define PPC7D_CPLD_FLASH_BANK_NUM_4 0x00 |
| 253 | #define PPC7D_CPLD_FLASH_BANK_NUM_3 0x04 |
| 254 | #define PPC7D_CPLD_FLASH_BANK_NUM_2 0x08 |
| 255 | #define PPC7D_CPLD_FLASH_BANK_NUM_1 0x0c |
| 256 | |
| 257 | /* SCSI_LED */ |
| 258 | #define PPC7D_CPLD_SCSI_ACTIVITY_LED_OFF 0 |
| 259 | #define PPC7D_CPLD_SCSI_ACTIVITY_LED_ON 1 |
| 260 | |
| 261 | /* EQUIPMENT_PRESENT_1 */ |
| 262 | #define PPC7D_CPLD_EQPT_PRES_1_FITTED 0 |
| 263 | #define PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK (0x80 >> 2) |
| 264 | #define PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK (0x80 >> 3) |
| 265 | #define PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK (0x80 >> 4) |
| 266 | |
| 267 | /* EQUIPMENT_PRESENT_2 */ |
| 268 | #define PPC7D_CPLD_EQPT_PRES_2_FITTED !0 |
| 269 | #define PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK (0x80 >> 0) |
| 270 | #define PPC7D_CPLD_EQPT_PRES_2_COM36_MASK (0x80 >> 2) |
| 271 | #define PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK (0x80 >> 3) |
| 272 | #define PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK (0x80 >> 4) |
| 273 | |
| 274 | /* EQUIPMENT_PRESENT_3 */ |
| 275 | #define PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK (0x80 >> 3) |
| 276 | #define PPC7D_CPLD_EQPT_PRES_3_PMC2_5V (0 >> 3) |
| 277 | #define PPC7D_CPLD_EQPT_PRES_3_PMC2_3V (0x80 >> 3) |
| 278 | #define PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK (0x80 >> 4) |
| 279 | #define PPC7D_CPLD_EQPT_PRES_3_PMC1_5V (0 >> 4) |
| 280 | #define PPC7D_CPLD_EQPT_PRES_3_PMC1_3V (0x80 >> 4) |
| 281 | #define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK (0x80 >> 5) |
| 282 | #define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_INTER (0 >> 5) |
| 283 | #define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_VME (0x80 >> 5) |
| 284 | |
| 285 | /* EQUIPMENT_PRESENT_4 */ |
| 286 | #define PPC7D_CPLD_EQPT_PRES_4_LPT_MASK (0x80 >> 2) |
| 287 | #define PPC7D_CPLD_EQPT_PRES_4_LPT_FITTED (0x80 >> 2) |
| 288 | #define PPC7D_CPLD_EQPT_PRES_4_PS2_USB2_MASK (0xc0 >> 6) |
| 289 | #define PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED (0x40 >> 6) |
| 290 | #define PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED (0x80 >> 6) |
| 291 | |
| 292 | /* CPLD_LEDS */ |
| 293 | #define PPC7D_CPLD_LEDS_ON (!0) |
| 294 | #define PPC7D_CPLD_LEDS_OFF (0) |
| 295 | #define PPC7D_CPLD_LEDS_NVRAM_PAGE_MASK (0xc0 >> 2) |
| 296 | #define PPC7D_CPLD_LEDS_DS201_MASK (0x80 >> 4) |
| 297 | #define PPC7D_CPLD_LEDS_DS219_MASK (0x80 >> 5) |
| 298 | #define PPC7D_CPLD_LEDS_DS220_MASK (0x80 >> 6) |
| 299 | #define PPC7D_CPLD_LEDS_DS221_MASK (0x80 >> 7) |
| 300 | |
| 301 | /* CPLD_COMS */ |
| 302 | #define PPC7D_CPLD_COMS_COM3_TCLKEN (0x80 >> 0) |
| 303 | #define PPC7D_CPLD_COMS_COM3_RTCLKEN (0x80 >> 1) |
| 304 | #define PPC7D_CPLD_COMS_COM3_MODE_MASK (0x80 >> 2) |
| 305 | #define PPC7D_CPLD_COMS_COM3_MODE_RS232 (0) |
| 306 | #define PPC7D_CPLD_COMS_COM3_MODE_RS422 (0x80 >> 2) |
| 307 | #define PPC7D_CPLD_COMS_COM3_TXEN (0x80 >> 3) |
| 308 | #define PPC7D_CPLD_COMS_COM4_TCLKEN (0x80 >> 4) |
| 309 | #define PPC7D_CPLD_COMS_COM4_RTCLKEN (0x80 >> 5) |
| 310 | #define PPC7D_CPLD_COMS_COM4_MODE_MASK (0x80 >> 6) |
| 311 | #define PPC7D_CPLD_COMS_COM4_MODE_RS232 (0) |
| 312 | #define PPC7D_CPLD_COMS_COM4_MODE_RS422 (0x80 >> 6) |
| 313 | #define PPC7D_CPLD_COMS_COM4_TXEN (0x80 >> 7) |
| 314 | |
| 315 | /* CPLD_RTS */ |
| 316 | #define PPC7D_CPLD_RTS_COM36_LOOPBACK (0x80 >> 0) |
| 317 | #define PPC7D_CPLD_RTS_COM4_SCLK (0x80 >> 1) |
| 318 | #define PPC7D_CPLD_RTS_COM3_TXFUNC_MASK (0xc0 >> 2) |
| 319 | #define PPC7D_CPLD_RTS_COM3_TXFUNC_DISABLED (0 >> 2) |
| 320 | #define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED (0x80 >> 2) |
| 321 | #define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3 (0xc0 >> 2) |
| 322 | #define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3S (0xc0 >> 2) |
| 323 | #define PPC7D_CPLD_RTS_COM56_MODE_MASK (0x80 >> 4) |
| 324 | #define PPC7D_CPLD_RTS_COM56_MODE_RS232 (0) |
| 325 | #define PPC7D_CPLD_RTS_COM56_MODE_RS422 (0x80 >> 4) |
| 326 | #define PPC7D_CPLD_RTS_COM56_ENABLE_MASK (0x80 >> 5) |
| 327 | #define PPC7D_CPLD_RTS_COM56_DISABLED (0) |
| 328 | #define PPC7D_CPLD_RTS_COM56_ENABLED (0x80 >> 5) |
| 329 | #define PPC7D_CPLD_RTS_COM4_TXFUNC_MASK (0xc0 >> 6) |
| 330 | #define PPC7D_CPLD_RTS_COM4_TXFUNC_DISABLED (0 >> 6) |
| 331 | #define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED (0x80 >> 6) |
| 332 | #define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3 (0x40 >> 6) |
| 333 | #define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3S (0x40 >> 6) |
| 334 | |
| 335 | /* WATCHDOG_TRIG */ |
| 336 | #define PPC7D_CPLD_WDOG_CAUSE_MASK (0x80 >> 0) |
| 337 | #define PPC7D_CPLD_WDOG_CAUSE_NORMAL_RESET (0 >> 0) |
| 338 | #define PPC7D_CPLD_WDOG_CAUSE_WATCHDOG (0x80 >> 0) |
| 339 | #define PPC7D_CPLD_WDOG_ENABLE_MASK (0x80 >> 6) |
| 340 | #define PPC7D_CPLD_WDOG_ENABLE_OFF (0 >> 6) |
| 341 | #define PPC7D_CPLD_WDOG_ENABLE_ON (0x80 >> 6) |
| 342 | #define PPC7D_CPLD_WDOG_RESETSW_MASK (0x80 >> 7) |
| 343 | #define PPC7D_CPLD_WDOG_RESETSW_OFF (0 >> 7) |
| 344 | #define PPC7D_CPLD_WDOG_RESETSW_ON (0x80 >> 7) |
| 345 | |
| 346 | /* Interrupt mask and status bits */ |
| 347 | #define PPC7D_CPLD_INTR_TEMP_MASK (0x80 >> 0) |
| 348 | #define PPC7D_CPLD_INTR_HB8_MASK (0x80 >> 1) |
| 349 | #define PPC7D_CPLD_INTR_PHY1_MASK (0x80 >> 2) |
| 350 | #define PPC7D_CPLD_INTR_PHY0_MASK (0x80 >> 3) |
| 351 | #define PPC7D_CPLD_INTR_ISANMI_MASK (0x80 >> 5) |
| 352 | #define PPC7D_CPLD_INTR_CRITTEMP_MASK (0x80 >> 6) |
| 353 | |
| 354 | /* CPLD_INTR */ |
| 355 | #define PPC7D_CPLD_INTR_ENABLE_OFF (0) |
| 356 | #define PPC7D_CPLD_INTR_ENABLE_ON (!0) |
| 357 | |
| 358 | /* CPLD_INTR_STATUS */ |
| 359 | #define PPC7D_CPLD_INTR_STATUS_OFF (0) |
| 360 | #define PPC7D_CPLD_INTR_STATUS_ON (!0) |
| 361 | |
| 362 | /* CPLD_PCI_CONFIG */ |
| 363 | #define PPC7D_CPLD_PCI_CONFIG_PCI0_MASK 0x70 |
| 364 | #define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI33 0x00 |
| 365 | #define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI66 0x10 |
| 366 | #define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX33 0x40 |
| 367 | #define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX66 0x50 |
| 368 | #define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX100 0x60 |
| 369 | #define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX133 0x70 |
| 370 | #define PPC7D_CPLD_PCI_CONFIG_PCI1_MASK 0x07 |
| 371 | #define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI33 0x00 |
| 372 | #define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI66 0x01 |
| 373 | #define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX33 0x04 |
| 374 | #define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX66 0x05 |
| 375 | #define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX100 0x06 |
| 376 | #define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX133 0x07 |
| 377 | |
| 378 | /* CPLD_BOARD_REVISION */ |
| 379 | #define PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK 0xe0 |
| 380 | #define PPC7D_CPLD_BOARD_REVISION_LETTER_MASK 0x1f |
| 381 | |
| 382 | /* CPLD_EXTENDED_ID */ |
| 383 | #define PPC7D_CPLD_EXTENDED_ID_PPC7D 0x18 |
| 384 | |
| 385 | /* CPLD_ID_LINK */ |
| 386 | #define PPC7D_CPLD_ID_LINK_VME64_GAP_MASK (0x80 >> 2) |
| 387 | #define PPC7D_CPLD_ID_LINK_VME64_GA4_MASK (0x80 >> 3) |
| 388 | #define PPC7D_CPLD_ID_LINK_E13_MASK (0x80 >> 4) |
| 389 | #define PPC7D_CPLD_ID_LINK_E12_MASK (0x80 >> 5) |
| 390 | #define PPC7D_CPLD_ID_LINK_E7_MASK (0x80 >> 6) |
| 391 | #define PPC7D_CPLD_ID_LINK_E6_MASK (0x80 >> 7) |
| 392 | |
| 393 | /* CPLD_MOTHERBOARD_TYPE */ |
| 394 | #define PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK (0x80 >> 0) |
| 395 | #define PPC7D_CPLD_MB_TYPE_ECC_ENABLED (0x80 >> 0) |
| 396 | #define PPC7D_CPLD_MB_TYPE_ECC_DISABLED (0 >> 0) |
| 397 | #define PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK (0x80 >> 3) |
| 398 | #define PPC7D_CPLD_MB_TYPE_PLL_MASK 0x0c |
| 399 | #define PPC7D_CPLD_MB_TYPE_PLL_133 0x00 |
| 400 | #define PPC7D_CPLD_MB_TYPE_PLL_100 0x08 |
| 401 | #define PPC7D_CPLD_MB_TYPE_PLL_64 0x04 |
| 402 | #define PPC7D_CPLD_MB_TYPE_HW_ID_MASK 0x03 |
| 403 | |
| 404 | /* CPLD_FLASH_WRITE_CNTL */ |
| 405 | #define PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK (0x80 >> 0) |
| 406 | #define PPD7D_CPLD_FLASH_CNTL_WR_LINK_FITTED (0x80 >> 0) |
| 407 | #define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK (0x80 >> 2) |
| 408 | #define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_FITTED (0x80 >> 2) |
| 409 | #define PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK (0x80 >> 3) |
| 410 | #define PPD7D_CPLD_FLASH_CNTL_USER_LINK_FITTED (0x80 >> 3) |
| 411 | #define PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK (0x80 >> 5) |
| 412 | #define PPD7D_CPLD_FLASH_CNTL_RECO_WR_ENABLED (0x80 >> 5) |
| 413 | #define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK (0x80 >> 6) |
| 414 | #define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_ENABLED (0x80 >> 6) |
| 415 | #define PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK (0x80 >> 7) |
| 416 | #define PPD7D_CPLD_FLASH_CNTL_USER_WR_ENABLED (0x80 >> 7) |
| 417 | |
| 418 | /* CPLD_SW_FLASH_WRITE_PROTECT */ |
| 419 | #define PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED (!0) |
| 420 | #define PPC7D_CPLD_SW_FLASH_WRPROT_DISABLED (0) |
| 421 | #define PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK (0x80 >> 6) |
| 422 | #define PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK (0x80 >> 7) |
| 423 | |
| 424 | /* CPLD_FLASH_WRITE_CNTL */ |
| 425 | #define PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK (0x80 >> 0) |
| 426 | #define PPC7D_CPLD_FLASH_CNTL_NVRAM_DISABLED (0 >> 0) |
| 427 | #define PPC7D_CPLD_FLASH_CNTL_NVRAM_ENABLED (0x80 >> 0) |
| 428 | #define PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK (0x80 >> 1) |
| 429 | #define PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK (0x80 >> 2) |
| 430 | #define PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK (0x80 >> 3) |
| 431 | |
| 432 | |
| 433 | #endif /* __PPC_PLATFORMS_PPC7D_H */ |