blob: 7e1859ba5f8365c66cfd9177c1fba689adbcaf85 [file] [log] [blame]
Andre Silvabd897822011-06-10 13:08:14 -03001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/smsc911x.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx53.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34
35#include "crm_regs.h"
36#include "devices-imx53.h"
37
38#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
39
40static iomux_v3_cfg_t mx53_ard_pads[] = {
41 /* UART1 */
42 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
43 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
44 /* WEIM for CS1 */
45 MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
46 MX53_PAD_EIM_D16__EMI_WEIM_D_16,
47 MX53_PAD_EIM_D17__EMI_WEIM_D_17,
48 MX53_PAD_EIM_D18__EMI_WEIM_D_18,
49 MX53_PAD_EIM_D19__EMI_WEIM_D_19,
50 MX53_PAD_EIM_D20__EMI_WEIM_D_20,
51 MX53_PAD_EIM_D21__EMI_WEIM_D_21,
52 MX53_PAD_EIM_D22__EMI_WEIM_D_22,
53 MX53_PAD_EIM_D23__EMI_WEIM_D_23,
54 MX53_PAD_EIM_D24__EMI_WEIM_D_24,
55 MX53_PAD_EIM_D25__EMI_WEIM_D_25,
56 MX53_PAD_EIM_D26__EMI_WEIM_D_26,
57 MX53_PAD_EIM_D27__EMI_WEIM_D_27,
58 MX53_PAD_EIM_D28__EMI_WEIM_D_28,
59 MX53_PAD_EIM_D29__EMI_WEIM_D_29,
60 MX53_PAD_EIM_D30__EMI_WEIM_D_30,
61 MX53_PAD_EIM_D31__EMI_WEIM_D_31,
62 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
63 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
64 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
65 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
66 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
67 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
68 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
69 MX53_PAD_EIM_OE__EMI_WEIM_OE,
70 MX53_PAD_EIM_RW__EMI_WEIM_RW,
71 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
72};
73
74static struct resource ard_smsc911x_resources[] = {
75 {
76 .start = MX53_CS1_64MB_BASE_ADDR,
77 .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
78 .flags = IORESOURCE_MEM,
79 },
80 {
81 .start = gpio_to_irq(ARD_ETHERNET_INT_B),
82 .end = gpio_to_irq(ARD_ETHERNET_INT_B),
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87struct smsc911x_platform_config ard_smsc911x_config = {
88 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
89 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
90 .flags = SMSC911X_USE_32BIT,
91};
92
93static struct platform_device ard_smsc_lan9220_device = {
94 .name = "smsc911x",
95 .id = -1,
96 .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
97 .resource = ard_smsc911x_resources,
98 .dev = {
99 .platform_data = &ard_smsc911x_config,
100 },
101};
102
103static void __init mx53_ard_io_init(void)
104{
105 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
106 ARRAY_SIZE(mx53_ard_pads));
107
108 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
109 gpio_direction_input(ARD_ETHERNET_INT_B);
110}
111
112 /* Config CS1 settings for ethernet controller */
113static int weim_cs_config(void)
114{
115 u32 reg;
116 void __iomem *weim_base, *iomuxc_base;
117
118 weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
119 if (!weim_base)
120 return -ENOMEM;
121
122 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
123 if (!iomuxc_base)
124 return -ENOMEM;
125
126 /* CS1 timings for LAN9220 */
127 writel(0x20001, (weim_base + 0x18));
128 writel(0x0, (weim_base + 0x1C));
129 writel(0x16000202, (weim_base + 0x20));
130 writel(0x00000002, (weim_base + 0x24));
131 writel(0x16002082, (weim_base + 0x28));
132 writel(0x00000000, (weim_base + 0x2C));
133 writel(0x00000000, (weim_base + 0x90));
134
135 /* specify 64 MB on CS1 and CS0 on GPR1 */
136 reg = readl(iomuxc_base + 0x4);
137 reg &= ~0x3F;
138 reg |= 0x1B;
139 writel(reg, (iomuxc_base + 0x4));
140
141 iounmap(iomuxc_base);
142 iounmap(weim_base);
143
144 return 0;
145}
146
147static struct platform_device *devices[] __initdata = {
148 &ard_smsc_lan9220_device,
149};
150
151static void __init mx53_ard_board_init(void)
152{
153 imx53_soc_init();
154 imx53_add_imx_uart(0, NULL);
155
156 mx53_ard_io_init();
157 weim_cs_config();
158 platform_add_devices(devices, ARRAY_SIZE(devices));
159}
160
161static void __init mx53_ard_timer_init(void)
162{
163 mx53_clocks_init(32768, 24000000, 22579200, 0);
164}
165
166static struct sys_timer mx53_ard_timer = {
167 .init = mx53_ard_timer_init,
168};
169
170MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
171 .map_io = mx53_map_io,
172 .init_early = imx53_init_early,
173 .init_irq = mx53_init_irq,
174 .timer = &mx53_ard_timer,
175 .init_machine = mx53_ard_board_init,
176MACHINE_END