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Paul Walmsley543d9372008-03-18 10:22:06 +02001/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
Tony Lindgrena16e9702008-03-18 11:56:39 +02004 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
6 *
7 * Contacts:
Paul Walmsley543d9372008-03-18 10:22:06 +02008 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley543d9372008-03-18 10:22:06 +02009 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
Russell Kinga09e64f2008-08-05 16:14:15 +010019#include <mach/clock.h>
Paul Walmsley543d9372008-03-18 10:22:06 +020020
Paul Walmsley88b8ba92008-07-03 12:24:46 +030021/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23
Russell Kingc0bf3132009-02-19 13:29:22 +000024/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
25#define CORE_CLK_SRC_32K 0x0
26#define CORE_CLK_SRC_DPLL 0x1
27#define CORE_CLK_SRC_DPLL_X2 0x2
28
29/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
30#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
31#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
32#define OMAP2XXX_EN_DPLL_LOCKED 0x3
33
34/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
35#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
37#define OMAP3XXX_EN_DPLL_LOCKED 0x7
38
Tony Lindgren646e3ed2008-10-06 15:49:36 +030039int omap2_clk_init(void);
Paul Walmsley543d9372008-03-18 10:22:06 +020040int omap2_clk_enable(struct clk *clk);
41void omap2_clk_disable(struct clk *clk);
42long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
43int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
44int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
Paul Walmsleyfecb4942009-01-27 19:12:50 -070045int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
Paul Walmsley88b8ba92008-07-03 12:24:46 +030046long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
Paul Walmsley543d9372008-03-18 10:22:06 +020047
48#ifdef CONFIG_OMAP_RESET_CLOCKS
49void omap2_clk_disable_unused(struct clk *clk);
50#else
51#define omap2_clk_disable_unused NULL
52#endif
53
Russell King8b9dbc12009-02-12 10:12:59 +000054unsigned long omap2_clksel_recalc(struct clk *clk);
Paul Walmsley333943b2008-08-19 11:08:45 +030055void omap2_init_clk_clkdm(struct clk *clk);
Paul Walmsley543d9372008-03-18 10:22:06 +020056void omap2_init_clksel_parent(struct clk *clk);
57u32 omap2_clksel_get_divisor(struct clk *clk);
58u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
59 u32 *new_div);
60u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
61u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
Russell King8b9dbc12009-02-12 10:12:59 +000062unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
Paul Walmsley543d9372008-03-18 10:22:06 +020063long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
64int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
65u32 omap2_get_dpll_rate(struct clk *clk);
66int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
Tony Lindgrenff00fcc2008-07-03 12:24:44 +030067void omap2_clk_prepare_for_reboot(void);
Paul Walmsley543d9372008-03-18 10:22:06 +020068
Russell Kingb36ee722008-11-04 17:59:52 +000069extern const struct clkops clkops_omap2_dflt_wait;
Russell Kingbc51da42008-11-04 18:59:32 +000070extern const struct clkops clkops_omap2_dflt;
Russell Kingb36ee722008-11-04 17:59:52 +000071
Paul Walmsley543d9372008-03-18 10:22:06 +020072extern u8 cpu_mask;
73
74/* clksel_rate data common to 24xx/343x */
75static const struct clksel_rate gpt_32k_rates[] = {
76 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
77 { .div = 0 }
78};
79
80static const struct clksel_rate gpt_sys_rates[] = {
81 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
82 { .div = 0 }
83};
84
85static const struct clksel_rate gfx_l3_rates[] = {
86 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
87 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
88 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
89 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
90 { .div = 0 }
91};
92
93
94#endif