Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/remote_spinlock.h> |
| 19 | |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 20 | #include <mach/scm-io.h> |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 21 | #include <mach/msm_iomap.h> |
| 22 | |
| 23 | #include "clock.h" |
| 24 | #include "clock-pll.h" |
| 25 | #include "smd_private.h" |
| 26 | |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 27 | #ifdef CONFIG_MSM_SECURE_IO |
| 28 | #undef readl_relaxed |
| 29 | #undef writel_relaxed |
| 30 | #define readl_relaxed secure_readl |
| 31 | #define writel_relaxed secure_writel |
| 32 | #endif |
| 33 | |
| 34 | #define PLL_OUTCTRL BIT(0) |
| 35 | #define PLL_BYPASSNL BIT(1) |
| 36 | #define PLL_RESET_N BIT(2) |
| 37 | #define PLL_MODE_MASK BM(3, 0) |
| 38 | |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 39 | #define PLL_EN_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->en_reg)) : \ |
| 40 | ((x)->en_reg)) |
| 41 | #define PLL_STATUS_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->status_reg)) : \ |
| 42 | ((x)->status_reg)) |
| 43 | #define PLL_MODE_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->mode_reg)) : \ |
| 44 | ((x)->mode_reg)) |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 45 | #define PLL_L_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->l_reg)) : \ |
| 46 | ((x)->l_reg)) |
| 47 | #define PLL_M_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->m_reg)) : \ |
| 48 | ((x)->m_reg)) |
| 49 | #define PLL_N_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->n_reg)) : \ |
| 50 | ((x)->n_reg)) |
| 51 | #define PLL_CONFIG_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->config_reg)) : \ |
| 52 | ((x)->config_reg)) |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 53 | |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 54 | static DEFINE_SPINLOCK(pll_reg_lock); |
| 55 | |
Vikram Mulukutla | 7b953b1 | 2012-04-09 13:56:26 -0700 | [diff] [blame] | 56 | #define ENABLE_WAIT_MAX_LOOPS 200 |
| 57 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 58 | int pll_vote_clk_enable(struct clk *c) |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 59 | { |
Vikram Mulukutla | 7b953b1 | 2012-04-09 13:56:26 -0700 | [diff] [blame] | 60 | u32 ena, count; |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 61 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 62 | struct pll_vote_clk *pllv = to_pll_vote_clk(c); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 63 | |
| 64 | spin_lock_irqsave(&pll_reg_lock, flags); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 65 | ena = readl_relaxed(PLL_EN_REG(pllv)); |
| 66 | ena |= pllv->en_mask; |
| 67 | writel_relaxed(ena, PLL_EN_REG(pllv)); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 68 | spin_unlock_irqrestore(&pll_reg_lock, flags); |
| 69 | |
Vikram Mulukutla | 7b953b1 | 2012-04-09 13:56:26 -0700 | [diff] [blame] | 70 | /* |
| 71 | * Use a memory barrier since some PLL status registers are |
| 72 | * not within the same 1K segment as the voting registers. |
| 73 | */ |
| 74 | mb(); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 75 | |
Vikram Mulukutla | 7b953b1 | 2012-04-09 13:56:26 -0700 | [diff] [blame] | 76 | /* Wait for pll to enable. */ |
| 77 | for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 78 | if (readl_relaxed(PLL_STATUS_REG(pllv)) & pllv->status_mask) |
Vikram Mulukutla | 7b953b1 | 2012-04-09 13:56:26 -0700 | [diff] [blame] | 79 | return 0; |
| 80 | udelay(1); |
| 81 | } |
| 82 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 83 | WARN("PLL %s didn't enable after voting for it!\n", c->dbg_name); |
Vikram Mulukutla | 7b953b1 | 2012-04-09 13:56:26 -0700 | [diff] [blame] | 84 | |
| 85 | return -ETIMEDOUT; |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 86 | } |
| 87 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 88 | void pll_vote_clk_disable(struct clk *c) |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 89 | { |
| 90 | u32 ena; |
| 91 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 92 | struct pll_vote_clk *pllv = to_pll_vote_clk(c); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 93 | |
| 94 | spin_lock_irqsave(&pll_reg_lock, flags); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 95 | ena = readl_relaxed(PLL_EN_REG(pllv)); |
| 96 | ena &= ~(pllv->en_mask); |
| 97 | writel_relaxed(ena, PLL_EN_REG(pllv)); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 98 | spin_unlock_irqrestore(&pll_reg_lock, flags); |
| 99 | } |
| 100 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 101 | struct clk *pll_vote_clk_get_parent(struct clk *c) |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 102 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 103 | return to_pll_vote_clk(c)->parent; |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 104 | } |
| 105 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 106 | int pll_vote_clk_is_enabled(struct clk *c) |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 107 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 108 | struct pll_vote_clk *pllv = to_pll_vote_clk(c); |
| 109 | return !!(readl_relaxed(PLL_STATUS_REG(pllv)) & pllv->status_mask); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 110 | } |
| 111 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 112 | static enum handoff pll_vote_clk_handoff(struct clk *c) |
Matt Wagantall | 4a36a7e | 2012-05-14 17:03:21 -0700 | [diff] [blame] | 113 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 114 | struct pll_vote_clk *pllv = to_pll_vote_clk(c); |
| 115 | if (readl_relaxed(PLL_EN_REG(pllv)) & pllv->en_mask) |
Matt Wagantall | 4a36a7e | 2012-05-14 17:03:21 -0700 | [diff] [blame] | 116 | return HANDOFF_ENABLED_CLK; |
| 117 | |
| 118 | return HANDOFF_DISABLED_CLK; |
| 119 | } |
| 120 | |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 121 | struct clk_ops clk_ops_pll_vote = { |
| 122 | .enable = pll_vote_clk_enable, |
| 123 | .disable = pll_vote_clk_disable, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 124 | .is_enabled = pll_vote_clk_is_enabled, |
| 125 | .get_parent = pll_vote_clk_get_parent, |
Matt Wagantall | 4a36a7e | 2012-05-14 17:03:21 -0700 | [diff] [blame] | 126 | .handoff = pll_vote_clk_handoff, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | static void __pll_clk_enable_reg(void __iomem *mode_reg) |
| 130 | { |
| 131 | u32 mode = readl_relaxed(mode_reg); |
| 132 | /* Disable PLL bypass mode. */ |
| 133 | mode |= PLL_BYPASSNL; |
| 134 | writel_relaxed(mode, mode_reg); |
| 135 | |
| 136 | /* |
| 137 | * H/W requires a 5us delay between disabling the bypass and |
| 138 | * de-asserting the reset. Delay 10us just to be safe. |
| 139 | */ |
| 140 | mb(); |
| 141 | udelay(10); |
| 142 | |
| 143 | /* De-assert active-low PLL reset. */ |
| 144 | mode |= PLL_RESET_N; |
| 145 | writel_relaxed(mode, mode_reg); |
| 146 | |
| 147 | /* Wait until PLL is locked. */ |
| 148 | mb(); |
| 149 | udelay(50); |
| 150 | |
| 151 | /* Enable PLL output. */ |
| 152 | mode |= PLL_OUTCTRL; |
| 153 | writel_relaxed(mode, mode_reg); |
| 154 | |
| 155 | /* Ensure that the write above goes through before returning. */ |
| 156 | mb(); |
| 157 | } |
| 158 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 159 | static int local_pll_clk_enable(struct clk *c) |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 160 | { |
| 161 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 162 | struct pll_clk *pll = to_pll_clk(c); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 163 | |
| 164 | spin_lock_irqsave(&pll_reg_lock, flags); |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 165 | __pll_clk_enable_reg(PLL_MODE_REG(pll)); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 166 | spin_unlock_irqrestore(&pll_reg_lock, flags); |
| 167 | |
| 168 | return 0; |
| 169 | } |
| 170 | |
| 171 | static void __pll_clk_disable_reg(void __iomem *mode_reg) |
| 172 | { |
| 173 | u32 mode = readl_relaxed(mode_reg); |
| 174 | mode &= ~PLL_MODE_MASK; |
| 175 | writel_relaxed(mode, mode_reg); |
| 176 | } |
| 177 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 178 | static void local_pll_clk_disable(struct clk *c) |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 179 | { |
| 180 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 181 | struct pll_clk *pll = to_pll_clk(c); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 182 | |
| 183 | /* |
| 184 | * Disable the PLL output, disable test mode, enable |
| 185 | * the bypass mode, and assert the reset. |
| 186 | */ |
| 187 | spin_lock_irqsave(&pll_reg_lock, flags); |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 188 | __pll_clk_disable_reg(PLL_MODE_REG(pll)); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 189 | spin_unlock_irqrestore(&pll_reg_lock, flags); |
| 190 | } |
| 191 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 192 | static enum handoff local_pll_clk_handoff(struct clk *c) |
Matt Wagantall | 4a36a7e | 2012-05-14 17:03:21 -0700 | [diff] [blame] | 193 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 194 | struct pll_clk *pll = to_pll_clk(c); |
Matt Wagantall | 4a36a7e | 2012-05-14 17:03:21 -0700 | [diff] [blame] | 195 | u32 mode = readl_relaxed(PLL_MODE_REG(pll)); |
| 196 | u32 mask = PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL; |
| 197 | |
| 198 | if ((mode & mask) == mask) |
| 199 | return HANDOFF_ENABLED_CLK; |
| 200 | |
| 201 | return HANDOFF_DISABLED_CLK; |
| 202 | } |
| 203 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 204 | static struct clk *local_pll_clk_get_parent(struct clk *c) |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 205 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 206 | return to_pll_clk(c)->parent; |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 207 | } |
| 208 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 209 | int sr_pll_clk_enable(struct clk *c) |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 210 | { |
| 211 | u32 mode; |
| 212 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 213 | struct pll_clk *pll = to_pll_clk(c); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 214 | |
| 215 | spin_lock_irqsave(&pll_reg_lock, flags); |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 216 | mode = readl_relaxed(PLL_MODE_REG(pll)); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 217 | /* De-assert active-low PLL reset. */ |
| 218 | mode |= PLL_RESET_N; |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 219 | writel_relaxed(mode, PLL_MODE_REG(pll)); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 220 | |
| 221 | /* |
| 222 | * H/W requires a 5us delay between disabling the bypass and |
| 223 | * de-asserting the reset. Delay 10us just to be safe. |
| 224 | */ |
| 225 | mb(); |
| 226 | udelay(10); |
| 227 | |
| 228 | /* Disable PLL bypass mode. */ |
| 229 | mode |= PLL_BYPASSNL; |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 230 | writel_relaxed(mode, PLL_MODE_REG(pll)); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 231 | |
| 232 | /* Wait until PLL is locked. */ |
| 233 | mb(); |
| 234 | udelay(60); |
| 235 | |
| 236 | /* Enable PLL output. */ |
| 237 | mode |= PLL_OUTCTRL; |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 238 | writel_relaxed(mode, PLL_MODE_REG(pll)); |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 239 | |
| 240 | /* Ensure that the write above goes through before returning. */ |
| 241 | mb(); |
| 242 | |
| 243 | spin_unlock_irqrestore(&pll_reg_lock, flags); |
| 244 | |
| 245 | return 0; |
| 246 | } |
| 247 | |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 248 | #define PLL_LOCKED_BIT BIT(16) |
| 249 | |
Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame] | 250 | int msm8974_pll_clk_enable(struct clk *c) |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 251 | { |
| 252 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 253 | struct pll_clk *pll = to_pll_clk(c); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 254 | u32 count, mode; |
| 255 | int ret = 0; |
| 256 | |
| 257 | spin_lock_irqsave(&pll_reg_lock, flags); |
| 258 | mode = readl_relaxed(PLL_MODE_REG(pll)); |
| 259 | /* Disable PLL bypass mode. */ |
Matt Wagantall | 10dde28 | 2012-05-14 19:30:11 -0700 | [diff] [blame] | 260 | mode |= PLL_BYPASSNL; |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 261 | writel_relaxed(mode, PLL_MODE_REG(pll)); |
| 262 | |
| 263 | /* |
| 264 | * H/W requires a 5us delay between disabling the bypass and |
| 265 | * de-asserting the reset. Delay 10us just to be safe. |
| 266 | */ |
| 267 | mb(); |
| 268 | udelay(10); |
| 269 | |
| 270 | /* De-assert active-low PLL reset. */ |
Matt Wagantall | 10dde28 | 2012-05-14 19:30:11 -0700 | [diff] [blame] | 271 | mode |= PLL_RESET_N; |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 272 | writel_relaxed(mode, PLL_MODE_REG(pll)); |
| 273 | |
| 274 | /* Wait for pll to enable. */ |
| 275 | for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) { |
| 276 | if (readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT) |
| 277 | break; |
| 278 | udelay(1); |
| 279 | } |
| 280 | |
| 281 | if (!(readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)) { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 282 | WARN("PLL %s didn't lock after enabling it!\n", c->dbg_name); |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 283 | ret = -ETIMEDOUT; |
| 284 | goto out; |
| 285 | } |
| 286 | |
| 287 | /* Enable PLL output. */ |
Matt Wagantall | 10dde28 | 2012-05-14 19:30:11 -0700 | [diff] [blame] | 288 | mode |= PLL_OUTCTRL; |
Vikram Mulukutla | aa3e011 | 2012-04-23 14:40:51 -0700 | [diff] [blame] | 289 | writel_relaxed(mode, PLL_MODE_REG(pll)); |
| 290 | |
| 291 | /* Ensure the write above goes through before returning. */ |
| 292 | mb(); |
| 293 | |
| 294 | out: |
| 295 | spin_unlock_irqrestore(&pll_reg_lock, flags); |
| 296 | return ret; |
| 297 | } |
| 298 | |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 299 | struct clk_ops clk_ops_local_pll = { |
| 300 | .enable = local_pll_clk_enable, |
| 301 | .disable = local_pll_clk_disable, |
Matt Wagantall | 4a36a7e | 2012-05-14 17:03:21 -0700 | [diff] [blame] | 302 | .handoff = local_pll_clk_handoff, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 303 | .get_parent = local_pll_clk_get_parent, |
| 304 | }; |
| 305 | |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 306 | struct pll_rate { |
| 307 | unsigned int lvalue; |
| 308 | unsigned long rate; |
| 309 | }; |
| 310 | |
| 311 | static struct pll_rate pll_l_rate[] = { |
| 312 | {10, 196000000}, |
| 313 | {12, 245760000}, |
| 314 | {30, 589820000}, |
| 315 | {38, 737280000}, |
| 316 | {41, 800000000}, |
| 317 | {50, 960000000}, |
| 318 | {52, 1008000000}, |
Trilok Soni | 4863172 | 2012-05-17 20:56:42 +0530 | [diff] [blame] | 319 | {60, 1152000000}, |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 320 | {62, 1200000000}, |
Pankaj Kumar | 50c705c | 2012-01-10 12:02:07 +0530 | [diff] [blame] | 321 | {63, 1209600000}, |
Kaushal Kumar | 86473f0 | 2012-06-28 19:35:58 +0530 | [diff] [blame] | 322 | {73, 1401600000}, |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 323 | {0, 0}, |
| 324 | }; |
| 325 | |
| 326 | #define PLL_BASE 7 |
| 327 | |
| 328 | struct shared_pll_control { |
| 329 | uint32_t version; |
| 330 | struct { |
| 331 | /* |
| 332 | * Denotes if the PLL is ON. Technically, this can be read |
| 333 | * directly from the PLL registers, but this feild is here, |
| 334 | * so let's use it. |
| 335 | */ |
| 336 | uint32_t on; |
| 337 | /* |
| 338 | * One bit for each processor core. The application processor |
| 339 | * is allocated bit position 1. All other bits should be |
| 340 | * considered as votes from other processors. |
| 341 | */ |
| 342 | uint32_t votes; |
| 343 | } pll[PLL_BASE + PLL_END]; |
| 344 | }; |
| 345 | |
| 346 | static remote_spinlock_t pll_lock; |
| 347 | static struct shared_pll_control *pll_control; |
| 348 | |
| 349 | void __init msm_shared_pll_control_init(void) |
| 350 | { |
| 351 | #define PLL_REMOTE_SPINLOCK_ID "S:7" |
| 352 | unsigned smem_size; |
| 353 | |
| 354 | remote_spin_lock_init(&pll_lock, PLL_REMOTE_SPINLOCK_ID); |
| 355 | |
| 356 | pll_control = smem_get_entry(SMEM_CLKREGIM_SOURCES, &smem_size); |
| 357 | if (!pll_control) { |
| 358 | pr_err("Can't find shared PLL control data structure!\n"); |
| 359 | BUG(); |
| 360 | /* |
| 361 | * There might be more PLLs than what the application processor knows |
| 362 | * about. But the index used for each PLL is guaranteed to remain the |
| 363 | * same. |
| 364 | */ |
| 365 | } else if (smem_size < sizeof(struct shared_pll_control)) { |
| 366 | pr_err("Shared PLL control data" |
| 367 | "structure too small!\n"); |
| 368 | BUG(); |
| 369 | } else if (pll_control->version != 0xCCEE0001) { |
| 370 | pr_err("Shared PLL control version mismatch!\n"); |
| 371 | BUG(); |
| 372 | } else { |
| 373 | pr_info("Shared PLL control available.\n"); |
| 374 | return; |
| 375 | } |
| 376 | |
| 377 | } |
| 378 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 379 | static int pll_clk_enable(struct clk *c) |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 380 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 381 | struct pll_shared_clk *pll = to_pll_shared_clk(c); |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 382 | unsigned int pll_id = pll->id; |
| 383 | |
| 384 | remote_spin_lock(&pll_lock); |
| 385 | |
| 386 | pll_control->pll[PLL_BASE + pll_id].votes |= BIT(1); |
| 387 | if (!pll_control->pll[PLL_BASE + pll_id].on) { |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 388 | __pll_clk_enable_reg(PLL_MODE_REG(pll)); |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 389 | pll_control->pll[PLL_BASE + pll_id].on = 1; |
| 390 | } |
| 391 | |
| 392 | remote_spin_unlock(&pll_lock); |
| 393 | return 0; |
| 394 | } |
| 395 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 396 | static void pll_clk_disable(struct clk *c) |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 397 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 398 | struct pll_shared_clk *pll = to_pll_shared_clk(c); |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 399 | unsigned int pll_id = pll->id; |
| 400 | |
| 401 | remote_spin_lock(&pll_lock); |
| 402 | |
| 403 | pll_control->pll[PLL_BASE + pll_id].votes &= ~BIT(1); |
| 404 | if (pll_control->pll[PLL_BASE + pll_id].on |
| 405 | && !pll_control->pll[PLL_BASE + pll_id].votes) { |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 406 | __pll_clk_disable_reg(PLL_MODE_REG(pll)); |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 407 | pll_control->pll[PLL_BASE + pll_id].on = 0; |
| 408 | } |
| 409 | |
| 410 | remote_spin_unlock(&pll_lock); |
| 411 | } |
| 412 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 413 | static int pll_clk_is_enabled(struct clk *c) |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 414 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 415 | return readl_relaxed(PLL_MODE_REG(to_pll_shared_clk(c))) & BIT(0); |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 416 | } |
| 417 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 418 | static enum handoff pll_clk_handoff(struct clk *c) |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 419 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 420 | struct pll_shared_clk *pll = to_pll_shared_clk(c); |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 421 | unsigned int pll_lval; |
| 422 | struct pll_rate *l; |
| 423 | |
| 424 | /* |
| 425 | * Wait for the PLLs to be initialized and then read their frequency. |
| 426 | */ |
| 427 | do { |
Vikram Mulukutla | 4d6caa8 | 2012-04-10 18:04:55 -0700 | [diff] [blame] | 428 | pll_lval = readl_relaxed(PLL_MODE_REG(pll) + 4) & 0x3ff; |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 429 | cpu_relax(); |
| 430 | udelay(50); |
| 431 | } while (pll_lval == 0); |
| 432 | |
| 433 | /* Convert PLL L values to PLL Output rate */ |
| 434 | for (l = pll_l_rate; l->rate != 0; l++) { |
| 435 | if (l->lvalue == pll_lval) { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 436 | c->rate = l->rate; |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 437 | break; |
| 438 | } |
| 439 | } |
| 440 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 441 | if (!c->rate) { |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 442 | pr_crit("Unknown PLL's L value!\n"); |
| 443 | BUG(); |
| 444 | } |
| 445 | |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 446 | return HANDOFF_ENABLED_CLK; |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 447 | } |
| 448 | |
Matt Wagantall | ae05322 | 2012-05-14 19:42:07 -0700 | [diff] [blame] | 449 | struct clk_ops clk_ops_pll = { |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 450 | .enable = pll_clk_enable, |
| 451 | .disable = pll_clk_disable, |
| 452 | .handoff = pll_clk_handoff, |
Pankaj Kumar | 3912c98 | 2011-12-07 16:59:03 +0530 | [diff] [blame] | 453 | .is_enabled = pll_clk_is_enabled, |
| 454 | }; |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 455 | |
| 456 | static void __init __set_fsm_mode(void __iomem *mode_reg) |
| 457 | { |
| 458 | u32 regval = readl_relaxed(mode_reg); |
| 459 | |
| 460 | /* De-assert reset to FSM */ |
| 461 | regval &= ~BIT(21); |
| 462 | writel_relaxed(regval, mode_reg); |
| 463 | |
| 464 | /* Program bias count */ |
| 465 | regval &= ~BM(19, 14); |
| 466 | regval |= BVAL(19, 14, 0x1); |
| 467 | writel_relaxed(regval, mode_reg); |
| 468 | |
| 469 | /* Program lock count */ |
| 470 | regval &= ~BM(13, 8); |
| 471 | regval |= BVAL(13, 8, 0x8); |
| 472 | writel_relaxed(regval, mode_reg); |
| 473 | |
| 474 | /* Enable PLL FSM voting */ |
| 475 | regval |= BIT(20); |
| 476 | writel_relaxed(regval, mode_reg); |
| 477 | } |
| 478 | |
| 479 | void __init configure_pll(struct pll_config *config, |
| 480 | struct pll_config_regs *regs, u32 ena_fsm_mode) |
| 481 | { |
| 482 | u32 regval; |
| 483 | |
| 484 | writel_relaxed(config->l, PLL_L_REG(regs)); |
| 485 | writel_relaxed(config->m, PLL_M_REG(regs)); |
| 486 | writel_relaxed(config->n, PLL_N_REG(regs)); |
| 487 | |
| 488 | regval = readl_relaxed(PLL_CONFIG_REG(regs)); |
| 489 | |
| 490 | /* Enable the MN accumulator */ |
| 491 | if (config->mn_ena_mask) { |
| 492 | regval &= ~config->mn_ena_mask; |
| 493 | regval |= config->mn_ena_val; |
| 494 | } |
| 495 | |
| 496 | /* Enable the main output */ |
| 497 | if (config->main_output_mask) { |
| 498 | regval &= ~config->main_output_mask; |
| 499 | regval |= config->main_output_val; |
| 500 | } |
| 501 | |
| 502 | /* Set pre-divider and post-divider values */ |
| 503 | regval &= ~config->pre_div_mask; |
| 504 | regval |= config->pre_div_val; |
| 505 | regval &= ~config->post_div_mask; |
| 506 | regval |= config->post_div_val; |
| 507 | |
| 508 | /* Select VCO setting */ |
| 509 | regval &= ~config->vco_mask; |
| 510 | regval |= config->vco_val; |
| 511 | writel_relaxed(regval, PLL_CONFIG_REG(regs)); |
| 512 | |
| 513 | /* Configure in FSM mode if necessary */ |
| 514 | if (ena_fsm_mode) |
| 515 | __set_fsm_mode(PLL_MODE_REG(regs)); |
| 516 | } |