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gerrit-public.fairphone.software / kernel / msm / c315b7e840a1f336ffefb21d3130f9799af2ecd6 / . / drivers / net / ibmlana.h
blob: 458ee226e5372d8250f20f733f483543e4eef259 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1#ifndef _IBM_LANA_INCLUDE_
2#define _IBM_LANA_INCLUDE_
3
4#ifdef _IBM_LANA_DRIVER_
5
6/* maximum packet size */
7
8#define PKTSIZE 1524
9
10/* number of transmit buffers */
11
12#define TXBUFCNT 4
13
14/* Adapter ID's */
15#define IBM_LANA_ID 0xffe0
16
17/* media enumeration - defined in a way that it fits onto the LAN/A's
18 POS registers... */
19
20typedef enum {
21 Media_10BaseT, Media_10Base5,
22 Media_Unknown, Media_10Base2, Media_Count
23} ibmlana_medium;
24
25/* private structure */
26
27typedef struct {
28 unsigned int slot; /* MCA-Slot-# */
29 struct net_device_stats stat; /* packet statistics */
30 int realirq; /* memorizes actual IRQ, even when
31 currently not allocated */
32 ibmlana_medium medium; /* physical cannector */
33 u32 tdastart, txbufstart, /* addresses */
34 rrastart, rxbufstart, rdastart, rxbufcnt, txusedcnt;
35 int nextrxdescr, /* next rx descriptor to be used */
36 lastrxdescr, /* last free rx descriptor */
37 nexttxdescr, /* last tx descriptor to be used */
38 currtxdescr, /* tx descriptor currently tx'ed */
39 txused[TXBUFCNT]; /* busy flags */
40 void __iomem *base;
41 spinlock_t lock;
42} ibmlana_priv;
43
44/* this card uses quite a lot of I/O ports...luckily the MCA bus decodes
45 a full 64K I/O range... */
46
47#define IBM_LANA_IORANGE 0xa0
48
49/* Command Register: */
50
51#define SONIC_CMDREG 0x00
52#define CMDREG_HTX 0x0001 /* halt transmission */
53#define CMDREG_TXP 0x0002 /* start transmission */
54#define CMDREG_RXDIS 0x0004 /* disable receiver */
55#define CMDREG_RXEN 0x0008 /* enable receiver */
56#define CMDREG_STP 0x0010 /* stop timer */
57#define CMDREG_ST 0x0020 /* start timer */
58#define CMDREG_RST 0x0080 /* software reset */
59#define CMDREG_RRRA 0x0100 /* force SONIC to read first RRA */
60#define CMDREG_LCAM 0x0200 /* force SONIC to read CAM descrs */
61
62/* Data Configuration Register */
63
64#define SONIC_DCREG 0x02
65#define DCREG_EXBUS 0x8000 /* Extended Bus Mode */
66#define DCREG_LBR 0x2000 /* Latched Bus Retry */
67#define DCREG_PO1 0x1000 /* Programmable Outputs */
68#define DCREG_PO0 0x0800
69#define DCREG_SBUS 0x0400 /* Synchronous Bus Mode */
70#define DCREG_USR1 0x0200 /* User Definable Pins */
71#define DCREG_USR0 0x0100
72#define DCREG_WC0 0x0000 /* 0..3 Wait States */
73#define DCREG_WC1 0x0040
74#define DCREG_WC2 0x0080
75#define DCREG_WC3 0x00c0
76#define DCREG_DW16 0x0000 /* 16 bit Bus Mode */
77#define DCREG_DW32 0x0020 /* 32 bit Bus Mode */
78#define DCREG_BMS 0x0010 /* Block Mode Select */
79#define DCREG_RFT4 0x0000 /* 4/8/16/24 bytes RX Threshold */
80#define DCREG_RFT8 0x0004
81#define DCREG_RFT16 0x0008
82#define DCREG_RFT24 0x000c
83#define DCREG_TFT8 0x0000 /* 8/16/24/28 bytes TX Threshold */
84#define DCREG_TFT16 0x0001
85#define DCREG_TFT24 0x0002
86#define DCREG_TFT28 0x0003
87
88/* Receive Control Register */
89
90#define SONIC_RCREG 0x04
91#define RCREG_ERR 0x8000 /* accept damaged and collided pkts */
92#define RCREG_RNT 0x4000 /* accept packets that are < 64 */
93#define RCREG_BRD 0x2000 /* accept broadcasts */
94#define RCREG_PRO 0x1000 /* promiscous mode */
95#define RCREG_AMC 0x0800 /* accept all multicasts */
96#define RCREG_LB_NONE 0x0000 /* no loopback */
97#define RCREG_LB_MAC 0x0200 /* MAC loopback */
98#define RCREG_LB_ENDEC 0x0400 /* ENDEC loopback */
99#define RCREG_LB_XVR 0x0600 /* Transceiver loopback */
100#define RCREG_MC 0x0100 /* Multicast received */
101#define RCREG_BC 0x0080 /* Broadcast received */
102#define RCREG_LPKT 0x0040 /* last packet in RBA */
103#define RCREG_CRS 0x0020 /* carrier sense present */
104#define RCREG_COL 0x0010 /* recv'd packet with collision */
105#define RCREG_CRCR 0x0008 /* recv'd packet with CRC error */
106#define RCREG_FAER 0x0004 /* recv'd packet with inv. framing */
107#define RCREG_LBK 0x0002 /* recv'd loopback packet */
108#define RCREG_PRX 0x0001 /* recv'd packet is OK */
109
110/* Transmit Control Register */
111
112#define SONIC_TCREG 0x06
113#define TCREG_PINT 0x8000 /* generate interrupt after TDA read */
114#define TCREG_POWC 0x4000 /* timer start out of window detect */
115#define TCREG_CRCI 0x2000 /* inhibit CRC generation */
116#define TCREG_EXDIS 0x1000 /* disable excessive deferral timer */
117#define TCREG_EXD 0x0400 /* excessive deferral occurred */
118#define TCREG_DEF 0x0200 /* single deferral occurred */
119#define TCREG_NCRS 0x0100 /* no carrier detected */
120#define TCREG_CRSL 0x0080 /* carrier lost */
121#define TCREG_EXC 0x0040 /* excessive collisions occurred */
122#define TCREG_OWC 0x0020 /* out of window collision occurred */
123#define TCREG_PMB 0x0008 /* packet monitored bad */
124#define TCREG_FU 0x0004 /* FIFO underrun */
125#define TCREG_BCM 0x0002 /* byte count mismatch of fragments */
126#define TCREG_PTX 0x0001 /* packet transmitted OK */
127
128/* Interrupt Mask Register */
129
130#define SONIC_IMREG 0x08
131#define IMREG_BREN 0x4000 /* interrupt when bus retry occurred */
132#define IMREG_HBLEN 0x2000 /* interrupt when heartbeat lost */
133#define IMREG_LCDEN 0x1000 /* interrupt when CAM loaded */
134#define IMREG_PINTEN 0x0800 /* interrupt when PINT in TDA set */
135#define IMREG_PRXEN 0x0400 /* interrupt when packet received */
136#define IMREG_PTXEN 0x0200 /* interrupt when packet was sent */
137#define IMREG_TXEREN 0x0100 /* interrupt when send failed */
138#define IMREG_TCEN 0x0080 /* interrupt when timer completed */
139#define IMREG_RDEEN 0x0040 /* interrupt when RDA exhausted */
140#define IMREG_RBEEN 0x0020 /* interrupt when RBA exhausted */
141#define IMREG_RBAEEN 0x0010 /* interrupt when RBA too short */
142#define IMREG_CRCEN 0x0008 /* interrupt when CRC counter rolls */
143#define IMREG_FAEEN 0x0004 /* interrupt when FAE counter rolls */
144#define IMREG_MPEN 0x0002 /* interrupt when MP counter rolls */
145#define IMREG_RFOEN 0x0001 /* interrupt when Rx FIFO overflows */
146
147/* Interrupt Status Register */
148
149#define SONIC_ISREG 0x0a
150#define ISREG_BR 0x4000 /* bus retry occurred */
151#define ISREG_HBL 0x2000 /* heartbeat lost */
152#define ISREG_LCD 0x1000 /* CAM loaded */
153#define ISREG_PINT 0x0800 /* PINT in TDA set */
154#define ISREG_PKTRX 0x0400 /* packet received */
155#define ISREG_TXDN 0x0200 /* packet was sent */
156#define ISREG_TXER 0x0100 /* send failed */
157#define ISREG_TC 0x0080 /* timer completed */
158#define ISREG_RDE 0x0040 /* RDA exhausted */
159#define ISREG_RBE 0x0020 /* RBA exhausted */
160#define ISREG_RBAE 0x0010 /* RBA too short for received frame */
161#define ISREG_CRC 0x0008 /* CRC counter rolls over */
162#define ISREG_FAE 0x0004 /* FAE counter rolls over */
163#define ISREG_MP 0x0002 /* MP counter rolls over */
164#define ISREG_RFO 0x0001 /* Rx FIFO overflows */
165
166#define SONIC_UTDA 0x0c /* current transmit descr address */
167#define SONIC_CTDA 0x0e
168
169#define SONIC_URDA 0x1a /* current receive descr address */
170#define SONIC_CRDA 0x1c
171
172#define SONIC_CRBA0 0x1e /* current receive buffer address */
173#define SONIC_CRBA1 0x20
174
175#define SONIC_RBWC0 0x22 /* word count in receive buffer */
176#define SONIC_RBWC1 0x24
177
178#define SONIC_EOBC 0x26 /* minimum space to be free in RBA */
179
180#define SONIC_URRA 0x28 /* upper address of CDA & Recv Area */
181
182#define SONIC_RSA 0x2a /* start of receive resource area */
183
184#define SONIC_REA 0x2c /* end of receive resource area */
185
186#define SONIC_RRP 0x2e /* resource read pointer */
187
188#define SONIC_RWP 0x30 /* resource write pointer */
189
190#define SONIC_CAMEPTR 0x42 /* CAM entry pointer */
191
192#define SONIC_CAMADDR2 0x44 /* CAM address ports */
193#define SONIC_CAMADDR1 0x46
194#define SONIC_CAMADDR0 0x48
195
196#define SONIC_CAMPTR 0x4c /* lower address of CDA */
197
198#define SONIC_CAMCNT 0x4e /* # of CAM descriptors to load */
199
200/* Data Configuration Register 2 */
201
202#define SONIC_DCREG2 0x7e
203#define DCREG2_EXPO3 0x8000 /* extended programmable outputs */
204#define DCREG2_EXPO2 0x4000
205#define DCREG2_EXPO1 0x2000
206#define DCREG2_EXPO0 0x1000
207#define DCREG2_HD 0x0800 /* heartbeat disable */
208#define DCREG2_JD 0x0200 /* jabber timer disable */
209#define DCREG2_AUTO 0x0100 /* enable AUI/TP auto selection */
210#define DCREG2_XWRAP 0x0040 /* TP transceiver loopback */
211#define DCREG2_PH 0x0010 /* HOLD request timing */
212#define DCREG2_PCM 0x0004 /* packet compress when matched */
213#define DCREG2_PCNM 0x0002 /* packet compress when not matched */
214#define DCREG2_RJCM 0x0001 /* inverse packet match via CAM */
215
216/* Board Control Register: Enable RAM, Interrupts... */
217
218#define BCMREG 0x80
219#define BCMREG_RAMEN 0x80 /* switch over to RAM */
220#define BCMREG_IPEND 0x40 /* interrupt pending ? */
221#define BCMREG_RESET 0x08 /* reset board */
222#define BCMREG_16BIT 0x04 /* adapter in 16-bit slot */
223#define BCMREG_RAMWIN 0x02 /* enable RAM window */
224#define BCMREG_IEN 0x01 /* interrupt enable */
225
226/* MAC Address PROM */
227
228#define MACADDRPROM 0x92
229
230/* structure of a CAM entry */
231
232typedef struct {
233 u32 index; /* pointer into CAM area */
234 u32 addr0; /* address part (bits 0..15 used) */
235 u32 addr1;
236 u32 addr2;
237} camentry_t;
238
239/* structure of a receive resource */
240
241typedef struct {
242 u32 startlo; /* start address (bits 0..15 used) */
243 u32 starthi;
244 u32 cntlo; /* size in 16-bit quantities */
245 u32 cnthi;
246} rra_t;
247
248/* structure of a receive descriptor */
249
250typedef struct {
251 u32 status; /* packet status */
252 u32 length; /* length in bytes */
253 u32 startlo; /* start address */
254 u32 starthi;
255 u32 seqno; /* frame sequence */
256 u32 link; /* pointer to next descriptor */
257 /* bit 0 = EOL */
258 u32 inuse; /* !=0 --> free for SONIC to write */
259} rda_t;
260
261/* structure of a transmit descriptor */
262
263typedef struct {
264 u32 status; /* transmit status */
265 u32 config; /* value for TCR */
266 u32 length; /* total length */
267 u32 fragcount; /* number of fragments */
268 u32 startlo; /* start address of fragment */
269 u32 starthi;
270 u32 fraglength; /* length of this fragment */
271 /* more address/length triplets may */
272 /* follow here */
273 u32 link; /* pointer to next descriptor */
274 /* bit 0 = EOL */
275} tda_t;
276
277#endif /* _IBM_LANA_DRIVER_ */
278
279#endif /* _IBM_LANA_INCLUDE_ */