blob: 89f1811777dc60b1d3d59b8fc3a3b5982a68f6ff [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/platform_device.h>
17#include <linux/msm_rotator.h>
18#include <linux/clkdev.h>
19#include <mach/irqs-8064.h>
20#include <mach/board.h>
21#include <mach/msm_iomap.h>
22#include "clock.h"
23#include "devices.h"
24
25/* Address of GSBI blocks */
26#define MSM_GSBI3_PHYS 0x16200000
Harini Jayaramanc4c58692011-07-19 14:50:10 -060027#define MSM_GSBI4_PHYS 0x16300000
28#define MSM_GSBI5_PHYS 0x1A200000
29#define MSM_GSBI6_PHYS 0x16500000
30#define MSM_GSBI7_PHYS 0x16600000
31
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070032#define MSM_UART3DM_PHYS (MSM_GSBI3_PHYS + 0x40000)
33
Harini Jayaramanc4c58692011-07-19 14:50:10 -060034/* GSBI QUP devices */
35#define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000)
36#define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000)
37#define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000)
38#define MSM_GSBI6_QUP_PHYS (MSM_GSBI6_PHYS + 0x80000)
39#define MSM_GSBI7_QUP_PHYS (MSM_GSBI7_PHYS + 0x80000)
40#define MSM_QUP_SIZE SZ_4K
41
42
Joel King0581896d2011-07-19 16:43:28 -070043static struct resource msm_dmov_resource[] = {
44 {
45 .start = ADM_0_SCSS_0_IRQ,
46 .end = (resource_size_t)MSM_DMOV_BASE,
47 .flags = IORESOURCE_IRQ,
48 },
49};
50
51struct platform_device msm_device_dmov = {
52 .name = "msm_dmov",
53 .id = -1,
54 .resource = msm_dmov_resource,
55 .num_resources = ARRAY_SIZE(msm_dmov_resource),
56};
57
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070058static struct resource resources_uart_gsbi3[] = {
59 {
60 .start = GSBI3_UARTDM_IRQ,
61 .end = GSBI3_UARTDM_IRQ,
62 .flags = IORESOURCE_IRQ,
63 },
64 {
65 .start = MSM_UART3DM_PHYS,
66 .end = MSM_UART3DM_PHYS + PAGE_SIZE - 1,
67 .name = "uartdm_resource",
68 .flags = IORESOURCE_MEM,
69 },
70 {
71 .start = MSM_GSBI3_PHYS,
72 .end = MSM_GSBI3_PHYS + PAGE_SIZE - 1,
73 .name = "gsbi_resource",
74 .flags = IORESOURCE_MEM,
75 },
76};
77
78struct platform_device apq8064_device_uart_gsbi3 = {
79 .name = "msm_serial_hsl",
80 .id = 0,
81 .num_resources = ARRAY_SIZE(resources_uart_gsbi3),
82 .resource = resources_uart_gsbi3,
83};
84
85static struct resource resources_qup_spi_gsbi5[] = {
86 {
87 .name = "spi_base",
88 .start = MSM_GSBI5_QUP_PHYS,
89 .end = MSM_GSBI5_QUP_PHYS + SZ_4K - 1,
90 .flags = IORESOURCE_MEM,
91 },
92 {
93 .name = "gsbi_base",
94 .start = MSM_GSBI5_PHYS,
95 .end = MSM_GSBI5_PHYS + 4 - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 {
99 .name = "spi_irq_in",
100 .start = GSBI5_QUP_IRQ,
101 .end = GSBI5_QUP_IRQ,
102 .flags = IORESOURCE_IRQ,
103 },
104};
105
106struct platform_device apq8064_device_qup_spi_gsbi5 = {
107 .name = "spi_qsd",
108 .id = 0,
109 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi5),
110 .resource = resources_qup_spi_gsbi5,
111};
112
113static struct resource resources_ssbi_pmic1[] = {
114 {
115 .start = MSM_PMIC1_SSBI_CMD_PHYS,
116 .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
117 .flags = IORESOURCE_MEM,
118 },
119};
120
121struct platform_device apq8064_device_ssbi_pmic1 = {
122 .name = "msm_ssbi",
123 .id = 0,
124 .resource = resources_ssbi_pmic1,
125 .num_resources = ARRAY_SIZE(resources_ssbi_pmic1),
126};
127
128static struct resource resources_ssbi_pmic2[] = {
129 {
130 .start = MSM_PMIC2_SSBI_CMD_PHYS,
131 .end = MSM_PMIC2_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
132 .flags = IORESOURCE_MEM,
133 },
134};
135
136struct platform_device apq8064_device_ssbi_pmic2 = {
137 .name = "msm_ssbi",
138 .id = 1,
139 .resource = resources_ssbi_pmic2,
140 .num_resources = ARRAY_SIZE(resources_ssbi_pmic2),
141};
142
143static struct resource resources_otg[] = {
144 {
145 .start = MSM_HSUSB_PHYS,
146 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 {
150 .start = USB1_HS_IRQ,
151 .end = USB1_HS_IRQ,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156struct platform_device msm_device_otg = {
157 .name = "msm_otg",
158 .id = -1,
159 .num_resources = ARRAY_SIZE(resources_otg),
160 .resource = resources_otg,
161 .dev = {
162 .coherent_dma_mask = 0xffffffff,
163 },
164};
165
166static struct resource resources_hsusb[] = {
167 {
168 .start = MSM_HSUSB_PHYS,
169 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE - 1,
170 .flags = IORESOURCE_MEM,
171 },
172 {
173 .start = USB1_HS_IRQ,
174 .end = USB1_HS_IRQ,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179struct platform_device msm_device_gadget_peripheral = {
180 .name = "msm_hsusb",
181 .id = -1,
182 .num_resources = ARRAY_SIZE(resources_hsusb),
183 .resource = resources_hsusb,
184 .dev = {
185 .coherent_dma_mask = 0xffffffff,
186 },
187};
188
189#define MSM_SDC1_BASE 0x12400000
190#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
191#define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000)
192#define MSM_SDC2_BASE 0x12140000
193#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
194#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
195#define MSM_SDC3_BASE 0x12180000
196#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
197#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
198#define MSM_SDC4_BASE 0x121C0000
199#define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800)
200#define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000)
201
202static struct resource resources_sdc1[] = {
203 {
204 .name = "core_mem",
205 .flags = IORESOURCE_MEM,
206 .start = MSM_SDC1_BASE,
207 .end = MSM_SDC1_DML_BASE - 1,
208 },
209 {
210 .name = "core_irq",
211 .flags = IORESOURCE_IRQ,
212 .start = SDC1_IRQ_0,
213 .end = SDC1_IRQ_0
214 },
215#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
216 {
217 .name = "sdcc_dml_addr",
218 .start = MSM_SDC1_DML_BASE,
219 .end = MSM_SDC1_BAM_BASE - 1,
220 .flags = IORESOURCE_MEM,
221 },
222 {
223 .name = "sdcc_bam_addr",
224 .start = MSM_SDC1_BAM_BASE,
225 .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1,
226 .flags = IORESOURCE_MEM,
227 },
228 {
229 .name = "sdcc_bam_irq",
230 .start = SDC1_BAM_IRQ,
231 .end = SDC1_BAM_IRQ,
232 .flags = IORESOURCE_IRQ,
233 },
234#endif
235};
236
237static struct resource resources_sdc2[] = {
238 {
239 .name = "core_mem",
240 .flags = IORESOURCE_MEM,
241 .start = MSM_SDC2_BASE,
242 .end = MSM_SDC2_DML_BASE - 1,
243 },
244 {
245 .name = "core_irq",
246 .flags = IORESOURCE_IRQ,
247 .start = SDC2_IRQ_0,
248 .end = SDC2_IRQ_0
249 },
250#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
251 {
252 .name = "sdcc_dml_addr",
253 .start = MSM_SDC2_DML_BASE,
254 .end = MSM_SDC2_BAM_BASE - 1,
255 .flags = IORESOURCE_MEM,
256 },
257 {
258 .name = "sdcc_bam_addr",
259 .start = MSM_SDC2_BAM_BASE,
260 .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1,
261 .flags = IORESOURCE_MEM,
262 },
263 {
264 .name = "sdcc_bam_irq",
265 .start = SDC2_BAM_IRQ,
266 .end = SDC2_BAM_IRQ,
267 .flags = IORESOURCE_IRQ,
268 },
269#endif
270};
271
272static struct resource resources_sdc3[] = {
273 {
274 .name = "core_mem",
275 .flags = IORESOURCE_MEM,
276 .start = MSM_SDC3_BASE,
277 .end = MSM_SDC3_DML_BASE - 1,
278 },
279 {
280 .name = "core_irq",
281 .flags = IORESOURCE_IRQ,
282 .start = SDC3_IRQ_0,
283 .end = SDC3_IRQ_0
284 },
285#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
286 {
287 .name = "sdcc_dml_addr",
288 .start = MSM_SDC3_DML_BASE,
289 .end = MSM_SDC3_BAM_BASE - 1,
290 .flags = IORESOURCE_MEM,
291 },
292 {
293 .name = "sdcc_bam_addr",
294 .start = MSM_SDC3_BAM_BASE,
295 .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .name = "sdcc_bam_irq",
300 .start = SDC3_BAM_IRQ,
301 .end = SDC3_BAM_IRQ,
302 .flags = IORESOURCE_IRQ,
303 },
304#endif
305};
306
307static struct resource resources_sdc4[] = {
308 {
309 .name = "core_mem",
310 .flags = IORESOURCE_MEM,
311 .start = MSM_SDC4_BASE,
312 .end = MSM_SDC4_DML_BASE - 1,
313 },
314 {
315 .name = "core_irq",
316 .flags = IORESOURCE_IRQ,
317 .start = SDC4_IRQ_0,
318 .end = SDC4_IRQ_0
319 },
320#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
321 {
322 .name = "sdcc_dml_addr",
323 .start = MSM_SDC4_DML_BASE,
324 .end = MSM_SDC4_BAM_BASE - 1,
325 .flags = IORESOURCE_MEM,
326 },
327 {
328 .name = "sdcc_bam_addr",
329 .start = MSM_SDC4_BAM_BASE,
330 .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1,
331 .flags = IORESOURCE_MEM,
332 },
333 {
334 .name = "sdcc_bam_irq",
335 .start = SDC4_BAM_IRQ,
336 .end = SDC4_BAM_IRQ,
337 .flags = IORESOURCE_IRQ,
338 },
339#endif
340};
341
342struct platform_device apq8064_device_sdc1 = {
343 .name = "msm_sdcc",
344 .id = 1,
345 .num_resources = ARRAY_SIZE(resources_sdc1),
346 .resource = resources_sdc1,
347 .dev = {
348 .coherent_dma_mask = 0xffffffff,
349 },
350};
351
352struct platform_device apq8064_device_sdc2 = {
353 .name = "msm_sdcc",
354 .id = 2,
355 .num_resources = ARRAY_SIZE(resources_sdc2),
356 .resource = resources_sdc2,
357 .dev = {
358 .coherent_dma_mask = 0xffffffff,
359 },
360};
361
362struct platform_device apq8064_device_sdc3 = {
363 .name = "msm_sdcc",
364 .id = 3,
365 .num_resources = ARRAY_SIZE(resources_sdc3),
366 .resource = resources_sdc3,
367 .dev = {
368 .coherent_dma_mask = 0xffffffff,
369 },
370};
371
372struct platform_device apq8064_device_sdc4 = {
373 .name = "msm_sdcc",
374 .id = 4,
375 .num_resources = ARRAY_SIZE(resources_sdc4),
376 .resource = resources_sdc4,
377 .dev = {
378 .coherent_dma_mask = 0xffffffff,
379 },
380};
381
382static struct platform_device *apq8064_sdcc_devices[] __initdata = {
383 &apq8064_device_sdc1,
384 &apq8064_device_sdc2,
385 &apq8064_device_sdc3,
386 &apq8064_device_sdc4,
387};
388
389int __init apq8064_add_sdcc(unsigned int controller,
390 struct mmc_platform_data *plat)
391{
392 struct platform_device *pdev;
393
394 if (!plat)
395 return 0;
396 if (controller < 1 || controller > 4)
397 return -EINVAL;
398
399 pdev = apq8064_sdcc_devices[controller-1];
400 pdev->dev.platform_data = plat;
401 return platform_device_register(pdev);
402}
403
404static struct clk_lookup msm_clocks_8064_dummy[] = {
405 CLK_DUMMY("pll2", PLL2, NULL, 0),
406 CLK_DUMMY("pll8", PLL8, NULL, 0),
407 CLK_DUMMY("pll4", PLL4, NULL, 0),
408
409 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
410 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
411 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
412 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
413 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
414 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
415 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
416 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
417 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
418 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
419 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
420 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
421 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
422 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
423 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
424 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
425
426 CLK_DUMMY("gsbi_uart_clk", GSBI1_UART_CLK, NULL, OFF),
427 CLK_DUMMY("gsbi_uart_clk", GSBI2_UART_CLK, NULL, OFF),
428 CLK_DUMMY("gsbi_uart_clk", GSBI3_UART_CLK,
429 "msm_serial_hsl.0", OFF),
430 CLK_DUMMY("gsbi_uart_clk", GSBI4_UART_CLK, NULL, OFF),
431 CLK_DUMMY("gsbi_uart_clk", GSBI5_UART_CLK, NULL, OFF),
432 CLK_DUMMY("uartdm_clk", GSBI6_UART_CLK, NULL, OFF),
433 CLK_DUMMY("gsbi_uart_clk", GSBI7_UART_CLK, NULL, OFF),
434 CLK_DUMMY("gsbi_uart_clk", GSBI8_UART_CLK, NULL, OFF),
435 CLK_DUMMY("gsbi_uart_clk", GSBI9_UART_CLK, NULL, OFF),
436 CLK_DUMMY("gsbi_uart_clk", GSBI10_UART_CLK, NULL, OFF),
437 CLK_DUMMY("gsbi_uart_clk", GSBI11_UART_CLK, NULL, OFF),
438 CLK_DUMMY("gsbi_uart_clk", GSBI12_UART_CLK, NULL, OFF),
439 CLK_DUMMY("spi_clk", GSBI1_QUP_CLK, NULL, OFF),
440 CLK_DUMMY("gsbi_qup_clk", GSBI2_QUP_CLK, NULL, OFF),
441 CLK_DUMMY("gsbi_qup_clk", GSBI3_QUP_CLK, NULL, OFF),
442 CLK_DUMMY("gsbi_qup_clk", GSBI4_QUP_CLK, NULL, OFF),
Harini Jayaramanc4c58692011-07-19 14:50:10 -0600443 CLK_DUMMY("spi_clk", GSBI5_QUP_CLK, "spi_qsd.0", OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700444 CLK_DUMMY("gsbi_qup_clk", GSBI6_QUP_CLK, NULL, OFF),
445 CLK_DUMMY("gsbi_qup_clk", GSBI7_QUP_CLK, NULL, OFF),
446 CLK_DUMMY("gsbi_qup_clk", GSBI8_QUP_CLK, NULL, OFF),
447 CLK_DUMMY("gsbi_qup_clk", GSBI9_QUP_CLK, NULL, OFF),
448 CLK_DUMMY("gsbi_qup_clk", GSBI10_QUP_CLK, NULL, OFF),
449 CLK_DUMMY("gsbi_qup_clk", GSBI11_QUP_CLK, NULL, OFF),
450 CLK_DUMMY("gsbi_qup_clk", GSBI12_QUP_CLK, NULL, OFF),
451 CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
452 CLK_DUMMY("pmem_clk", PMEM_CLK, NULL, OFF),
453 CLK_DUMMY("prng_clk", PRNG_CLK, NULL, OFF),
454 CLK_DUMMY("sdc_clk", SDC1_CLK, NULL, OFF),
455 CLK_DUMMY("sdc_clk", SDC2_CLK, NULL, OFF),
456 CLK_DUMMY("sdc_clk", SDC3_CLK, NULL, OFF),
457 CLK_DUMMY("sdc_clk", SDC4_CLK, NULL, OFF),
458 CLK_DUMMY("sdc_clk", SDC5_CLK, NULL, OFF),
459 CLK_DUMMY("tsif_ref_clk", TSIF_REF_CLK, NULL, OFF),
460 CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
461 CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
462 CLK_DUMMY("usb_phy_clk", USB_PHY0_CLK, NULL, OFF),
463 CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
464 CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL, OFF),
465 CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
466 CLK_DUMMY("usb_fs_src_clk", USB_FS2_SRC_CLK, NULL, OFF),
467 CLK_DUMMY("usb_fs_clk", USB_FS2_XCVR_CLK, NULL, OFF),
468 CLK_DUMMY("usb_fs_sys_clk", USB_FS2_SYS_CLK, NULL, OFF),
469 CLK_DUMMY("ce_pclk", CE2_CLK, NULL, OFF),
470 CLK_DUMMY("ce_clk", CE1_CORE_CLK, NULL, OFF),
471 CLK_DUMMY("spi_pclk", GSBI1_P_CLK, NULL, OFF),
472 CLK_DUMMY("gsbi_pclk", GSBI2_P_CLK, NULL, OFF),
473 CLK_DUMMY("gsbi_pclk", GSBI3_P_CLK,
474 "msm_serial_hsl.0", OFF),
475 CLK_DUMMY("gsbi_pclk", GSBI4_P_CLK, NULL, OFF),
Harini Jayaramanc4c58692011-07-19 14:50:10 -0600476 CLK_DUMMY("spi_pclk", GSBI5_P_CLK, "spi_qsd.0", OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700477 CLK_DUMMY("uartdm_pclk", GSBI6_P_CLK, NULL, OFF),
478 CLK_DUMMY("gsbi_pclk", GSBI7_P_CLK, NULL, OFF),
479 CLK_DUMMY("gsbi_pclk", GSBI8_P_CLK, NULL, OFF),
480 CLK_DUMMY("gsbi_pclk", GSBI9_P_CLK, NULL, OFF),
481 CLK_DUMMY("gsbi_pclk", GSBI10_P_CLK, NULL, OFF),
482 CLK_DUMMY("gsbi_pclk", GSBI11_P_CLK, NULL, OFF),
483 CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL, OFF),
484 CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL, OFF),
485 CLK_DUMMY("tsif_pclk", TSIF_P_CLK, NULL, OFF),
486 CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL, OFF),
487 CLK_DUMMY("usb_fs_pclk", USB_FS2_P_CLK, NULL, OFF),
488 CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL, OFF),
489 CLK_DUMMY("sdc_pclk", SDC1_P_CLK, NULL, OFF),
490 CLK_DUMMY("sdc_pclk", SDC2_P_CLK, NULL, OFF),
491 CLK_DUMMY("sdc_pclk", SDC3_P_CLK, NULL, OFF),
492 CLK_DUMMY("sdc_pclk", SDC4_P_CLK, NULL, OFF),
493 CLK_DUMMY("sdc_pclk", SDC5_P_CLK, NULL, OFF),
494 CLK_DUMMY("adm_clk", ADM0_CLK, NULL, OFF),
495 CLK_DUMMY("adm_pclk", ADM0_P_CLK, NULL, OFF),
496 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
497 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
498 CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
499 CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
500 CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
501 CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
502 CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
503 CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
504 CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF),
505 CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
506 CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF),
507 CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
508 CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
509 CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF),
510 CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF),
511 CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF),
512 CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, NULL, OFF),
513 CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, NULL, OFF),
514 CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, NULL, OFF),
515 CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, NULL, OFF),
516 CLK_DUMMY("gfx2d0_clk", GFX2D0_CLK, NULL, OFF),
517 CLK_DUMMY("gfx2d1_clk", GFX2D1_CLK, NULL, OFF),
518 CLK_DUMMY("gfx3d_clk", GFX3D_CLK, NULL, OFF),
519 CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
520 CLK_DUMMY("imem_clk", IMEM_CLK, NULL, OFF),
521 CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
522 CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
523 CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
524 CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
525 CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
526 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
527 CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
528 CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
529 CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
530 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
531 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
532 CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL, OFF),
533 CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF),
534 CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF),
535 CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF),
536 CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
537 CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
538 CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
539 CLK_DUMMY("rot_axi_clk", ROT_AXI_CLK, NULL, OFF),
540 CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
541 CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
542 CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
543 CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF),
544 CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF),
545 CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF),
546 CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, NULL, OFF),
547 CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, NULL, OFF),
548 CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, NULL, OFF),
549 CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, NULL, OFF),
550 CLK_DUMMY("gfx2d0_pclk", GFX2D0_P_CLK, NULL, OFF),
551 CLK_DUMMY("gfx2d1_pclk", GFX2D1_P_CLK, NULL, OFF),
552 CLK_DUMMY("gfx3d_pclk", GFX3D_P_CLK, NULL, OFF),
553 CLK_DUMMY("hdmi_m_pclk", HDMI_M_P_CLK, NULL, OFF),
554 CLK_DUMMY("hdmi_s_pclk", HDMI_S_P_CLK, NULL, OFF),
555 CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF),
556 CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
557 CLK_DUMMY("imem_pclk", IMEM_P_CLK, NULL, OFF),
558 CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
559 CLK_DUMMY("smmu_pclk", SMMU_P_CLK, NULL, OFF),
560 CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
561 CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL, OFF),
562 CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
563 CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
564 CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
565 CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
566 CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
567 CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
568 CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
569 CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
570 CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
571 CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
572 CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
573 CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
574 CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
575 CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
576 CLK_DUMMY("iommu_clk", JPEGD_AXI_CLK, NULL, 0),
577 CLK_DUMMY("iommu_clk", VFE_AXI_CLK, NULL, 0),
578 CLK_DUMMY("iommu_clk", VCODEC_AXI_CLK, NULL, 0),
579 CLK_DUMMY("iommu_clk", GFX3D_CLK, NULL, 0),
580 CLK_DUMMY("iommu_clk", GFX2D0_CLK, NULL, 0),
581 CLK_DUMMY("iommu_clk", GFX2D1_CLK, NULL, 0),
582
583 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
584 CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
585 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC1_CLK, NULL, 0),
586 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC2_CLK, NULL, 0),
587 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC3_CLK, NULL, 0),
588 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC4_CLK, NULL, 0),
589 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC5_CLK, NULL, 0),
590 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
591 CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0),
592};
593
594unsigned msm_num_clocks_8064_dummy = ARRAY_SIZE(msm_clocks_8064_dummy);