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gerrit-public.fairphone.software / kernel / msm / c4d7e58fb52c632d8e33cd23a4917d7a7f8302ac / . / arch / arm / mach-omap2 / cm2xxx_3xxx.c
blob: e3d598a4c62472f6b36bdb7798cdf126138b3e2d [file] [log] [blame]
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]1/*
2 * OMAP2/3 CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]13#include <linux/types.h>
14#include <linux/delay.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
Paul Walmsley6f8b7ff2009-12-08 16:33:16 -0700[diff] [blame]21#include <plat/common.h>
22
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]23#include "cm.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]24#include "cm2xxx_3xxx.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]25#include "cm-regbits-24xx.h"
26#include "cm-regbits-34xx.h"
27
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]28static const u8 cm_idlest_offs[] = {
29 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
30};
31
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]32u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]33{
34 return __raw_readl(cm_base + module + idx);
35}
36
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]37void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]38{
39 __raw_writel(val, cm_base + module + idx);
40}
41
42/* Read-modify-write a register in a CM module. Caller must lock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]43u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]44{
45 u32 v;
46
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]47 v = omap2_cm_read_mod_reg(module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]48 v &= ~mask;
49 v |= bits;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]50 omap2_cm_write_mod_reg(v, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]51
52 return v;
53}
54
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]55u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]56{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]57 return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]58}
59
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]60u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]61{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]62 return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]63}
64
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]65/**
66 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
67 * @prcm_mod: PRCM module offset
68 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
69 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
70 *
71 * XXX document
72 */
73int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
74{
75 int ena = 0, i = 0;
76 u8 cm_idlest_reg;
77 u32 mask;
78
79 if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
80 return -EINVAL;
81
82 cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
83
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]84 mask = 1 << idlest_shift;
85
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]86 if (cpu_is_omap24xx())
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]87 ena = mask;
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]88 else if (cpu_is_omap34xx())
89 ena = 0;
90 else
91 BUG();
92
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]93 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
Paul Walmsley6f8b7ff2009-12-08 16:33:16 -0700[diff] [blame]94 MAX_MODULE_READY_TIME, i);
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]95
96 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
97}
98
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]99/*
100 * Context save/restore code - OMAP3 only
101 */
102#ifdef CONFIG_ARCH_OMAP3
103struct omap3_cm_regs {
104 u32 iva2_cm_clksel1;
105 u32 iva2_cm_clksel2;
106 u32 cm_sysconfig;
107 u32 sgx_cm_clksel;
108 u32 dss_cm_clksel;
109 u32 cam_cm_clksel;
110 u32 per_cm_clksel;
111 u32 emu_cm_clksel;
112 u32 emu_cm_clkstctrl;
113 u32 pll_cm_autoidle2;
114 u32 pll_cm_clksel4;
115 u32 pll_cm_clksel5;
116 u32 pll_cm_clken2;
117 u32 cm_polctrl;
118 u32 iva2_cm_fclken;
119 u32 iva2_cm_clken_pll;
120 u32 core_cm_fclken1;
121 u32 core_cm_fclken3;
122 u32 sgx_cm_fclken;
123 u32 wkup_cm_fclken;
124 u32 dss_cm_fclken;
125 u32 cam_cm_fclken;
126 u32 per_cm_fclken;
127 u32 usbhost_cm_fclken;
128 u32 core_cm_iclken1;
129 u32 core_cm_iclken2;
130 u32 core_cm_iclken3;
131 u32 sgx_cm_iclken;
132 u32 wkup_cm_iclken;
133 u32 dss_cm_iclken;
134 u32 cam_cm_iclken;
135 u32 per_cm_iclken;
136 u32 usbhost_cm_iclken;
137 u32 iva2_cm_autoidle2;
138 u32 mpu_cm_autoidle2;
139 u32 iva2_cm_clkstctrl;
140 u32 mpu_cm_clkstctrl;
141 u32 core_cm_clkstctrl;
142 u32 sgx_cm_clkstctrl;
143 u32 dss_cm_clkstctrl;
144 u32 cam_cm_clkstctrl;
145 u32 per_cm_clkstctrl;
146 u32 neon_cm_clkstctrl;
147 u32 usbhost_cm_clkstctrl;
148 u32 core_cm_autoidle1;
149 u32 core_cm_autoidle2;
150 u32 core_cm_autoidle3;
151 u32 wkup_cm_autoidle;
152 u32 dss_cm_autoidle;
153 u32 cam_cm_autoidle;
154 u32 per_cm_autoidle;
155 u32 usbhost_cm_autoidle;
156 u32 sgx_cm_sleepdep;
157 u32 dss_cm_sleepdep;
158 u32 cam_cm_sleepdep;
159 u32 per_cm_sleepdep;
160 u32 usbhost_cm_sleepdep;
161 u32 cm_clkout_ctrl;
162};
163
164static struct omap3_cm_regs cm_context;
165
166void omap3_cm_save_context(void)
167{
168 cm_context.iva2_cm_clksel1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]169 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]170 cm_context.iva2_cm_clksel2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]171 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]172 cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
173 cm_context.sgx_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]174 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]175 cm_context.dss_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]176 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]177 cm_context.cam_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]178 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]179 cm_context.per_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]180 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]181 cm_context.emu_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]182 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]183 cm_context.emu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]184 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]185 cm_context.pll_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]186 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]187 cm_context.pll_cm_clksel4 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]188 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]189 cm_context.pll_cm_clksel5 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]190 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]191 cm_context.pll_cm_clken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]192 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]193 cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
194 cm_context.iva2_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]195 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
196 cm_context.iva2_cm_clken_pll =
197 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]198 cm_context.core_cm_fclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]199 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]200 cm_context.core_cm_fclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]201 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]202 cm_context.sgx_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]203 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]204 cm_context.wkup_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]205 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]206 cm_context.dss_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]207 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]208 cm_context.cam_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]209 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]210 cm_context.per_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]211 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]212 cm_context.usbhost_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]213 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]214 cm_context.core_cm_iclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]215 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]216 cm_context.core_cm_iclken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]217 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]218 cm_context.core_cm_iclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]219 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]220 cm_context.sgx_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]221 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]222 cm_context.wkup_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]223 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]224 cm_context.dss_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]225 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]226 cm_context.cam_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]227 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]228 cm_context.per_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]229 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]230 cm_context.usbhost_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]231 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]232 cm_context.iva2_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]233 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]234 cm_context.mpu_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]235 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]236 cm_context.iva2_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]237 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]238 cm_context.mpu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]239 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]240 cm_context.core_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]241 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]242 cm_context.sgx_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]243 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]244 cm_context.dss_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]245 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]246 cm_context.cam_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]247 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]248 cm_context.per_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]249 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]250 cm_context.neon_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]251 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]252 cm_context.usbhost_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]253 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
254 OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]255 cm_context.core_cm_autoidle1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]256 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]257 cm_context.core_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]258 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]259 cm_context.core_cm_autoidle3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]260 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]261 cm_context.wkup_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]262 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]263 cm_context.dss_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]264 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]265 cm_context.cam_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]266 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]267 cm_context.per_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]268 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]269 cm_context.usbhost_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]270 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]271 cm_context.sgx_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]272 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
273 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]274 cm_context.dss_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]275 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]276 cm_context.cam_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]277 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]278 cm_context.per_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]279 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]280 cm_context.usbhost_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]281 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
282 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]283 cm_context.cm_clkout_ctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]284 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
285 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]286}
287
288void omap3_cm_restore_context(void)
289{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]290 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
291 CM_CLKSEL1);
292 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
293 CM_CLKSEL2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]294 __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]295 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
296 CM_CLKSEL);
297 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
298 CM_CLKSEL);
299 omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
300 CM_CLKSEL);
301 omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
302 CM_CLKSEL);
303 omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
304 CM_CLKSEL1);
305 omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
306 OMAP2_CM_CLKSTCTRL);
307 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
308 CM_AUTOIDLE2);
309 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
310 OMAP3430ES2_CM_CLKSEL4);
311 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
312 OMAP3430ES2_CM_CLKSEL5);
313 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
314 OMAP3430ES2_CM_CLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]315 __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame^]316 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
317 CM_FCLKEN);
318 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
319 OMAP3430_CM_CLKEN_PLL);
320 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
321 CM_FCLKEN1);
322 omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
323 OMAP3430ES2_CM_FCLKEN3);
324 omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
325 CM_FCLKEN);
326 omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
327 omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
328 CM_FCLKEN);
329 omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
330 CM_FCLKEN);
331 omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
332 CM_FCLKEN);
333 omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
334 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
335 omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
336 CM_ICLKEN1);
337 omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
338 CM_ICLKEN2);
339 omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
340 CM_ICLKEN3);
341 omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
342 CM_ICLKEN);
343 omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
344 omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
345 CM_ICLKEN);
346 omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
347 CM_ICLKEN);
348 omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
349 CM_ICLKEN);
350 omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
351 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
352 omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
353 CM_AUTOIDLE2);
354 omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
355 CM_AUTOIDLE2);
356 omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
357 OMAP2_CM_CLKSTCTRL);
358 omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
359 OMAP2_CM_CLKSTCTRL);
360 omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
361 OMAP2_CM_CLKSTCTRL);
362 omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
363 OMAP2_CM_CLKSTCTRL);
364 omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
365 OMAP2_CM_CLKSTCTRL);
366 omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
367 OMAP2_CM_CLKSTCTRL);
368 omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
369 OMAP2_CM_CLKSTCTRL);
370 omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
371 OMAP2_CM_CLKSTCTRL);
372 omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
373 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
374 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
375 CM_AUTOIDLE1);
376 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
377 CM_AUTOIDLE2);
378 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
379 CM_AUTOIDLE3);
380 omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
381 CM_AUTOIDLE);
382 omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
383 CM_AUTOIDLE);
384 omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
385 CM_AUTOIDLE);
386 omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
387 CM_AUTOIDLE);
388 omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
389 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
390 omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
391 OMAP3430_CM_SLEEPDEP);
392 omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
393 OMAP3430_CM_SLEEPDEP);
394 omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
395 OMAP3430_CM_SLEEPDEP);
396 omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
397 OMAP3430_CM_SLEEPDEP);
398 omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
399 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
400 omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
401 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]402}
403#endif