| SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h |
| 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People |
| 6 | * |
| 7 | * System peripherals registers. |
| 8 | * Based on AT91RM9200 datasheet revision E. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #ifndef AT91RM9200_SYS_H |
| 17 | #define AT91RM9200_SYS_H |
| 18 | |
| 19 | /* |
| 20 | * Advanced Interrupt Controller. |
| 21 | */ |
| 22 | #define AT91_AIC 0x000 |
| 23 | |
| 24 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ |
| 25 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ |
| 26 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ |
| 27 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) |
| 28 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) |
| 29 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) |
| 30 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) |
| 31 | |
| 32 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ |
| 33 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ |
| 34 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ |
| 35 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ |
| 36 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ |
| 37 | |
| 38 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ |
| 39 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ |
| 40 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ |
| 41 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ |
| 42 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ |
| 43 | |
| 44 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ |
| 45 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ |
| 46 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ |
| 47 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ |
| 48 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ |
| 49 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ |
| 50 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ |
| 51 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ |
| 52 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ |
| 53 | |
| 54 | |
| 55 | /* |
| 56 | * Debug Unit. |
| 57 | */ |
| 58 | #define AT91_DBGU 0x200 |
| 59 | |
| 60 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ |
| 61 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ |
| 62 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ |
| 63 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ |
| 64 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ |
| 65 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ |
| 66 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ |
| 67 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ |
| 68 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ |
| 69 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ |
| 70 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ |
| 71 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ |
| 72 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ |
| 73 | |
| 74 | |
| 75 | /* |
| 76 | * PIO Controllers. |
| 77 | */ |
| 78 | #define AT91_PIOA 0x400 |
| 79 | #define AT91_PIOB 0x600 |
| 80 | #define AT91_PIOC 0x800 |
| 81 | #define AT91_PIOD 0xa00 |
| 82 | |
| 83 | #define PIO_PER 0x00 /* Enable Register */ |
| 84 | #define PIO_PDR 0x04 /* Disable Register */ |
| 85 | #define PIO_PSR 0x08 /* Status Register */ |
| 86 | #define PIO_OER 0x10 /* Output Enable Register */ |
| 87 | #define PIO_ODR 0x14 /* Output Disable Register */ |
| 88 | #define PIO_OSR 0x18 /* Output Status Register */ |
| 89 | #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ |
| 90 | #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ |
| 91 | #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ |
| 92 | #define PIO_SODR 0x30 /* Set Output Data Register */ |
| 93 | #define PIO_CODR 0x34 /* Clear Output Data Register */ |
| 94 | #define PIO_ODSR 0x38 /* Output Data Status Register */ |
| 95 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ |
| 96 | #define PIO_IER 0x40 /* Interrupt Enable Register */ |
| 97 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ |
| 98 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ |
| 99 | #define PIO_ISR 0x4c /* Interrupt Status Register */ |
| 100 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ |
| 101 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ |
| 102 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ |
| 103 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ |
| 104 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ |
| 105 | #define PIO_PUSR 0x68 /* Pull-up Status Register */ |
| 106 | #define PIO_ASR 0x70 /* Peripheral A Select Register */ |
| 107 | #define PIO_BSR 0x74 /* Peripheral B Select Register */ |
| 108 | #define PIO_ABSR 0x78 /* AB Status Register */ |
| 109 | #define PIO_OWER 0xa0 /* Output Write Enable Register */ |
| 110 | #define PIO_OWDR 0xa4 /* Output Write Disable Register */ |
| 111 | #define PIO_OWSR 0xa8 /* Output Write Status Register */ |
| 112 | |
| 113 | #define AT91_PIO_P(n) (1 << (n)) |
| 114 | |
| 115 | |
| 116 | /* |
| 117 | * Power Management Controller. |
| 118 | */ |
| 119 | #define AT91_PMC 0xc00 |
| 120 | |
| 121 | #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ |
| 122 | #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ |
| 123 | |
| 124 | #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ |
| 125 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
| 126 | #define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */ |
| 127 | #define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */ |
| 128 | #define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */ |
| 129 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ |
| 130 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ |
| 131 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ |
| 132 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ |
| 133 | |
| 134 | #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ |
| 135 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ |
| 136 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ |
| 137 | |
| 138 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ |
| 139 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
| 140 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
| 141 | |
| 142 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ |
| 143 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ |
| 144 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ |
| 145 | |
| 146 | #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ |
| 147 | #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ |
| 148 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ |
| 149 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ |
| 150 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ |
| 151 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ |
| 152 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ |
| 153 | |
| 154 | #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ |
| 155 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ |
| 156 | #define AT91_PMC_CSS_SLOW (0 << 0) |
| 157 | #define AT91_PMC_CSS_MAIN (1 << 0) |
| 158 | #define AT91_PMC_CSS_PLLA (2 << 0) |
| 159 | #define AT91_PMC_CSS_PLLB (3 << 0) |
| 160 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ |
| 161 | #define AT91_PMC_PRES_1 (0 << 2) |
| 162 | #define AT91_PMC_PRES_2 (1 << 2) |
| 163 | #define AT91_PMC_PRES_4 (2 << 2) |
| 164 | #define AT91_PMC_PRES_8 (3 << 2) |
| 165 | #define AT91_PMC_PRES_16 (4 << 2) |
| 166 | #define AT91_PMC_PRES_32 (5 << 2) |
| 167 | #define AT91_PMC_PRES_64 (6 << 2) |
| 168 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ |
| 169 | #define AT91_PMC_MDIV_1 (0 << 8) |
| 170 | #define AT91_PMC_MDIV_2 (1 << 8) |
| 171 | #define AT91_PMC_MDIV_3 (2 << 8) |
| 172 | #define AT91_PMC_MDIV_4 (3 << 8) |
| 173 | |
| 174 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ |
| 175 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ |
| 176 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ |
| 177 | #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ |
| 178 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ |
| 179 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
| 180 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
| 181 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ |
| 182 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
| 183 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
| 184 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
| 185 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ |
| 186 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ |
| 187 | |
| 188 | |
| 189 | /* |
| 190 | * System Timer. |
| 191 | */ |
| 192 | #define AT91_ST 0xd00 |
| 193 | |
| 194 | #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ |
| 195 | #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ |
| 196 | #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ |
| 197 | #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ |
| 198 | #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ |
| 199 | #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ |
| 200 | #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ |
| 201 | #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ |
| 202 | #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ |
| 203 | #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ |
| 204 | #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ |
| 205 | #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ |
| 206 | #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ |
| 207 | #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ |
| 208 | #define AT91_ST_ALMS (1 << 3) /* Alarm Status */ |
| 209 | #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ |
| 210 | #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ |
| 211 | #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ |
| 212 | #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ |
| 213 | #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ |
| 214 | #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ |
| 215 | #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ |
| 216 | |
| 217 | |
| 218 | /* |
| 219 | * Real-time Clock. |
| 220 | */ |
| 221 | #define AT91_RTC 0xe00 |
| 222 | |
| 223 | #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ |
| 224 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ |
| 225 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ |
| 226 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ |
| 227 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) |
| 228 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) |
| 229 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) |
| 230 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) |
| 231 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ |
| 232 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) |
| 233 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) |
| 234 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) |
| 235 | |
| 236 | #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ |
| 237 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ |
| 238 | |
| 239 | #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ |
| 240 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ |
| 241 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ |
| 242 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ |
| 243 | #define At91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ |
| 244 | |
| 245 | #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ |
| 246 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ |
| 247 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ |
| 248 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ |
| 249 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ |
| 250 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ |
| 251 | |
| 252 | #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ |
| 253 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ |
| 254 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ |
| 255 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ |
| 256 | |
| 257 | #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ |
| 258 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ |
| 259 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ |
| 260 | |
| 261 | #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ |
| 262 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ |
| 263 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ |
| 264 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ |
| 265 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ |
| 266 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ |
| 267 | |
| 268 | #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ |
| 269 | #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ |
| 270 | #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ |
| 271 | #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ |
| 272 | |
| 273 | #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ |
| 274 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ |
| 275 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ |
| 276 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ |
| 277 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ |
| 278 | |
| 279 | |
| 280 | /* |
| 281 | * Memory Controller. |
| 282 | */ |
| 283 | #define AT91_MC 0xf00 |
| 284 | |
| 285 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ |
| 286 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ |
| 287 | |
| 288 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ |
| 289 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ |
| 290 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ |
| 291 | |
| 292 | /* External Bus Interface (EBI) registers */ |
| 293 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ |
| 294 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ |
| 295 | #define AT91_EBI_CS0A_SMC (0 << 0) |
| 296 | #define AT91_EBI_CS0A_BFC (1 << 0) |
| 297 | #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
| 298 | #define AT91_EBI_CS1A_SMC (0 << 1) |
| 299 | #define AT91_EBI_CS1A_SDRAMC (1 << 1) |
| 300 | #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ |
| 301 | #define AT91_EBI_CS3A_SMC (0 << 3) |
| 302 | #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) |
| 303 | #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ |
| 304 | #define AT91_EBI_CS4A_SMC (0 << 4) |
| 305 | #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) |
| 306 | #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ |
| 307 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ |
| 308 | |
| 309 | /* Static Memory Controller (SMC) registers */ |
| 310 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ |
| 311 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ |
| 312 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ |
| 313 | #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ |
| 314 | #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ |
| 315 | #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ |
| 316 | #define AT91_SMC_DBW_16 (1 << 13) |
| 317 | #define AT91_SMC_DBW_8 (2 << 13) |
| 318 | #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ |
| 319 | #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ |
| 320 | #define AT91_SMC_ACSS_STD (0 << 16) |
| 321 | #define AT91_SMC_ACSS_1 (1 << 16) |
| 322 | #define AT91_SMC_ACSS_2 (2 << 16) |
| 323 | #define AT91_SMC_ACSS_3 (3 << 16) |
| 324 | #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ |
| 325 | #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ |
| 326 | |
| 327 | |
| 328 | #endif |