blob: 3cda63e37b28d0c18b76c6b3bb866755943310a3 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
Dave Airlie746c1aa2009-12-08 07:07:28 +100036#include <drm_dp_helper.h>
Ben Skeggs68adac52010-04-28 11:46:42 +100037#include <drm_fixed.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020038#include <linux/i2c.h>
39#include <linux/i2c-id.h>
40#include <linux/i2c-algo-bit.h>
Jerome Glissec93bb852009-07-13 21:04:08 +020041
Dave Airlie38651672010-03-30 05:34:13 +000042struct radeon_bo;
Jerome Glissec93bb852009-07-13 21:04:08 +020043struct radeon_device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020044
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
Jerome Glisse771fe6b2009-06-05 14:42:42 +020050enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
Alex Deucherd79766f2009-12-17 19:00:29 -050066 TV_STD_PAL_N,
Jerome Glisse771fe6b2009-06-05 14:42:42 +020067};
68
Alex Deucher5b1714d2010-08-03 19:59:20 -040069enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
Alex Deucher8e36ed02010-05-18 19:26:47 -040075enum radeon_hpd_id {
76 RADEON_HPD_1 = 0,
77 RADEON_HPD_2,
78 RADEON_HPD_3,
79 RADEON_HPD_4,
80 RADEON_HPD_5,
81 RADEON_HPD_6,
82 RADEON_HPD_NONE = 0xff,
83};
84
Alex Deucherf376b942010-08-05 21:21:16 -040085#define RADEON_MAX_I2C_BUS 16
86
Alex Deucher9b9fe722009-11-10 15:59:44 -050087/* radeon gpio-based i2c
88 * 1. "mask" reg and bits
89 * grabs the gpio pins for software use
90 * 0=not held 1=held
91 * 2. "a" reg and bits
92 * output pin value
93 * 0=low 1=high
94 * 3. "en" reg and bits
95 * sets the pin direction
96 * 0=input 1=output
97 * 4. "y" reg and bits
98 * input pin value
99 * 0=low 1=high
100 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200101struct radeon_i2c_bus_rec {
102 bool valid;
Alex Deucher6a93cb22009-11-23 17:39:28 -0500103 /* id used by atom */
104 uint8_t i2c_id;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500105 /* id used by atom */
Alex Deucher8e36ed02010-05-18 19:26:47 -0400106 enum radeon_hpd_id hpd;
Alex Deucher6a93cb22009-11-23 17:39:28 -0500107 /* can be used with hw i2c engine */
108 bool hw_capable;
109 /* uses multi-media i2c engine */
110 bool mm_i2c;
111 /* regs and bits */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200112 uint32_t mask_clk_reg;
113 uint32_t mask_data_reg;
114 uint32_t a_clk_reg;
115 uint32_t a_data_reg;
Alex Deucher9b9fe722009-11-10 15:59:44 -0500116 uint32_t en_clk_reg;
117 uint32_t en_data_reg;
118 uint32_t y_clk_reg;
119 uint32_t y_data_reg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200120 uint32_t mask_clk_mask;
121 uint32_t mask_data_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122 uint32_t a_clk_mask;
123 uint32_t a_data_mask;
Alex Deucher9b9fe722009-11-10 15:59:44 -0500124 uint32_t en_clk_mask;
125 uint32_t en_data_mask;
126 uint32_t y_clk_mask;
127 uint32_t y_data_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200128};
129
130struct radeon_tmds_pll {
131 uint32_t freq;
132 uint32_t value;
133};
134
135#define RADEON_MAX_BIOS_CONNECTOR 16
136
Alex Deucher7c27f872010-02-02 12:05:01 -0500137/* pll flags */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200138#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
139#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
140#define RADEON_PLL_USE_REF_DIV (1 << 2)
141#define RADEON_PLL_LEGACY (1 << 3)
Alex Deucherf28488c2010-09-29 11:37:40 -0400142#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 4)
143#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 5)
144#define RADEON_PLL_USE_POST_DIV (1 << 6)
145#define RADEON_PLL_IS_LCD (1 << 7)
Alex Deucher7c27f872010-02-02 12:05:01 -0500146
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200147struct radeon_pll {
Alex Deucherfc103322010-01-19 17:16:10 -0500148 /* reference frequency */
149 uint32_t reference_freq;
150
151 /* fixed dividers */
152 uint32_t reference_div;
153 uint32_t post_div;
154
155 /* pll in/out limits */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200156 uint32_t pll_in_min;
157 uint32_t pll_in_max;
158 uint32_t pll_out_min;
159 uint32_t pll_out_max;
Alex Deucher86cb2bb2010-03-08 12:55:16 -0500160 uint32_t lcd_pll_out_min;
161 uint32_t lcd_pll_out_max;
Alex Deucherfc103322010-01-19 17:16:10 -0500162 uint32_t best_vco;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163
Alex Deucherfc103322010-01-19 17:16:10 -0500164 /* divider limits */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200165 uint32_t min_ref_div;
166 uint32_t max_ref_div;
167 uint32_t min_post_div;
168 uint32_t max_post_div;
169 uint32_t min_feedback_div;
170 uint32_t max_feedback_div;
171 uint32_t min_frac_feedback_div;
172 uint32_t max_frac_feedback_div;
Alex Deucherfc103322010-01-19 17:16:10 -0500173
174 /* flags for the current clock */
175 uint32_t flags;
176
177 /* pll id */
178 uint32_t id;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200179};
180
181struct radeon_i2c_chan {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200182 struct i2c_adapter adapter;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000183 struct drm_device *dev;
184 union {
Alex Deucherac1aade2010-03-14 12:22:44 -0400185 struct i2c_algo_bit_data bit;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000186 struct i2c_algo_dp_aux_data dp;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000187 } algo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200188 struct radeon_i2c_bus_rec rec;
189};
190
191/* mostly for macs, but really any system without connector tables */
192enum radeon_connector_table {
Alex Deucheraa74fbb2010-09-07 14:41:30 -0400193 CT_NONE = 0,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200194 CT_GENERIC,
195 CT_IBOOK,
196 CT_POWERBOOK_EXTERNAL,
197 CT_POWERBOOK_INTERNAL,
198 CT_POWERBOOK_VGA,
199 CT_MINI_EXTERNAL,
200 CT_MINI_INTERNAL,
201 CT_IMAC_G5_ISIGHT,
202 CT_EMAC,
Dave Airlie76a71422010-06-11 01:09:05 -0400203 CT_RN50_POWER,
Alex Deucheraa74fbb2010-09-07 14:41:30 -0400204 CT_MAC_X800,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200205};
206
Alex Deucherfcec5702009-11-10 21:25:07 -0500207enum radeon_dvo_chip {
208 DVO_SIL164,
209 DVO_SIL1178,
210};
211
Dave Airlie8be48d92010-03-30 05:34:14 +0000212struct radeon_fbdev;
Dave Airlie38651672010-03-30 05:34:13 +0000213
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200214struct radeon_mode_info {
215 struct atom_context *atom_context;
Mathias Fröhlich61c4b242009-10-27 15:08:01 -0400216 struct card_info *atom_card_info;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200217 enum radeon_connector_table connector_table;
218 bool mode_config_initialized;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500219 struct radeon_crtc *crtcs[6];
Dave Airlie445282d2009-09-09 17:40:54 +1000220 /* DVI-I properties */
221 struct drm_property *coherent_mode_property;
222 /* DAC enable load detect */
223 struct drm_property *load_detect_property;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400224 /* TV standard */
Dave Airlie445282d2009-09-09 17:40:54 +1000225 struct drm_property *tv_std_property;
226 /* legacy TMDS PLL detect */
227 struct drm_property *tmds_pll_property;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400228 /* underscan */
229 struct drm_property *underscan_property;
Marius Gröger5bccf5e2010-09-21 21:30:59 +0200230 struct drm_property *underscan_hborder_property;
231 struct drm_property *underscan_vborder_property;
Alex Deucher3c537882010-02-05 04:21:19 -0500232 /* hardcoded DFP edid from BIOS */
233 struct edid *bios_hardcoded_edid;
Dave Airlie38651672010-03-30 05:34:13 +0000234
235 /* pointer to fbdev info structure */
Dave Airlie8be48d92010-03-30 05:34:14 +0000236 struct radeon_fbdev *rfbdev;
Jerome Glissec93bb852009-07-13 21:04:08 +0200237};
238
Dave Airlie4ce001a2009-08-13 16:32:14 +1000239#define MAX_H_CODE_TIMING_LEN 32
240#define MAX_V_CODE_TIMING_LEN 32
241
242/* need to store these as reading
243 back code tables is excessive */
244struct radeon_tv_regs {
245 uint32_t tv_uv_adr;
246 uint32_t timing_cntl;
247 uint32_t hrestart;
248 uint32_t vrestart;
249 uint32_t frestart;
250 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
251 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
252};
253
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200254struct radeon_crtc {
255 struct drm_crtc base;
256 int crtc_id;
257 u16 lut_r[256], lut_g[256], lut_b[256];
Jason Wesselff773712010-09-26 06:47:26 -0500258 u16 lut_r_copy[256], lut_g_copy[256], lut_b_copy[256];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200259 bool enabled;
260 bool can_tile;
261 uint32_t crtc_offset;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200262 struct drm_gem_object *cursor_bo;
263 uint64_t cursor_addr;
264 int cursor_width;
265 int cursor_height;
Dave Airlie41623382009-07-09 15:04:19 +1000266 uint32_t legacy_display_base_addr;
Alex Deucherc836e862009-07-13 13:51:03 -0400267 uint32_t legacy_cursor_offset;
Jerome Glissec93bb852009-07-13 21:04:08 +0200268 enum radeon_rmx_type rmx_type;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400269 u8 h_border;
270 u8 v_border;
Jerome Glissec93bb852009-07-13 21:04:08 +0200271 fixed20_12 vsc;
272 fixed20_12 hsc;
Alex Deucherde2103e2009-10-09 15:14:30 -0400273 struct drm_display_mode native_mode;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500274 int pll_id;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200275};
276
277struct radeon_encoder_primary_dac {
278 /* legacy primary dac */
279 uint32_t ps2_pdac_adj;
280};
281
282struct radeon_encoder_lvds {
283 /* legacy lvds */
284 uint16_t panel_vcc_delay;
285 uint8_t panel_pwr_delay;
286 uint8_t panel_digon_delay;
287 uint8_t panel_blon_delay;
288 uint16_t panel_ref_divider;
289 uint8_t panel_post_divider;
290 uint16_t panel_fb_divider;
291 bool use_bios_dividers;
292 uint32_t lvds_gen_cntl;
293 /* panel mode */
Alex Deucherde2103e2009-10-09 15:14:30 -0400294 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200295};
296
297struct radeon_encoder_tv_dac {
298 /* legacy tv dac */
299 uint32_t ps2_tvdac_adj;
300 uint32_t ntsc_tvdac_adj;
301 uint32_t pal_tvdac_adj;
302
Dave Airlie4ce001a2009-08-13 16:32:14 +1000303 int h_pos;
304 int v_pos;
305 int h_size;
306 int supported_tv_stds;
307 bool tv_on;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200308 enum radeon_tv_std tv_std;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000309 struct radeon_tv_regs tv;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200310};
311
312struct radeon_encoder_int_tmds {
313 /* legacy int tmds */
314 struct radeon_tmds_pll tmds_pll[4];
315};
316
Alex Deucherfcec5702009-11-10 21:25:07 -0500317struct radeon_encoder_ext_tmds {
318 /* tmds over dvo */
319 struct radeon_i2c_chan *i2c_bus;
320 uint8_t slave_addr;
321 enum radeon_dvo_chip dvo_chip;
322};
323
Alex Deucherebbe1cb2009-10-16 11:15:25 -0400324/* spread spectrum */
325struct radeon_atom_ss {
326 uint16_t percentage;
327 uint8_t type;
Alex Deucherba032a52010-10-04 17:13:01 -0400328 uint16_t step;
Alex Deucherebbe1cb2009-10-16 11:15:25 -0400329 uint8_t delay;
330 uint8_t range;
331 uint8_t refdiv;
Alex Deucherba032a52010-10-04 17:13:01 -0400332 /* asic_ss */
333 uint16_t rate;
334 uint16_t amount;
Alex Deucherebbe1cb2009-10-16 11:15:25 -0400335};
336
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200337struct radeon_encoder_atom_dig {
Alex Deucher5137ee92010-08-12 18:58:47 -0400338 bool linkb;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200339 /* atom dig */
340 bool coherent_mode;
Alex Deucherba032a52010-10-04 17:13:01 -0400341 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
342 /* atom lvds/edp */
343 uint32_t lcd_misc;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200344 uint16_t panel_pwr_delay;
Alex Deucherba032a52010-10-04 17:13:01 -0400345 uint32_t lcd_ss_id;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200346 /* panel mode */
Alex Deucherde2103e2009-10-09 15:14:30 -0400347 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200348};
349
Dave Airlie4ce001a2009-08-13 16:32:14 +1000350struct radeon_encoder_atom_dac {
351 enum radeon_tv_std tv_std;
352};
353
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200354struct radeon_encoder {
355 struct drm_encoder base;
Alex Deucher5137ee92010-08-12 18:58:47 -0400356 uint32_t encoder_enum;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200357 uint32_t encoder_id;
358 uint32_t devices;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000359 uint32_t active_device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200360 uint32_t flags;
361 uint32_t pixel_clock;
362 enum radeon_rmx_type rmx_type;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400363 enum radeon_underscan_type underscan_type;
Marius Gröger5bccf5e2010-09-21 21:30:59 +0200364 uint32_t underscan_hborder;
365 uint32_t underscan_vborder;
Alex Deucherde2103e2009-10-09 15:14:30 -0400366 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200367 void *enc_priv;
Christian König58bd0862010-04-05 22:14:55 +0200368 int audio_polling_active;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200369 int hdmi_offset;
Rafał Miłecki808032e2010-03-06 13:03:33 +0000370 int hdmi_config_offset;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200371 int hdmi_audio_workaround;
372 int hdmi_buffer_status;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200373};
374
375struct radeon_connector_atom_dig {
376 uint32_t igp_lane_info;
Alex Deucher4143e912009-11-23 18:02:35 -0500377 /* displayport */
Dave Airlie746c1aa2009-12-08 07:07:28 +1000378 struct radeon_i2c_chan *dp_i2c_bus;
Alex Deucher1a66c952009-11-20 19:40:13 -0500379 u8 dpcd[8];
Alex Deucher4143e912009-11-23 18:02:35 -0500380 u8 dp_sink_type;
Alex Deucher5801ead2009-11-24 13:32:59 -0500381 int dp_clock;
382 int dp_lane_count;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200383};
384
Alex Deuchereed45b32009-12-04 14:45:27 -0500385struct radeon_gpio_rec {
386 bool valid;
387 u8 id;
388 u32 reg;
389 u32 mask;
390};
391
Alex Deuchereed45b32009-12-04 14:45:27 -0500392struct radeon_hpd {
393 enum radeon_hpd_id hpd;
394 u8 plugged_state;
395 struct radeon_gpio_rec gpio;
396};
397
Alex Deucher26b5bc92010-08-05 21:21:18 -0400398struct radeon_router {
399 bool valid;
400 u32 router_id;
401 struct radeon_i2c_bus_rec i2c_info;
402 u8 i2c_addr;
403 u8 mux_type;
404 u8 mux_control_pin;
405 u8 mux_state;
406};
407
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200408struct radeon_connector {
409 struct drm_connector base;
410 uint32_t connector_id;
411 uint32_t devices;
412 struct radeon_i2c_chan *ddc_bus;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400413 /* some systems have an hdmi and vga port with a shared ddc line */
Alex Deucher0294cf4f2009-10-15 16:16:35 -0400414 bool shared_ddc;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000415 bool use_digital;
416 /* we need to mind the EDID between detect
417 and get modes due to analog/digital/tvencoder */
418 struct edid *edid;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200419 void *con_priv;
Dave Airlie445282d2009-09-09 17:40:54 +1000420 bool dac_load_detect;
Alex Deucherb75fad02009-11-05 13:16:01 -0500421 uint16_t connector_object_id;
Alex Deuchereed45b32009-12-04 14:45:27 -0500422 struct radeon_hpd hpd;
Alex Deucher26b5bc92010-08-05 21:21:18 -0400423 struct radeon_router router;
424 struct radeon_i2c_chan *router_bus;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200425};
426
427struct radeon_framebuffer {
428 struct drm_framebuffer base;
429 struct drm_gem_object *obj;
430};
431
Mario Kleiner6383cf72010-10-05 19:57:36 -0400432/* radeon_get_crtc_scanoutpos() return flags */
433#define RADEON_SCANOUTPOS_VALID (1 << 0)
434#define RADEON_SCANOUTPOS_INVBL (1 << 1)
435#define RADEON_SCANOUTPOS_ACCURATE (1 << 2)
436
Alex Deucherd79766f2009-12-17 19:00:29 -0500437extern enum radeon_tv_std
438radeon_combios_get_tv_info(struct radeon_device *rdev);
439extern enum radeon_tv_std
440radeon_atombios_get_tv_info(struct radeon_device *rdev);
441
Alex Deucher5b1714d2010-08-03 19:59:20 -0400442extern struct drm_connector *
443radeon_get_connector_for_encoder(struct drm_encoder *encoder);
444
Alex Deucherd4877cf2009-12-04 16:56:37 -0500445extern void radeon_connector_hotplug(struct drm_connector *connector);
446extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
Alex Deucher5801ead2009-11-24 13:32:59 -0500447extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
448 struct drm_display_mode *mode);
449extern void radeon_dp_set_link_config(struct drm_connector *connector,
450 struct drm_display_mode *mode);
451extern void dp_link_train(struct drm_encoder *encoder,
452 struct drm_connector *connector);
Alex Deucher4143e912009-11-23 18:02:35 -0500453extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
Alex Deucher9fa05c92009-11-27 13:01:46 -0500454extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500455extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
Alex Deucher5801ead2009-11-24 13:32:59 -0500456extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
457 int action, uint8_t lane_num,
458 uint8_t lane_set);
Dave Airlie746c1aa2009-12-08 07:07:28 +1000459extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
460 uint8_t write_byte, uint8_t *read_byte);
461
Alex Deucherf376b942010-08-05 21:21:16 -0400462extern void radeon_i2c_init(struct radeon_device *rdev);
463extern void radeon_i2c_fini(struct radeon_device *rdev);
464extern void radeon_combios_i2c_init(struct radeon_device *rdev);
465extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
466extern void radeon_i2c_add(struct radeon_device *rdev,
467 struct radeon_i2c_bus_rec *rec,
468 const char *name);
469extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
470 struct radeon_i2c_bus_rec *i2c_bus);
Dave Airlie746c1aa2009-12-08 07:07:28 +1000471extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
Alex Deucher6a93cb22009-11-23 17:39:28 -0500472 struct radeon_i2c_bus_rec *rec,
473 const char *name);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200474extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
475 struct radeon_i2c_bus_rec *rec,
476 const char *name);
477extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
Alex Deucher5a6f98f2009-12-22 15:04:48 -0500478extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
479 u8 slave_addr,
480 u8 addr,
481 u8 *val);
482extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
483 u8 slave_addr,
484 u8 addr,
485 u8 val);
Alex Deucher26b5bc92010-08-05 21:21:18 -0400486extern void radeon_router_select_port(struct radeon_connector *radeon_connector);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200487extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
488extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
489
490extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
491
Alex Deucherba032a52010-10-04 17:13:01 -0400492extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
493 struct radeon_atom_ss *ss,
494 int id);
495extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
496 struct radeon_atom_ss *ss,
497 int id, u32 clock);
498
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200499extern void radeon_compute_pll(struct radeon_pll *pll,
500 uint64_t freq,
501 uint32_t *dot_clock_p,
502 uint32_t *fb_div_p,
503 uint32_t *frac_fb_div_p,
504 uint32_t *ref_div_p,
Alex Deucherfc103322010-01-19 17:16:10 -0500505 uint32_t *post_div_p);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200506
Dave Airlie1f3b6a42009-10-13 14:10:37 +1000507extern void radeon_setup_encoder_clones(struct drm_device *dev);
508
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200509struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
510struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
511struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
512struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
513struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
514extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
Alex Deucher32f48ff2009-11-30 01:54:16 -0500515extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200516extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000517extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200518
519extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
Jason Wesselff773712010-09-26 06:47:26 -0500520extern void radeon_crtc_save_lut(struct drm_crtc *crtc);
521extern void radeon_crtc_restore_lut(struct drm_crtc *crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200522extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
523 struct drm_framebuffer *old_fb);
Chris Ball4dd19b02010-09-26 06:47:23 -0500524extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
525 struct drm_framebuffer *fb,
Jason Wessel413d45d2010-09-26 06:47:25 -0500526 int x, int y, int enter);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200527extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
528 struct drm_display_mode *mode,
529 struct drm_display_mode *adjusted_mode,
530 int x, int y,
531 struct drm_framebuffer *old_fb);
532extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
533
534extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
535 struct drm_framebuffer *old_fb);
Chris Ball4dd19b02010-09-26 06:47:23 -0500536extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
537 struct drm_framebuffer *fb,
Jason Wessel413d45d2010-09-26 06:47:25 -0500538 int x, int y, int enter);
Chris Ball4dd19b02010-09-26 06:47:23 -0500539extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
540 struct drm_framebuffer *fb,
541 int x, int y, int atomic);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200542extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
543 struct drm_file *file_priv,
544 uint32_t handle,
545 uint32_t width,
546 uint32_t height);
547extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
548 int x, int y);
549
Mario Kleiner6383cf72010-10-05 19:57:36 -0400550extern int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos);
551
Alex Deucher3c537882010-02-05 04:21:19 -0500552extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
553extern struct edid *
554radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200555extern bool radeon_atom_get_clock_info(struct drm_device *dev);
556extern bool radeon_combios_get_clock_info(struct drm_device *dev);
557extern struct radeon_encoder_atom_dig *
558radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
Alex Deucherfcec5702009-11-10 21:25:07 -0500559extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
560 struct radeon_encoder_int_tmds *tmds);
561extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
562 struct radeon_encoder_int_tmds *tmds);
563extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
564 struct radeon_encoder_int_tmds *tmds);
565extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
566 struct radeon_encoder_ext_tmds *tmds);
567extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
568 struct radeon_encoder_ext_tmds *tmds);
Alex Deucher6fe7ac32009-06-12 17:26:08 +0000569extern struct radeon_encoder_primary_dac *
570radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
571extern struct radeon_encoder_tv_dac *
572radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200573extern struct radeon_encoder_lvds *
574radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200575extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
576extern struct radeon_encoder_tv_dac *
577radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
578extern struct radeon_encoder_primary_dac *
579radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
Alex Deucherfcec5702009-11-10 21:25:07 -0500580extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
581extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200582extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
583extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
584extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
585extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
Yang Zhaof657c2a2009-09-15 12:21:01 +1000586extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
587extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200588extern void
589radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
590extern void
591radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
592extern void
593radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
594extern void
595radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
596extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
597 u16 blue, int regno);
Dave Airlieb8c00ac2009-10-06 13:54:01 +1000598extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
599 u16 *blue, int regno);
Dave Airlie38651672010-03-30 05:34:13 +0000600void radeon_framebuffer_init(struct drm_device *dev,
601 struct radeon_framebuffer *rfb,
602 struct drm_mode_fb_cmd *mode_cmd,
603 struct drm_gem_object *obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200604
605int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
606bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
607bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
608void radeon_atombios_init_crtc(struct drm_device *dev,
609 struct radeon_crtc *radeon_crtc);
610void radeon_legacy_init_crtc(struct drm_device *dev,
611 struct radeon_crtc *radeon_crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200612
613void radeon_get_clock_info(struct drm_device *dev);
614
615extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
616extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
617
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200618void radeon_enc_destroy(struct drm_encoder *encoder);
619void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
620void radeon_combios_asic_init(struct drm_device *dev);
Jerome Glissec93bb852009-07-13 21:04:08 +0200621bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
622 struct drm_display_mode *mode,
623 struct drm_display_mode *adjusted_mode);
Alex Deucher35153872010-04-30 12:00:44 -0400624void radeon_panel_mode_fixup(struct drm_encoder *encoder,
625 struct drm_display_mode *adjusted_mode);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000626void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200627
Dave Airlie4ce001a2009-08-13 16:32:14 +1000628/* legacy tv */
629void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
630 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
631 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
632void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
633 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
634 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
635void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
636 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
637 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
638void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
639 struct drm_display_mode *mode,
640 struct drm_display_mode *adjusted_mode);
Dave Airlie38651672010-03-30 05:34:13 +0000641
642/* fbdev layer */
643int radeon_fbdev_init(struct radeon_device *rdev);
644void radeon_fbdev_fini(struct radeon_device *rdev);
645void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
646int radeon_fbdev_total_size(struct radeon_device *rdev);
647bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
Dave Airlieeb1f8e42010-05-07 06:42:51 +0000648
649void radeon_fb_output_poll_changed(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200650#endif